Add clang patch corresponding to r275759.
This commit is contained in:
Dimitry Andric
parent
b567315ffc
commit
be038cc81f
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=275760
241
contrib/llvm/patches/patch-r275759-clang-r221170-ppc-vaarg.diff
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241
contrib/llvm/patches/patch-r275759-clang-r221170-ppc-vaarg.diff
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@ -0,0 +1,241 @@
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Pull in r221170 from upstream clang trunk (by Roman Divacky):
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Implement vaarg lowering for ppc32. Lowering of scalars and
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aggregates is supported. Complex numbers are not.
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This adds va_args support for PowerPC (32 bit) to clang.
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Introduced here: http://svnweb.freebsd.org/changeset/base/275759
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Index: tools/clang/lib/CodeGen/TargetInfo.cpp
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===================================================================
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--- tools/clang/lib/CodeGen/TargetInfo.cpp
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+++ tools/clang/lib/CodeGen/TargetInfo.cpp
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@@ -2733,12 +2733,20 @@ llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Va
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// PowerPC-32
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-
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namespace {
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-class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
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+/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
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+class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
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public:
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- PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
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+ PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
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+ llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
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+ CodeGenFunction &CGF) const;
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+};
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+
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+class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
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+public:
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+ PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
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+
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
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// This is recovered from gcc output.
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return 1; // r1 is the dedicated stack pointer
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@@ -2750,6 +2758,96 @@ namespace {
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}
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+llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,
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+ QualType Ty,
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+ CodeGenFunction &CGF) const {
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+ if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
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+ // TODO: Implement this. For now ignore.
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+ (void)CTy;
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+ return NULL;
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+ }
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+
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+ bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
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+ bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
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+ llvm::Type *CharPtr = CGF.Int8PtrTy;
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+ llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;
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+
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+ CGBuilderTy &Builder = CGF.Builder;
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+ llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");
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+ llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);
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+ llvm::Value *FPRPtrAsInt = Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));
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+ llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);
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+ llvm::Value *OverflowAreaPtrAsInt = Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));
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+ llvm::Value *OverflowAreaPtr = Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);
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+ llvm::Value *RegsaveAreaPtrAsInt = Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));
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+ llvm::Value *RegsaveAreaPtr = Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);
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+ llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");
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+ // Align GPR when TY is i64.
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+ if (isI64) {
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+ llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));
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+ llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));
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+ llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));
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+ GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);
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+ }
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+ llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");
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+ llvm::Value *OverflowArea = Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");
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+ llvm::Value *OverflowAreaAsInt = Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);
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+ llvm::Value *RegsaveArea = Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");
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+ llvm::Value *RegsaveAreaAsInt = Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);
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+
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+ llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,
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+ Builder.getInt8(8), "cond");
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+
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+ llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,
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+ Builder.getInt8(isInt ? 4 : 8));
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+
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+ llvm::Value *OurReg = Builder.CreateAdd(RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));
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+
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+ if (Ty->isFloatingType())
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+ OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));
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+
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+ llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
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+ llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
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+ llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
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+
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+ Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
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+
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+ CGF.EmitBlock(UsingRegs);
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+
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+ llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));
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+ llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);
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+ // Increase the GPR/FPR indexes.
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+ if (isInt) {
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+ GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));
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+ Builder.CreateStore(GPR, GPRPtr);
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+ } else {
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+ FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));
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+ Builder.CreateStore(FPR, FPRPtr);
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+ }
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+ CGF.EmitBranch(Cont);
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+
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+ CGF.EmitBlock(UsingOverflow);
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+
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+ // Increase the overflow area.
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+ llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);
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+ OverflowAreaAsInt = Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));
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+ Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr), OverflowAreaPtr);
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+ CGF.EmitBranch(Cont);
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+
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+ CGF.EmitBlock(Cont);
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+
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+ llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");
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+ Result->addIncoming(Result1, UsingRegs);
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+ Result->addIncoming(Result2, UsingOverflow);
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+
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+ if (Ty->isAggregateType()) {
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+ llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr") ;
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+ return Builder.CreateLoad(AGGPtr, false, "aggr");
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+ }
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+
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+ return Result;
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+}
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+
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bool
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PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const {
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Index: tools/clang/test/CodeGen/ppc64-varargs-struct.c
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===================================================================
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--- tools/clang/test/CodeGen/ppc64-varargs-struct.c
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+++ tools/clang/test/CodeGen/ppc64-varargs-struct.c
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@@ -1,5 +1,6 @@
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// REQUIRES: ppc64-registered-target
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// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
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+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-PPC
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#include <stdarg.h>
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@@ -17,6 +18,46 @@ void testva (int n, ...)
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// CHECK: bitcast %struct.x* %t to i8*
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// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8*
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// CHECK: call void @llvm.memcpy
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+// CHECK-PPC: %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0
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+// CHECK-PPC-NEXT: %gprptr = bitcast %struct.__va_list_tag* %arraydecay to i8*
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+// CHECK-PPC-NEXT: %0 = ptrtoint i8* %gprptr to i32
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+// CHECK-PPC-NEXT: %1 = add i32 %0, 1
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+// CHECK-PPC-NEXT: %2 = inttoptr i32 %1 to i8*
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+// CHECK-PPC-NEXT: %3 = add i32 %1, 3
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+// CHECK-PPC-NEXT: %4 = inttoptr i32 %3 to i8**
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+// CHECK-PPC-NEXT: %5 = add i32 %3, 4
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+// CHECK-PPC-NEXT: %6 = inttoptr i32 %5 to i8**
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+// CHECK-PPC-NEXT: %gpr = load i8* %gprptr
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+// CHECK-PPC-NEXT: %fpr = load i8* %2
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+// CHECK-PPC-NEXT: %overflow_area = load i8** %4
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+// CHECK-PPC-NEXT: %7 = ptrtoint i8* %overflow_area to i32
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+// CHECK-PPC-NEXT: %regsave_area = load i8** %6
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+// CHECK-PPC-NEXT: %8 = ptrtoint i8* %regsave_area to i32
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+// CHECK-PPC-NEXT: %cond = icmp ult i8 %gpr, 8
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+// CHECK-PPC-NEXT: %9 = mul i8 %gpr, 4
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+// CHECK-PPC-NEXT: %10 = sext i8 %9 to i32
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+// CHECK-PPC-NEXT: %11 = add i32 %8, %10
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+// CHECK-PPC-NEXT: br i1 %cond, label %using_regs, label %using_overflow
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+//
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+// CHECK-PPC-LABEL:using_regs: ; preds = %entry
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+// CHECK-PPC-NEXT: %12 = inttoptr i32 %11 to %struct.x*
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+// CHECK-PPC-NEXT: %13 = add i8 %gpr, 1
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+// CHECK-PPC-NEXT: store i8 %13, i8* %gprptr
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+// CHECK-PPC-NEXT: br label %cont
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+//
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+// CHECK-PPC-LABEL:using_overflow: ; preds = %entry
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+// CHECK-PPC-NEXT: %14 = inttoptr i32 %7 to %struct.x*
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+// CHECK-PPC-NEXT: %15 = add i32 %7, 4
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+// CHECK-PPC-NEXT: %16 = inttoptr i32 %15 to i8*
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+// CHECK-PPC-NEXT: store i8* %16, i8** %4
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+// CHECK-PPC-NEXT: br label %cont
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+//
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+// CHECK-PPC-LABEL:cont: ; preds = %using_overflow, %using_regs
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+// CHECK-PPC-NEXT: %vaarg.addr = phi %struct.x* [ %12, %using_regs ], [ %14, %using_overflow ]
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+// CHECK-PPC-NEXT: %aggrptr = bitcast %struct.x* %vaarg.addr to i8**
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+// CHECK-PPC-NEXT: %aggr = load i8** %aggrptr
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+// CHECK-PPC-NEXT: %17 = bitcast %struct.x* %t to i8*
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+// CHECK-PPC-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %17, i8* %aggr, i32 16, i32 8, i1 false)
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int v = va_arg (ap, int);
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// CHECK: ptrtoint i8* %{{[a-z.0-9]*}} to i64
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@@ -23,8 +64,48 @@ void testva (int n, ...)
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// CHECK: add i64 %{{[0-9]+}}, 4
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// CHECK: inttoptr i64 %{{[0-9]+}} to i8*
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// CHECK: bitcast i8* %{{[0-9]+}} to i32*
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+// CHECK-PPC: %arraydecay1 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0
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+// CHECK-PPC-NEXT: %gprptr2 = bitcast %struct.__va_list_tag* %arraydecay1 to i8*
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+// CHECK-PPC-NEXT: %18 = ptrtoint i8* %gprptr2 to i32
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+// CHECK-PPC-NEXT: %19 = add i32 %18, 1
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+// CHECK-PPC-NEXT: %20 = inttoptr i32 %19 to i8*
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+// CHECK-PPC-NEXT: %21 = add i32 %19, 3
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+// CHECK-PPC-NEXT: %22 = inttoptr i32 %21 to i8**
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+// CHECK-PPC-NEXT: %23 = add i32 %21, 4
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+// CHECK-PPC-NEXT: %24 = inttoptr i32 %23 to i8**
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+// CHECK-PPC-NEXT: %gpr3 = load i8* %gprptr2
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+// CHECK-PPC-NEXT: %fpr4 = load i8* %20
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+// CHECK-PPC-NEXT: %overflow_area5 = load i8** %22
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+// CHECK-PPC-NEXT: %25 = ptrtoint i8* %overflow_area5 to i32
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+// CHECK-PPC-NEXT: %regsave_area6 = load i8** %24
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+// CHECK-PPC-NEXT: %26 = ptrtoint i8* %regsave_area6 to i32
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+// CHECK-PPC-NEXT: %cond7 = icmp ult i8 %gpr3, 8
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+// CHECK-PPC-NEXT: %27 = mul i8 %gpr3, 4
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+// CHECK-PPC-NEXT: %28 = sext i8 %27 to i32
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+// CHECK-PPC-NEXT: %29 = add i32 %26, %28
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+// CHECK-PPC-NEXT: br i1 %cond7, label %using_regs8, label %using_overflow9
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+//
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+// CHECK-PPC-LABEL:using_regs8: ; preds = %cont
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+// CHECK-PPC-NEXT: %30 = inttoptr i32 %29 to i32*
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+// CHECK-PPC-NEXT: %31 = add i8 %gpr3, 1
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+// CHECK-PPC-NEXT: store i8 %31, i8* %gprptr2
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+// CHECK-PPC-NEXT: br label %cont10
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+//
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+// CHECK-PPC-LABEL:using_overflow9: ; preds = %cont
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+// CHECK-PPC-NEXT: %32 = inttoptr i32 %25 to i32*
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+// CHECK-PPC-NEXT: %33 = add i32 %25, 4
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+// CHECK-PPC-NEXT: %34 = inttoptr i32 %33 to i8*
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+// CHECK-PPC-NEXT: store i8* %34, i8** %22
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+// CHECK-PPC-NEXT: br label %cont10
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+//
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+// CHECK-PPC-LABEL:cont10: ; preds = %using_overflow9, %using_regs8
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+// CHECK-PPC-NEXT: %vaarg.addr11 = phi i32* [ %30, %using_regs8 ], [ %32, %using_overflow9 ]
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+// CHECK-PPC-NEXT: %35 = load i32* %vaarg.addr11
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+// CHECK-PPC-NEXT: store i32 %35, i32* %v, align 4
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+#ifdef __powerpc64__
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__int128_t u = va_arg (ap, __int128_t);
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+#endif
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// CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128*
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// CHECK-NEXT: load i128* %{{[0-9]+}}
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}
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