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Update SW4 to the Intel ixl/ixlv drivers. This is primarily a shared

Browse Source 
code update, with supporting changes in the CORE. Changes for the extended
media types, VF driver has virtual channel protocol changes, and some
register use corrections.  This software change should be coordinated with
Firmware updates to your hardware, contact your support channels for that.

MFC after:	1 week
This commit is contained in:
Jack F Vogel 2015-06-05 22:52:42 +00:00
parent b1998e6914
commit be771cda12
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=284049
20 changed files with 3263 additions and 254 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
sys/dev/ixl/i40e_adminq.c
View File

@ -315,8 +315,12 @@ static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.asq.tail, 0);
/* set starting point */
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK));
if (!i40e_is_vf(hw))
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK));
if (i40e_is_vf(hw))
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
I40E_VF_ATQLEN1_ATQENABLE_MASK));
wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
@ -344,8 +348,12 @@ static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.arq.tail, 0);
/* set starting point */
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK));
if (!i40e_is_vf(hw))
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK));
if (i40e_is_vf(hw))
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
I40E_VF_ARQLEN1_ARQENABLE_MASK));
wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
@ -559,6 +567,7 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
{
enum i40e_status_code ret_code;
u16 eetrack_lo, eetrack_hi;
u16 cfg_ptr, oem_hi, oem_lo;
int retry = 0;
/* verify input for valid configuration */
if ((hw->aq.num_arq_entries == 0) ||
@ -619,6 +628,12 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
&oem_hi);
i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
&oem_lo);
hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
ret_code = I40E_ERR_FIRMWARE_API_VERSION;
@ -669,6 +684,9 @@ enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
i40e_destroy_spinlock(&hw->aq.asq_spinlock);
i40e_destroy_spinlock(&hw->aq.arq_spinlock);
if (hw->nvm_buff.va)
i40e_free_virt_mem(hw, &hw->nvm_buff);
return ret_code;
}
@ -688,16 +706,16 @@ u16 i40e_clean_asq(struct i40e_hw *hw)
desc = I40E_ADMINQ_DESC(*asq, ntc);
details = I40E_ADMINQ_DETAILS(*asq, ntc);
while (rd32(hw, hw->aq.asq.head) != ntc) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"%s: ntc %d head %d.\n", __FUNCTION__, ntc,
rd32(hw, hw->aq.asq.head));
"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
if (details->callback) {
I40E_ADMINQ_CALLBACK cb_func =
(I40E_ADMINQ_CALLBACK)details->callback;
i40e_memcpy(&desc_cb, desc,
sizeof(struct i40e_aq_desc), I40E_DMA_TO_DMA);
i40e_memcpy(&desc_cb, desc, sizeof(struct i40e_aq_desc),
I40E_DMA_TO_DMA);
cb_func(hw, &desc_cb);
}
i40e_memset(desc, 0, sizeof(*desc), I40E_DMA_MEM);
@ -755,6 +773,8 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
u16 retval = 0;
u32 val = 0;
hw->aq.asq_last_status = I40E_AQ_RC_OK;
val = rd32(hw, hw->aq.asq.head);
if (val >= hw->aq.num_asq_entries) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
@ -912,6 +932,11 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
"AQTX: desc and buffer writeback:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
/* save writeback aq if requested */
if (details->wb_desc)
i40e_memcpy(details->wb_desc, desc_on_ring,
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
/* update the error if time out occurred */
if ((!cmd_completed) &&
(!details->async && !details->postpone)) {
@ -971,7 +996,10 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
i40e_acquire_spinlock(&hw->aq.arq_spinlock);
/* set next_to_use to head */
ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
if (!i40e_is_vf(hw))
ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
if (i40e_is_vf(hw))
ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
if (ntu == ntc) {
/* nothing to do - shouldn't need to update ring's values */
ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
@ -1040,6 +1068,19 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
i40e_release_nvm(hw);
hw->aq.nvm_release_on_done = FALSE;
}
switch (hw->nvmupd_state) {
case I40E_NVMUPD_STATE_INIT_WAIT:
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
break;
case I40E_NVMUPD_STATE_WRITE_WAIT:
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
break;
default:
break;
}
}
return ret_code;
@ -1051,9 +1092,6 @@ void i40e_resume_aq(struct i40e_hw *hw)
hw->aq.asq.next_to_use = 0;
hw->aq.asq.next_to_clean = 0;
#if (I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK)
#error I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK
#endif
i40e_config_asq_regs(hw);
hw->aq.arq.next_to_use = 0;

3
sys/dev/ixl/i40e_adminq.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -77,6 +77,7 @@ struct i40e_asq_cmd_details {
u16 flags_dis;
bool async;
bool postpone;
struct i40e_aq_desc *wb_desc;
};
#define I40E_ADMINQ_DETAILS(R, i) \

123
sys/dev/ixl/i40e_adminq_cmd.h
View File

@ -42,7 +42,11 @@
*/
#define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR 0x0002
#ifdef X722_SUPPORT
#define I40E_FW_API_VERSION_MINOR 0x0003
#else
#define I40E_FW_API_VERSION_MINOR 0x0004
#endif
struct i40e_aq_desc {
__le16 flags;
@ -140,12 +144,7 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_list_func_capabilities = 0x000A,
i40e_aqc_opc_list_dev_capabilities = 0x000B,
i40e_aqc_opc_set_cppm_configuration = 0x0103,
i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
/* LAA */
i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
i40e_aqc_opc_mac_address_read = 0x0107,
i40e_aqc_opc_mac_address_write = 0x0108,
@ -240,6 +239,7 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,
i40e_aqc_opc_oem_post_update = 0x0720,
/* virtualization commands */
i40e_aqc_opc_send_msg_to_pf = 0x0801,
@ -270,7 +270,12 @@ enum i40e_admin_queue_opc {
/* Tunnel commands */
i40e_aqc_opc_add_udp_tunnel = 0x0B00,
i40e_aqc_opc_del_udp_tunnel = 0x0B01,
i40e_aqc_opc_tunnel_key_structure = 0x0B10,
#ifdef X722_SUPPORT
i40e_aqc_opc_set_rss_key = 0x0B02,
i40e_aqc_opc_set_rss_lut = 0x0B03,
i40e_aqc_opc_get_rss_key = 0x0B04,
i40e_aqc_opc_get_rss_lut = 0x0B05,
#endif
/* Async Events */
i40e_aqc_opc_event_lan_overflow = 0x1001,
@ -282,8 +287,6 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
/* debug commands */
i40e_aqc_opc_debug_get_deviceid = 0xFF00,
i40e_aqc_opc_debug_set_mode = 0xFF01,
i40e_aqc_opc_debug_read_reg = 0xFF03,
i40e_aqc_opc_debug_write_reg = 0xFF04,
i40e_aqc_opc_debug_modify_reg = 0xFF07,
@ -517,7 +520,8 @@ struct i40e_aqc_mac_address_read {
#define I40E_AQC_SAN_ADDR_VALID 0x20
#define I40E_AQC_PORT_ADDR_VALID 0x40
#define I40E_AQC_WOL_ADDR_VALID 0x80
#define I40E_AQC_ADDR_VALID_MASK 0xf0
#define I40E_AQC_MC_MAG_EN_VALID 0x100
#define I40E_AQC_ADDR_VALID_MASK 0x1F0
u8 reserved[6];
__le32 addr_high;
__le32 addr_low;
@ -540,7 +544,9 @@ struct i40e_aqc_mac_address_write {
#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
#define I40E_AQC_WRITE_TYPE_PORT 0x8000
#define I40E_AQC_WRITE_TYPE_MASK 0xc000
#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
#define I40E_AQC_WRITE_TYPE_MASK 0xC000
__le16 mac_sah;
__le32 mac_sal;
u8 reserved[8];
@ -834,8 +840,16 @@ struct i40e_aqc_vsi_properties_data {
I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
/* queueing option section */
u8 queueing_opt_flags;
#ifdef X722_SUPPORT
#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
#endif
#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
#ifdef X722_SUPPORT
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
#endif
u8 queueing_opt_reserved[3];
/* scheduler section */
u8 up_enable_bits;
@ -1076,6 +1090,7 @@ struct i40e_aqc_set_vsi_promiscuous_modes {
__le16 seid;
#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
__le16 vlan_tag;
#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
u8 reserved[8];
};
@ -1725,11 +1740,13 @@ struct i40e_aqc_get_link_status {
u8 phy_type; /* i40e_aq_phy_type */
u8 link_speed; /* i40e_aq_link_speed */
u8 link_info;
#define I40E_AQ_LINK_UP 0x01
#define I40E_AQ_LINK_UP 0x01 /* obsolete */
#define I40E_AQ_LINK_UP_FUNCTION 0x01
#define I40E_AQ_LINK_FAULT 0x02
#define I40E_AQ_LINK_FAULT_TX 0x04
#define I40E_AQ_LINK_FAULT_RX 0x08
#define I40E_AQ_LINK_FAULT_REMOTE 0x10
#define I40E_AQ_LINK_UP_PORT 0x20
#define I40E_AQ_MEDIA_AVAILABLE 0x40
#define I40E_AQ_SIGNAL_DETECT 0x80
u8 an_info;
@ -1891,6 +1908,26 @@ struct i40e_aqc_nvm_config_data_immediate_field {
I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
/* OEM Post Update (indirect 0x0720)
* no command data struct used
*/
struct i40e_aqc_nvm_oem_post_update {
#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
u8 sel_data;
u8 reserved[7];
};
I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
struct i40e_aqc_nvm_oem_post_update_buffer {
u8 str_len;
u8 dev_addr;
__le16 eeprom_addr;
u8 data[36];
};
I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
/* Send to PF command (indirect 0x0801) id is only used by PF
* Send to VF command (indirect 0x0802) id is only used by PF
* Send to Peer PF command (indirect 0x0803)
@ -2064,12 +2101,28 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
* word boundary layout issues, which the Linux compilers silently deal
* with by adding padding, making the actual struct larger than designed.
* However, the FW compiler for the NIC is less lenient and complains
* about the struct. Hence, the struct defined here has an extra byte in
* fields reserved3 and reserved4 to directly acknowledge that padding,
* and the new length is used in the length check macro.
*/
struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
u8 reserved1;
u8 oper_num_tc;
@ -2077,9 +2130,9 @@ struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
u8 reserved2;
u8 oper_tc_bw[8];
u8 oper_pfc_en;
u8 reserved3;
u8 reserved3[2];
__le16 oper_app_prio;
u8 reserved4;
u8 reserved4[2];
__le16 tlv_status;
};
@ -2168,6 +2221,48 @@ struct i40e_aqc_del_udp_tunnel_completion {
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
#ifdef X722_SUPPORT
struct i40e_aqc_get_set_rss_key {
#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
__le16 vsi_id;
u8 reserved[6];
__le32 addr_high;
__le32 addr_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
struct i40e_aqc_get_set_rss_key_data {
u8 standard_rss_key[0x28];
u8 extended_hash_key[0xc];
};
I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
struct i40e_aqc_get_set_rss_lut {
#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
__le16 vsi_id;
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
__le16 flags;
u8 reserved[4];
__le32 addr_high;
__le32 addr_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
#endif
/* tunnel key structure 0x0B10 */

653
sys/dev/ixl/i40e_common.c
View File

@ -62,9 +62,24 @@ enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
case I40E_DEV_ID_QSFP_B:
case I40E_DEV_ID_QSFP_C:
case I40E_DEV_ID_10G_BASE_T:
case I40E_DEV_ID_10G_BASE_T4:
case I40E_DEV_ID_20G_KR2:
case I40E_DEV_ID_20G_KR2_A:
hw->mac.type = I40E_MAC_XL710;
break;
#ifdef X722_SUPPORT
case I40E_DEV_ID_SFP_X722:
case I40E_DEV_ID_1G_BASE_T_X722:
case I40E_DEV_ID_10G_BASE_T_X722:
hw->mac.type = I40E_MAC_X722;
break;
#endif
#ifdef X722_SUPPORT
case I40E_DEV_ID_X722_VF:
case I40E_DEV_ID_X722_VF_HV:
hw->mac.type = I40E_MAC_X722_VF;
break;
#endif
case I40E_DEV_ID_VF:
case I40E_DEV_ID_VF_HV:
hw->mac.type = I40E_MAC_VF;
@ -82,6 +97,212 @@ enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
return status;
}
/**
* i40e_aq_str - convert AQ err code to a string
* @hw: pointer to the HW structure
* @aq_err: the AQ error code to convert
**/
char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
{
switch (aq_err) {
case I40E_AQ_RC_OK:
return "OK";
case I40E_AQ_RC_EPERM:
return "I40E_AQ_RC_EPERM";
case I40E_AQ_RC_ENOENT:
return "I40E_AQ_RC_ENOENT";
case I40E_AQ_RC_ESRCH:
return "I40E_AQ_RC_ESRCH";
case I40E_AQ_RC_EINTR:
return "I40E_AQ_RC_EINTR";
case I40E_AQ_RC_EIO:
return "I40E_AQ_RC_EIO";
case I40E_AQ_RC_ENXIO:
return "I40E_AQ_RC_ENXIO";
case I40E_AQ_RC_E2BIG:
return "I40E_AQ_RC_E2BIG";
case I40E_AQ_RC_EAGAIN:
return "I40E_AQ_RC_EAGAIN";
case I40E_AQ_RC_ENOMEM:
return "I40E_AQ_RC_ENOMEM";
case I40E_AQ_RC_EACCES:
return "I40E_AQ_RC_EACCES";
case I40E_AQ_RC_EFAULT:
return "I40E_AQ_RC_EFAULT";
case I40E_AQ_RC_EBUSY:
return "I40E_AQ_RC_EBUSY";
case I40E_AQ_RC_EEXIST:
return "I40E_AQ_RC_EEXIST";
case I40E_AQ_RC_EINVAL:
return "I40E_AQ_RC_EINVAL";
case I40E_AQ_RC_ENOTTY:
return "I40E_AQ_RC_ENOTTY";
case I40E_AQ_RC_ENOSPC:
return "I40E_AQ_RC_ENOSPC";
case I40E_AQ_RC_ENOSYS:
return "I40E_AQ_RC_ENOSYS";
case I40E_AQ_RC_ERANGE:
return "I40E_AQ_RC_ERANGE";
case I40E_AQ_RC_EFLUSHED:
return "I40E_AQ_RC_EFLUSHED";
case I40E_AQ_RC_BAD_ADDR:
return "I40E_AQ_RC_BAD_ADDR";
case I40E_AQ_RC_EMODE:
return "I40E_AQ_RC_EMODE";
case I40E_AQ_RC_EFBIG:
return "I40E_AQ_RC_EFBIG";
}
snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
return hw->err_str;
}
/**
* i40e_stat_str - convert status err code to a string
* @hw: pointer to the HW structure
* @stat_err: the status error code to convert
**/
char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
{
switch (stat_err) {
case I40E_SUCCESS:
return "OK";
case I40E_ERR_NVM:
return "I40E_ERR_NVM";
case I40E_ERR_NVM_CHECKSUM:
return "I40E_ERR_NVM_CHECKSUM";
case I40E_ERR_PHY:
return "I40E_ERR_PHY";
case I40E_ERR_CONFIG:
return "I40E_ERR_CONFIG";
case I40E_ERR_PARAM:
return "I40E_ERR_PARAM";
case I40E_ERR_MAC_TYPE:
return "I40E_ERR_MAC_TYPE";
case I40E_ERR_UNKNOWN_PHY:
return "I40E_ERR_UNKNOWN_PHY";
case I40E_ERR_LINK_SETUP:
return "I40E_ERR_LINK_SETUP";
case I40E_ERR_ADAPTER_STOPPED:
return "I40E_ERR_ADAPTER_STOPPED";
case I40E_ERR_INVALID_MAC_ADDR:
return "I40E_ERR_INVALID_MAC_ADDR";
case I40E_ERR_DEVICE_NOT_SUPPORTED:
return "I40E_ERR_DEVICE_NOT_SUPPORTED";
case I40E_ERR_MASTER_REQUESTS_PENDING:
return "I40E_ERR_MASTER_REQUESTS_PENDING";
case I40E_ERR_INVALID_LINK_SETTINGS:
return "I40E_ERR_INVALID_LINK_SETTINGS";
case I40E_ERR_AUTONEG_NOT_COMPLETE:
return "I40E_ERR_AUTONEG_NOT_COMPLETE";
case I40E_ERR_RESET_FAILED:
return "I40E_ERR_RESET_FAILED";
case I40E_ERR_SWFW_SYNC:
return "I40E_ERR_SWFW_SYNC";
case I40E_ERR_NO_AVAILABLE_VSI:
return "I40E_ERR_NO_AVAILABLE_VSI";
case I40E_ERR_NO_MEMORY:
return "I40E_ERR_NO_MEMORY";
case I40E_ERR_BAD_PTR:
return "I40E_ERR_BAD_PTR";
case I40E_ERR_RING_FULL:
return "I40E_ERR_RING_FULL";
case I40E_ERR_INVALID_PD_ID:
return "I40E_ERR_INVALID_PD_ID";
case I40E_ERR_INVALID_QP_ID:
return "I40E_ERR_INVALID_QP_ID";
case I40E_ERR_INVALID_CQ_ID:
return "I40E_ERR_INVALID_CQ_ID";
case I40E_ERR_INVALID_CEQ_ID:
return "I40E_ERR_INVALID_CEQ_ID";
case I40E_ERR_INVALID_AEQ_ID:
return "I40E_ERR_INVALID_AEQ_ID";
case I40E_ERR_INVALID_SIZE:
return "I40E_ERR_INVALID_SIZE";
case I40E_ERR_INVALID_ARP_INDEX:
return "I40E_ERR_INVALID_ARP_INDEX";
case I40E_ERR_INVALID_FPM_FUNC_ID:
return "I40E_ERR_INVALID_FPM_FUNC_ID";
case I40E_ERR_QP_INVALID_MSG_SIZE:
return "I40E_ERR_QP_INVALID_MSG_SIZE";
case I40E_ERR_QP_TOOMANY_WRS_POSTED:
return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
case I40E_ERR_INVALID_FRAG_COUNT:
return "I40E_ERR_INVALID_FRAG_COUNT";
case I40E_ERR_QUEUE_EMPTY:
return "I40E_ERR_QUEUE_EMPTY";
case I40E_ERR_INVALID_ALIGNMENT:
return "I40E_ERR_INVALID_ALIGNMENT";
case I40E_ERR_FLUSHED_QUEUE:
return "I40E_ERR_FLUSHED_QUEUE";
case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
case I40E_ERR_INVALID_IMM_DATA_SIZE:
return "I40E_ERR_INVALID_IMM_DATA_SIZE";
case I40E_ERR_TIMEOUT:
return "I40E_ERR_TIMEOUT";
case I40E_ERR_OPCODE_MISMATCH:
return "I40E_ERR_OPCODE_MISMATCH";
case I40E_ERR_CQP_COMPL_ERROR:
return "I40E_ERR_CQP_COMPL_ERROR";
case I40E_ERR_INVALID_VF_ID:
return "I40E_ERR_INVALID_VF_ID";
case I40E_ERR_INVALID_HMCFN_ID:
return "I40E_ERR_INVALID_HMCFN_ID";
case I40E_ERR_BACKING_PAGE_ERROR:
return "I40E_ERR_BACKING_PAGE_ERROR";
case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
case I40E_ERR_INVALID_PBLE_INDEX:
return "I40E_ERR_INVALID_PBLE_INDEX";
case I40E_ERR_INVALID_SD_INDEX:
return "I40E_ERR_INVALID_SD_INDEX";
case I40E_ERR_INVALID_PAGE_DESC_INDEX:
return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
case I40E_ERR_INVALID_SD_TYPE:
return "I40E_ERR_INVALID_SD_TYPE";
case I40E_ERR_MEMCPY_FAILED:
return "I40E_ERR_MEMCPY_FAILED";
case I40E_ERR_INVALID_HMC_OBJ_INDEX:
return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
case I40E_ERR_INVALID_HMC_OBJ_COUNT:
return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
case I40E_ERR_SRQ_ENABLED:
return "I40E_ERR_SRQ_ENABLED";
case I40E_ERR_ADMIN_QUEUE_ERROR:
return "I40E_ERR_ADMIN_QUEUE_ERROR";
case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
case I40E_ERR_BUF_TOO_SHORT:
return "I40E_ERR_BUF_TOO_SHORT";
case I40E_ERR_ADMIN_QUEUE_FULL:
return "I40E_ERR_ADMIN_QUEUE_FULL";
case I40E_ERR_ADMIN_QUEUE_NO_WORK:
return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
case I40E_ERR_BAD_IWARP_CQE:
return "I40E_ERR_BAD_IWARP_CQE";
case I40E_ERR_NVM_BLANK_MODE:
return "I40E_ERR_NVM_BLANK_MODE";
case I40E_ERR_NOT_IMPLEMENTED:
return "I40E_ERR_NOT_IMPLEMENTED";
case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
case I40E_ERR_DIAG_TEST_FAILED:
return "I40E_ERR_DIAG_TEST_FAILED";
case I40E_ERR_NOT_READY:
return "I40E_ERR_NOT_READY";
case I40E_NOT_SUPPORTED:
return "I40E_NOT_SUPPORTED";
case I40E_ERR_FIRMWARE_API_VERSION:
return "I40E_ERR_FIRMWARE_API_VERSION";
}
snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
return hw->err_str;
}
/**
* i40e_debug_aq
* @hw: debug mask related to admin queue
@ -154,9 +375,13 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
bool i40e_check_asq_alive(struct i40e_hw *hw)
{
if (hw->aq.asq.len)
return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
else
return FALSE;
if (!i40e_is_vf(hw))
return !!(rd32(hw, hw->aq.asq.len) &
I40E_PF_ATQLEN_ATQENABLE_MASK);
if (i40e_is_vf(hw))
return !!(rd32(hw, hw->aq.asq.len) &
I40E_VF_ATQLEN1_ATQENABLE_MASK);
return FALSE;
}
/**
@ -184,6 +409,171 @@ enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
return status;
}
#ifdef X722_SUPPORT
/**
* i40e_aq_get_set_rss_lut
* @hw: pointer to the hardware structure
* @vsi_id: vsi fw index
* @pf_lut: for PF table set TRUE, for VSI table set FALSE
* @lut: pointer to the lut buffer provided by the caller
* @lut_size: size of the lut buffer
* @set: set TRUE to set the table, FALSE to get the table
*
* Internal function to get or set RSS look up table
**/
static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
u16 vsi_id, bool pf_lut,
u8 *lut, u16 lut_size,
bool set)
{
enum i40e_status_code status;
struct i40e_aq_desc desc;
struct i40e_aqc_get_set_rss_lut *cmd_resp =
(struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
if (set)
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_rss_lut);
else
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_get_rss_lut);
/* Indirect command */
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
cmd_resp->vsi_id =
CPU_TO_LE16((u16)((vsi_id <<
I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
if (pf_lut)
cmd_resp->flags |= CPU_TO_LE16((u16)
((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
else
cmd_resp->flags |= CPU_TO_LE16((u16)
((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)lut));
cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)lut));
status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
return status;
}
/**
* i40e_aq_get_rss_lut
* @hw: pointer to the hardware structure
* @vsi_id: vsi fw index
* @pf_lut: for PF table set TRUE, for VSI table set FALSE
* @lut: pointer to the lut buffer provided by the caller
* @lut_size: size of the lut buffer
*
* get the RSS lookup table, PF or VSI type
**/
enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
bool pf_lut, u8 *lut, u16 lut_size)
{
return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
FALSE);
}
/**
* i40e_aq_set_rss_lut
* @hw: pointer to the hardware structure
* @vsi_id: vsi fw index
* @pf_lut: for PF table set TRUE, for VSI table set FALSE
* @lut: pointer to the lut buffer provided by the caller
* @lut_size: size of the lut buffer
*
* set the RSS lookup table, PF or VSI type
**/
enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
bool pf_lut, u8 *lut, u16 lut_size)
{
return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
}
/**
* i40e_aq_get_set_rss_key
* @hw: pointer to the hw struct
* @vsi_id: vsi fw index
* @key: pointer to key info struct
* @set: set TRUE to set the key, FALSE to get the key
*
* get the RSS key per VSI
**/
static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
u16 vsi_id,
struct i40e_aqc_get_set_rss_key_data *key,
bool set)
{
enum i40e_status_code status;
struct i40e_aq_desc desc;
struct i40e_aqc_get_set_rss_key *cmd_resp =
(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
if (set)
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_rss_key);
else
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_get_rss_key);
/* Indirect command */
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
cmd_resp->vsi_id =
CPU_TO_LE16((u16)((vsi_id <<
I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)key));
cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)key));
status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
return status;
}
/**
* i40e_aq_get_rss_key
* @hw: pointer to the hw struct
* @vsi_id: vsi fw index
* @key: pointer to key info struct
*
**/
enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
u16 vsi_id,
struct i40e_aqc_get_set_rss_key_data *key)
{
return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
}
/**
* i40e_aq_set_rss_key
* @hw: pointer to the hw struct
* @vsi_id: vsi fw index
* @key: pointer to key info struct
*
* set the RSS key per VSI
**/
enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
u16 vsi_id,
struct i40e_aqc_get_set_rss_key_data *key)
{
return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
}
#endif /* X722_SUPPORT */
/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
* hardware to a bit-field that can be used by SW to more easily determine the
@ -598,6 +988,9 @@ enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
switch (hw->mac.type) {
case I40E_MAC_XL710:
#ifdef X722_SUPPORT
case I40E_MAC_X722:
#endif
break;
default:
return I40E_ERR_DEVICE_NOT_SUPPORTED;
@ -888,7 +1281,7 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
for (cnt = 0; cnt < grst_del + 2; cnt++) {
for (cnt = 0; cnt < grst_del + 10; cnt++) {
reg = rd32(hw, I40E_GLGEN_RSTAT);
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
break;
@ -1108,9 +1501,11 @@ u32 i40e_led_get(struct i40e_hw *hw)
if (!gpio_val)
continue;
/* ignore gpio LED src mode entries related to the activity LEDs */
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
/* ignore gpio LED src mode entries related to the activity
* LEDs
*/
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
switch (current_mode) {
case I40E_COMBINED_ACTIVITY:
case I40E_FILTER_ACTIVITY:
@ -1154,9 +1549,11 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
if (!gpio_val)
continue;
/* ignore gpio LED src mode entries related to the activity LEDs */
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
/* ignore gpio LED src mode entries related to the activity
* LEDs
*/
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
switch (current_mode) {
case I40E_COMBINED_ACTIVITY:
case I40E_FILTER_ACTIVITY:
@ -1175,9 +1572,9 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
blink = FALSE;
if (blink)
gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
else
gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
break;
@ -1329,14 +1726,14 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
}
/* Update the link info */
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
status = i40e_update_link_info(hw);
if (status) {
/* Wait a little bit (on 40G cards it sometimes takes a really
* long time for link to come back from the atomic reset)
* and try once more
*/
i40e_msec_delay(1000);
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
status = i40e_update_link_info(hw);
}
if (status)
*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
@ -1525,7 +1922,6 @@ enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
return status;
}
/**
* i40e_aq_set_phy_int_mask
* @hw: pointer to the hw struct
@ -1836,6 +2232,74 @@ enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
return status;
}
/**
* i40e_aq_set_vsi_mc_promisc_on_vlan
* @hw: pointer to the hw struct
* @seid: vsi number
* @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
* @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
* @cmd_details: pointer to command details structure or NULL
**/
enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
u16 seid, bool enable, u16 vid,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
enum i40e_status_code status;
u16 flags = 0;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_vsi_promiscuous_modes);
if (enable)
flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
cmd->seid = CPU_TO_LE16(seid);
cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_aq_set_vsi_uc_promisc_on_vlan
* @hw: pointer to the hw struct
* @seid: vsi number
* @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
* @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
* @cmd_details: pointer to command details structure or NULL
**/
enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
u16 seid, bool enable, u16 vid,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
enum i40e_status_code status;
u16 flags = 0;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_vsi_promiscuous_modes);
if (enable)
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
cmd->seid = CPU_TO_LE16(seid);
cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_aq_set_vsi_broadcast
* @hw: pointer to the hw struct
@ -2067,29 +2531,55 @@ enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
/**
* i40e_get_link_status - get status of the HW network link
* @hw: pointer to the hw struct
* @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
*
* Returns TRUE if link is up, FALSE if link is down.
* Variable link_up TRUE if link is up, FALSE if link is down.
* The variable link_up is invalid if returned value of status != I40E_SUCCESS
*
* Side effect: LinkStatusEvent reporting becomes enabled
**/
bool i40e_get_link_status(struct i40e_hw *hw)
enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
{
enum i40e_status_code status = I40E_SUCCESS;
bool link_status = FALSE;
if (hw->phy.get_link_info) {
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
status = i40e_update_link_info(hw);
if (status != I40E_SUCCESS)
goto i40e_get_link_status_exit;
i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
status);
}
link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
i40e_get_link_status_exit:
return link_status;
return status;
}
/**
* i40e_updatelink_status - update status of the HW network link
* @hw: pointer to the hw struct
**/
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
{
struct i40e_aq_get_phy_abilities_resp abilities;
enum i40e_status_code status = I40E_SUCCESS;
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
if (status)
return status;
status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
NULL);
if (status)
return status;
memcpy(hw->phy.link_info.module_type, &abilities.module_type,
sizeof(hw->phy.link_info.module_type));
return status;
}
/**
* i40e_get_link_speed
* @hw: pointer to the hw struct
@ -2218,6 +2708,7 @@ enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
*vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
if (floating) {
u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
if (flags & I40E_AQC_ADD_VEB_FLOATING)
*floating = TRUE;
else
@ -2749,6 +3240,27 @@ enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
return status;
}
/**
* i40e_aq_oem_post_update - triggers an OEM specific flow after update
* @hw: pointer to the hw struct
* @cmd_details: pointer to command details structure or NULL
**/
enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
void *buff, u16 buff_size,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
enum i40e_status_code status;
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
status = I40E_ERR_NOT_IMPLEMENTED;
return status;
}
/**
* i40e_aq_erase_nvm
* @hw: pointer to the hw struct
@ -2813,12 +3325,13 @@ enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
#define I40E_DEV_FUNC_CAP_FLEX10 0xF1
#define I40E_DEV_FUNC_CAP_CEM 0xF2
#define I40E_DEV_FUNC_CAP_IWARP 0x51
#define I40E_DEV_FUNC_CAP_LED 0x61
#define I40E_DEV_FUNC_CAP_SDP 0x62
#define I40E_DEV_FUNC_CAP_MDIO 0x63
#define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
/**
* i40e_parse_discover_capabilities
@ -2837,6 +3350,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
u32 valid_functions, num_functions;
u32 number, logical_id, phys_id;
struct i40e_hw_capabilities *p;
u8 major_rev;
u32 i = 0;
u16 id;
@ -2854,6 +3368,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
number = LE32_TO_CPU(cap->number);
logical_id = LE32_TO_CPU(cap->logical_id);
phys_id = LE32_TO_CPU(cap->phys_id);
major_rev = cap->major_rev;
switch (id) {
case I40E_DEV_FUNC_CAP_SWITCH_MODE:
@ -2928,9 +3443,21 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
case I40E_DEV_FUNC_CAP_MSIX_VF:
p->num_msix_vectors_vf = number;
break;
case I40E_DEV_FUNC_CAP_MFP_MODE_1:
if (number == 1)
p->mfp_mode_1 = TRUE;
case I40E_DEV_FUNC_CAP_FLEX10:
if (major_rev == 1) {
if (number == 1) {
p->flex10_enable = TRUE;
p->flex10_capable = TRUE;
}
} else {
/* Capability revision >= 2 */
if (number & 1)
p->flex10_enable = TRUE;
if (number & 2)
p->flex10_capable = TRUE;
}
p->flex10_mode = logical_id;
p->flex10_status = phys_id;
break;
case I40E_DEV_FUNC_CAP_CEM:
if (number == 1)
@ -2963,11 +3490,18 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
p->fd_filters_guaranteed = number;
p->fd_filters_best_effort = logical_id;
break;
case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
p->wr_csr_prot = (u64)number;
p->wr_csr_prot |= (u64)logical_id << 32;
break;
default:
break;
}
}
if (p->fcoe)
i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
/* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
p->fcoe = FALSE;
@ -4922,6 +5456,63 @@ void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
}
}
/**
* i40e_aq_debug_dump
* @hw: pointer to the hardware structure
* @cluster_id: specific cluster to dump
* @table_id: table id within cluster
* @start_index: index of line in the block to read
* @buff_size: dump buffer size
* @buff: dump buffer
* @ret_buff_size: actual buffer size returned
* @ret_next_table: next block to read
* @ret_next_index: next index to read
*
* Dump internal FW/HW data for debug purposes.
*
**/
enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
u8 table_id, u32 start_index, u16 buff_size,
void *buff, u16 *ret_buff_size,
u8 *ret_next_table, u32 *ret_next_index,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_debug_dump_internals *cmd =
(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
struct i40e_aqc_debug_dump_internals *resp =
(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
enum i40e_status_code status;
if (buff_size == 0 || !buff)
return I40E_ERR_PARAM;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_debug_dump_internals);
/* Indirect Command */
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
cmd->cluster_id = cluster_id;
cmd->table_id = table_id;
cmd->idx = CPU_TO_LE32(start_index);
desc.datalen = CPU_TO_LE16(buff_size);
status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
if (!status) {
if (ret_buff_size != NULL)
*ret_buff_size = LE16_TO_CPU(desc.datalen);
if (ret_next_table != NULL)
*ret_next_table = resp->table_id;
if (ret_next_index != NULL)
*ret_next_index = LE32_TO_CPU(resp->idx);
}
return status;
}
/**
* i40e_read_bw_from_alt_ram
* @hw: pointer to the hardware structure
@ -4941,11 +5532,11 @@ enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
/* Calculate the address of the min/max bw registers */
max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
I40E_ALT_STRUCT_MAX_BW_OFFSET +
(I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
I40E_ALT_STRUCT_MAX_BW_OFFSET +
(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
I40E_ALT_STRUCT_MIN_BW_OFFSET +
(I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
I40E_ALT_STRUCT_MIN_BW_OFFSET +
(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
/* Read the bandwidths from alt ram */
status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,

68
sys/dev/ixl/i40e_devids.h Normal file
View File

@ -0,0 +1,68 @@
/******************************************************************************
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD$*/
#ifndef _I40E_DEVIDS_H_
#define _I40E_DEVIDS_H_
/* Vendor ID */
#define I40E_INTEL_VENDOR_ID 0x8086
/* Device IDs */
#define I40E_DEV_ID_SFP_XL710 0x1572
#define I40E_DEV_ID_QEMU 0x1574
#define I40E_DEV_ID_KX_A 0x157F
#define I40E_DEV_ID_KX_B 0x1580
#define I40E_DEV_ID_KX_C 0x1581
#define I40E_DEV_ID_QSFP_A 0x1583
#define I40E_DEV_ID_QSFP_B 0x1584
#define I40E_DEV_ID_QSFP_C 0x1585
#define I40E_DEV_ID_10G_BASE_T 0x1586
#define I40E_DEV_ID_20G_KR2 0x1587
#define I40E_DEV_ID_20G_KR2_A 0x1588
#define I40E_DEV_ID_10G_BASE_T4 0x1589
#define I40E_DEV_ID_VF 0x154C
#define I40E_DEV_ID_VF_HV 0x1571
#ifdef X722_SUPPORT
#define I40E_DEV_ID_SFP_X722 0x37D0
#define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
#define I40E_DEV_ID_X722_VF 0x37CD
#define I40E_DEV_ID_X722_VF_HV 0x37D9
#endif /* X722_SUPPORT */
#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
(d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C)
#endif /* _I40E_DEVIDS_H_ */

69
sys/dev/ixl/i40e_hmc.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -130,6 +130,7 @@ enum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,
* @hw: pointer to our HW structure
* @hmc_info: pointer to the HMC configuration information structure
* @pd_index: which page descriptor index to manipulate
* @rsrc_pg: if not NULL, use preallocated page instead of allocating new one.
*
* This function:
* 1. Initializes the pd entry
@ -143,12 +144,14 @@ enum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,
**/
enum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,
struct i40e_hmc_info *hmc_info,
u32 pd_index)
u32 pd_index,
struct i40e_dma_mem *rsrc_pg)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
struct i40e_hmc_pd_table *pd_table;
struct i40e_hmc_pd_entry *pd_entry;
struct i40e_dma_mem mem;
struct i40e_dma_mem *page = &mem;
u32 sd_idx, rel_pd_idx;
u64 *pd_addr;
u64 page_desc;
@ -169,19 +172,25 @@ enum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,
pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
pd_entry = &pd_table->pd_entry[rel_pd_idx];
if (!pd_entry->valid) {
/* allocate a 4K backing page */
ret_code = i40e_allocate_dma_mem(hw, &mem, i40e_mem_bp,
I40E_HMC_PAGED_BP_SIZE,
I40E_HMC_PD_BP_BUF_ALIGNMENT);
if (ret_code)
goto exit;
if (rsrc_pg) {
pd_entry->rsrc_pg = TRUE;
page = rsrc_pg;
} else {
/* allocate a 4K backing page */
ret_code = i40e_allocate_dma_mem(hw, page, i40e_mem_bp,
I40E_HMC_PAGED_BP_SIZE,
I40E_HMC_PD_BP_BUF_ALIGNMENT);
if (ret_code)
goto exit;
pd_entry->rsrc_pg = FALSE;
}
i40e_memcpy(&pd_entry->bp.addr, &mem,
i40e_memcpy(&pd_entry->bp.addr, page,
sizeof(struct i40e_dma_mem), I40E_NONDMA_TO_NONDMA);
pd_entry->bp.sd_pd_index = pd_index;
pd_entry->bp.entry_type = I40E_SD_TYPE_PAGED;
/* Set page address and valid bit */
page_desc = mem.pa | 0x1;
page_desc = page->pa | 0x1;
pd_addr = (u64 *)pd_table->pd_page_addr.va;
pd_addr += rel_pd_idx;
@ -256,7 +265,8 @@ enum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,
I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, idx);
/* free memory here */
ret_code = i40e_free_dma_mem(hw, &(pd_entry->bp.addr));
if (!pd_entry->rsrc_pg)
ret_code = i40e_free_dma_mem(hw, &(pd_entry->bp.addr));
if (I40E_SUCCESS != ret_code)
goto exit;
if (!pd_table->ref_cnt)
@ -303,21 +313,15 @@ enum i40e_status_code i40e_remove_sd_bp_new(struct i40e_hw *hw,
u32 idx, bool is_pf)
{
struct i40e_hmc_sd_entry *sd_entry;
enum i40e_status_code ret_code = I40E_SUCCESS;
if (!is_pf)
return I40E_NOT_SUPPORTED;
/* get the entry and decrease its ref counter */
sd_entry = &hmc_info->sd_table.sd_entry[idx];
if (is_pf) {
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_DIRECT);
} else {
ret_code = I40E_NOT_SUPPORTED;
goto exit;
}
ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.bp.addr));
if (I40E_SUCCESS != ret_code)
goto exit;
exit:
return ret_code;
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_DIRECT);
return i40e_free_dma_mem(hw, &(sd_entry->u.bp.addr));
}
/**
@ -357,20 +361,13 @@ enum i40e_status_code i40e_remove_pd_page_new(struct i40e_hw *hw,
struct i40e_hmc_info *hmc_info,
u32 idx, bool is_pf)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
struct i40e_hmc_sd_entry *sd_entry;
if (!is_pf)
return I40E_NOT_SUPPORTED;
sd_entry = &hmc_info->sd_table.sd_entry[idx];
if (is_pf) {
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_PAGED);
} else {
ret_code = I40E_NOT_SUPPORTED;
goto exit;
}
/* free memory here */
ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.pd_table.pd_page_addr));
if (I40E_SUCCESS != ret_code)
goto exit;
exit:
return ret_code;
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_PAGED);
return i40e_free_dma_mem(hw, &(sd_entry->u.pd_table.pd_page_addr));
}

12
sys/dev/ixl/i40e_hmc.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -70,6 +70,7 @@ struct i40e_hmc_bp {
struct i40e_hmc_pd_entry {
struct i40e_hmc_bp bp;
u32 sd_index;
bool rsrc_pg;
bool valid;
};
@ -134,8 +135,8 @@ struct i40e_hmc_info {
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
wr32((hw), I40E_PFHMC_SDCMD, val3); \
@ -154,7 +155,7 @@ struct i40e_hmc_info {
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
wr32((hw), I40E_PFHMC_SDCMD, val3); \
@ -226,7 +227,8 @@ enum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,
enum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,
struct i40e_hmc_info *hmc_info,
u32 pd_index);
u32 pd_index,
struct i40e_dma_mem *rsrc_pg);
enum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,
struct i40e_hmc_info *hmc_info,
u32 idx);

29
sys/dev/ixl/i40e_lan_hmc.c
View File

@ -137,7 +137,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
obj->cnt = txq_num;
obj->base = 0;
size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
obj->size = (u64)1 << size_exp;
obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (txq_num > obj->max_cnt) {
@ -160,7 +160,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
obj->size = (u64)1 << size_exp;
obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (rxq_num > obj->max_cnt) {
@ -183,7 +183,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
obj->size = (u64)1 << size_exp;
obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (fcoe_cntx_num > obj->max_cnt) {
@ -206,7 +206,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
obj->size = (u64)1 << size_exp;
obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (fcoe_filt_num > obj->max_cnt) {
@ -395,7 +395,7 @@ enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
/* update the pd table entry */
ret_code = i40e_add_pd_table_entry(hw,
info->hmc_info,
i);
i, NULL);
if (I40E_SUCCESS != ret_code) {
pd_error = TRUE;
break;
@ -439,9 +439,8 @@ enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
pd_idx1 = max(pd_idx,
((j - 1) * I40E_HMC_MAX_BP_COUNT));
pd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));
for (i = pd_idx1; i < pd_lmt1; i++) {
for (i = pd_idx1; i < pd_lmt1; i++)
i40e_remove_pd_bp(hw, info->hmc_info, i);
}
i40e_remove_pd_page(hw, info->hmc_info, (j - 1));
break;
case I40E_SD_TYPE_DIRECT:
@ -771,7 +770,7 @@ static void i40e_write_byte(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u8)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
src_byte = *from;
src_byte &= mask;
@ -812,7 +811,7 @@ static void i40e_write_word(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u16)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
/* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines
@ -862,7 +861,7 @@ static void i40e_write_dword(u8 *hmc_bits,
* to 5 bits so the shift will do nothing
*/
if (ce_info->width < 32)
mask = ((u32)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
else
mask = ~(u32)0;
@ -914,7 +913,7 @@ static void i40e_write_qword(u8 *hmc_bits,
* to 6 bits so the shift will do nothing
*/
if (ce_info->width < 64)
mask = ((u64)1 << ce_info->width) - 1;
mask = BIT_ULL(ce_info->width) - 1;
else
mask = ~(u64)0;
@ -956,7 +955,7 @@ static void i40e_read_byte(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u8)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
/* shift to correct alignment */
mask <<= shift_width;
@ -994,7 +993,7 @@ static void i40e_read_word(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u16)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
/* shift to correct alignment */
mask <<= shift_width;
@ -1044,7 +1043,7 @@ static void i40e_read_dword(u8 *hmc_bits,
* to 5 bits so the shift will do nothing
*/
if (ce_info->width < 32)
mask = ((u32)1 << ce_info->width) - 1;
mask = BIT(ce_info->width) - 1;
else
mask = ~(u32)0;
@ -1097,7 +1096,7 @@ static void i40e_read_qword(u8 *hmc_bits,
* to 6 bits so the shift will do nothing
*/
if (ce_info->width < 64)
mask = ((u64)1 << ce_info->width) - 1;
mask = BIT_ULL(ce_info->width) - 1;
else
mask = ~(u64)0;

53
sys/dev/ixl/i40e_nvm.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -72,7 +72,7 @@ enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
I40E_GLNVM_GENS_SR_SIZE_SHIFT);
/* Switching to words (sr_size contains power of 2KB) */
nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
/* Check if we are in the normal or blank NVM programming mode */
fla = rd32(hw, I40E_GLNVM_FLA);
@ -158,10 +158,26 @@ enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
**/
void i40e_release_nvm(struct i40e_hw *hw)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
u32 total_delay = 0;
DEBUGFUNC("i40e_release_nvm");
if (!hw->nvm.blank_nvm_mode)
i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
if (hw->nvm.blank_nvm_mode)
return;
ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
/* there are some rare cases when trying to release the resource
* results in an admin Q timeout, so handle them correctly
*/
while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
(total_delay < hw->aq.asq_cmd_timeout)) {
i40e_msec_delay(1);
ret_code = i40e_aq_release_resource(hw,
I40E_NVM_RESOURCE_ID, 0, NULL);
total_delay++;
}
}
/**
@ -202,6 +218,10 @@ static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
u16 *data)
{
#ifdef X722_SUPPORT
if (hw->mac.type == I40E_MAC_X722)
return i40e_read_nvm_word_aq(hw, offset, data);
#endif
return i40e_read_nvm_word_srctl(hw, offset, data);
}
@ -233,8 +253,8 @@ enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
ret_code = i40e_poll_sr_srctl_done_bit(hw);
if (ret_code == I40E_SUCCESS) {
/* Write the address and start reading */
sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
(1 << I40E_GLNVM_SRCTL_START_SHIFT);
sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
BIT(I40E_GLNVM_SRCTL_START_SHIFT);
wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
/* Poll I40E_GLNVM_SRCTL until the done bit is set */
@ -290,6 +310,10 @@ enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
u16 *words, u16 *data)
{
#ifdef X722_SUPPORT
if (hw->mac.type == I40E_MAC_X722)
return i40e_read_nvm_buffer_aq(hw, offset, words, data);
#endif
return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
}
@ -401,9 +425,13 @@ enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
bool last_command)
{
enum i40e_status_code ret_code = I40E_ERR_NVM;
struct i40e_asq_cmd_details cmd_details;
DEBUGFUNC("i40e_read_nvm_aq");
memset(&cmd_details, 0, sizeof(cmd_details));
cmd_details.wb_desc = &hw->nvm_wb_desc;
/* Here we are checking the SR limit only for the flat memory model.
* We cannot do it for the module-based model, as we did not acquire
* the NVM resource yet (we cannot get the module pointer value).
@ -428,7 +456,7 @@ enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
ret_code = i40e_aq_read_nvm(hw, module_pointer,
2 * offset, /*bytes*/
2 * words, /*bytes*/
data, last_command, NULL);
data, last_command, &cmd_details);
return ret_code;
}
@ -449,9 +477,13 @@ enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
bool last_command)
{
enum i40e_status_code ret_code = I40E_ERR_NVM;
struct i40e_asq_cmd_details cmd_details;
DEBUGFUNC("i40e_write_nvm_aq");
memset(&cmd_details, 0, sizeof(cmd_details));
cmd_details.wb_desc = &hw->nvm_wb_desc;
/* Here we are checking the SR limit only for the flat memory model.
* We cannot do it for the module-based model, as we did not acquire
* the NVM resource yet (we cannot get the module pointer value).
@ -470,7 +502,7 @@ enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
ret_code = i40e_aq_update_nvm(hw, module_pointer,
2 * offset, /*bytes*/
2 * words, /*bytes*/
data, last_command, NULL);
data, last_command, &cmd_details);
return ret_code;
}
@ -580,6 +612,7 @@ enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
/* Read SR page */
if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
if (ret_code != I40E_SUCCESS) {
ret_code = I40E_ERR_NVM_CHECKSUM;
@ -625,13 +658,15 @@ enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
u16 checksum;
__le16 le_sum;
DEBUGFUNC("i40e_update_nvm_checksum");
ret_code = i40e_calc_nvm_checksum(hw, &checksum);
le_sum = CPU_TO_LE16(checksum);
if (ret_code == I40E_SUCCESS)
ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
1, &checksum, TRUE);
1, &le_sum, TRUE);
return ret_code;
}

10
sys/dev/ixl/i40e_osdep.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -112,6 +112,9 @@
#define FIELD_SIZEOF(x, y) (sizeof(((x*)0)->y))
#define BIT(a) (1UL << (a))
#define BIT_ULL(a) (1ULL << (a))
typedef uint8_t u8;
typedef int8_t s8;
typedef uint16_t u16;
@ -189,7 +192,7 @@ rd32_osdep(struct i40e_osdep *osdep, uint32_t reg)
{
KASSERT(reg < osdep->mem_bus_space_size,
("ixl: register offset %#jx too large (max is %#jx",
("ixl: register offset %#jx too large (max is %#jx)",
(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));
return (bus_space_read_4(osdep->mem_bus_space_tag,
@ -201,7 +204,7 @@ wr32_osdep(struct i40e_osdep *osdep, uint32_t reg, uint32_t value)
{
KASSERT(reg < osdep->mem_bus_space_size,
("ixl: register offset %#jx too large (max is %#jx",
("ixl: register offset %#jx too large (max is %#jx)",
(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));
bus_space_write_4(osdep->mem_bus_space_tag,
@ -211,7 +214,6 @@ wr32_osdep(struct i40e_osdep *osdep, uint32_t reg, uint32_t value)
static __inline void
ixl_flush_osdep(struct i40e_osdep *osdep)
{
rd32_osdep(osdep, osdep->flush_reg);
}

32
sys/dev/ixl/i40e_prototype.h
View File

@ -78,6 +78,21 @@ void i40e_idle_aq(struct i40e_hw *hw);
void i40e_resume_aq(struct i40e_hw *hw);
bool i40e_check_asq_alive(struct i40e_hw *hw);
enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
#ifdef X722_SUPPORT
enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
bool pf_lut, u8 *lut, u16 lut_size);
enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
bool pf_lut, u8 *lut, u16 lut_size);
enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
u16 seid,
struct i40e_aqc_get_set_rss_key_data *key);
enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
u16 seid,
struct i40e_aqc_get_set_rss_key_data *key);
#endif
char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err);
u32 i40e_led_get(struct i40e_hw *hw);
@ -145,6 +160,12 @@ enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
u16 seid, bool enable, u16 vid,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
u16 seid, bool enable, u16 vid,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
struct i40e_vsi_context *vsi_ctx,
struct i40e_asq_cmd_details *cmd_details);
@ -204,6 +225,9 @@ enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
u8 cmd_flags, void *data, u16 buf_size,
u16 element_count,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
void *buff, u16 buff_size,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
void *buff, u16 buff_size, u16 *data_size,
enum i40e_admin_queue_opc list_type_opc,
@ -377,7 +401,8 @@ enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw);
enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw);
void i40e_clear_hw(struct i40e_hw *hw);
void i40e_clear_pxe_mode(struct i40e_hw *hw);
bool i40e_get_link_status(struct i40e_hw *hw);
enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up);
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw);
enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
u32 *max_bw, u32 *min_bw, bool *min_valid, bool *max_valid);
@ -445,4 +470,9 @@ enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
u16 vsi_seid, u16 queue, bool is_add,
struct i40e_control_filter_stats *stats,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
u8 table_id, u32 start_index, u16 buff_size,
void *buff, u16 *ret_buff_size,
u8 *ret_next_table, u32 *ret_next_index,
struct i40e_asq_cmd_details *cmd_details);
#endif /* _I40E_PROTOTYPE_H_ */

1941
sys/dev/ixl/i40e_register.h
View File

File diff suppressed because it is too large Load Diff

201
sys/dev/ixl/i40e_type.h
View File

@ -41,29 +41,12 @@
#include "i40e_adminq.h"
#include "i40e_hmc.h"
#include "i40e_lan_hmc.h"
#include "i40e_devids.h"
#define UNREFERENCED_XPARAMETER
/* Vendor ID */
#define I40E_INTEL_VENDOR_ID 0x8086
/* Device IDs */
#define I40E_DEV_ID_SFP_XL710 0x1572
#define I40E_DEV_ID_QEMU 0x1574
#define I40E_DEV_ID_KX_A 0x157F
#define I40E_DEV_ID_KX_B 0x1580
#define I40E_DEV_ID_KX_C 0x1581
#define I40E_DEV_ID_QSFP_A 0x1583
#define I40E_DEV_ID_QSFP_B 0x1584
#define I40E_DEV_ID_QSFP_C 0x1585
#define I40E_DEV_ID_10G_BASE_T 0x1586
#define I40E_DEV_ID_20G_KR2 0x1587
#define I40E_DEV_ID_VF 0x154C
#define I40E_DEV_ID_VF_HV 0x1571
#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
(d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C)
#define BIT(a) (1UL << (a))
#define BIT_ULL(a) (1ULL << (a))
#ifndef I40E_MASK
/* I40E_MASK is a macro used on 32 bit registers */
@ -191,6 +174,10 @@ enum i40e_mac_type {
I40E_MAC_X710,
I40E_MAC_XL710,
I40E_MAC_VF,
#ifdef X722_SUPPORT
I40E_MAC_X722,
I40E_MAC_X722_VF,
#endif
I40E_MAC_GENERIC,
};
@ -222,14 +209,14 @@ enum i40e_set_fc_aq_failures {
};
enum i40e_vsi_type {
I40E_VSI_MAIN = 0,
I40E_VSI_VMDQ1,
I40E_VSI_VMDQ2,
I40E_VSI_CTRL,
I40E_VSI_FCOE,
I40E_VSI_MIRROR,
I40E_VSI_SRIOV,
I40E_VSI_FDIR,
I40E_VSI_MAIN = 0,
I40E_VSI_VMDQ1 = 1,
I40E_VSI_VMDQ2 = 2,
I40E_VSI_CTRL = 3,
I40E_VSI_FCOE = 4,
I40E_VSI_MIRROR = 5,
I40E_VSI_SRIOV = 6,
I40E_VSI_FDIR = 7,
I40E_VSI_TYPE_UNKNOWN
};
@ -253,16 +240,64 @@ struct i40e_link_status {
bool crc_enable;
u8 pacing;
u8 requested_speeds;
u8 module_type[3];
/* 1st byte: module identifier */
#define I40E_MODULE_TYPE_SFP 0x03
#define I40E_MODULE_TYPE_QSFP 0x0D
/* 2nd byte: ethernet compliance codes for 10/40G */
#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
#define I40E_MODULE_TYPE_40G_LR4 0x02
#define I40E_MODULE_TYPE_40G_SR4 0x04
#define I40E_MODULE_TYPE_40G_CR4 0x08
#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
/* 3rd byte: ethernet compliance codes for 1G */
#define I40E_MODULE_TYPE_1000BASE_SX 0x01
#define I40E_MODULE_TYPE_1000BASE_LX 0x02
#define I40E_MODULE_TYPE_1000BASE_CX 0x04
#define I40E_MODULE_TYPE_1000BASE_T 0x08
};
enum i40e_aq_capabilities_phy_type {
I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
};
struct i40e_phy_info {
struct i40e_link_status link_info;
struct i40e_link_status link_info_old;
u32 autoneg_advertised;
u32 phy_id;
u32 module_type;
bool get_link_info;
enum i40e_media_type media_type;
/* all the phy types the NVM is capable of */
enum i40e_aq_capabilities_phy_type phy_types;
};
#define I40E_HW_CAP_MAX_GPIO 30
@ -287,7 +322,17 @@ struct i40e_hw_capabilities {
bool dcb;
bool fcoe;
bool iscsi; /* Indicates iSCSI enabled */
bool mfp_mode_1;
bool flex10_enable;
bool flex10_capable;
u32 flex10_mode;
#define I40E_FLEX10_MODE_UNKNOWN 0x0
#define I40E_FLEX10_MODE_DCC 0x1
#define I40E_FLEX10_MODE_DCI 0x2
u32 flex10_status;
#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
#define I40E_FLEX10_STATUS_VC_MODE 0x2
bool mgmt_cem;
bool ieee_1588;
bool iwarp;
@ -316,6 +361,7 @@ struct i40e_hw_capabilities {
u8 rx_buf_chain_len;
u32 enabled_tcmap;
u32 maxtc;
u64 wr_csr_prot;
};
struct i40e_mac_info {
@ -343,6 +389,7 @@ struct i40e_nvm_info {
bool blank_nvm_mode; /* is NVM empty (no FW present)*/
u16 version; /* NVM package version */
u32 eetrack; /* NVM data version */
u32 oem_ver; /* OEM version info */
};
/* definitions used in NVM update support */
@ -361,12 +408,17 @@ enum i40e_nvmupd_cmd {
I40E_NVMUPD_CSUM_CON,
I40E_NVMUPD_CSUM_SA,
I40E_NVMUPD_CSUM_LCB,
I40E_NVMUPD_STATUS,
I40E_NVMUPD_EXEC_AQ,
I40E_NVMUPD_GET_AQ_RESULT,
};
enum i40e_nvmupd_state {
I40E_NVMUPD_STATE_INIT,
I40E_NVMUPD_STATE_READING,
I40E_NVMUPD_STATE_WRITING
I40E_NVMUPD_STATE_WRITING,
I40E_NVMUPD_STATE_INIT_WAIT,
I40E_NVMUPD_STATE_WRITE_WAIT,
};
/* nvm_access definition and its masks/shifts need to be accessible to
@ -385,6 +437,7 @@ enum i40e_nvmupd_state {
#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
#define I40E_NVM_ERA 0x4
#define I40E_NVM_CSUM 0x8
#define I40E_NVM_EXEC 0xf
#define I40E_NVM_ADAPT_SHIFT 16
#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
@ -465,6 +518,8 @@ struct i40e_fc_info {
#define I40E_APP_PROTOID_FIP 0x8914
#define I40E_APP_SEL_ETHTYPE 0x1
#define I40E_APP_SEL_TCPIP 0x2
#define I40E_CEE_APP_SEL_ETHTYPE 0x0
#define I40E_CEE_APP_SEL_TCPIP 0x1
/* CEE or IEEE 802.1Qaz ETS Configuration data */
struct i40e_dcb_ets_config {
@ -496,6 +551,7 @@ struct i40e_dcbx_config {
#define I40E_DCBX_MODE_CEE 0x1
#define I40E_DCBX_MODE_IEEE 0x2
u32 numapps;
u32 tlv_status; /* CEE mode TLV status */
struct i40e_dcb_ets_config etscfg;
struct i40e_dcb_ets_config etsrec;
struct i40e_dcb_pfc_config pfc;
@ -547,6 +603,8 @@ struct i40e_hw {
/* state of nvm update process */
enum i40e_nvmupd_state nvmupd_state;
struct i40e_aq_desc nvm_wb_desc;
struct i40e_virt_mem nvm_buff;
/* HMC info */
struct i40e_hmc_info hmc; /* HMC info struct */
@ -555,16 +613,23 @@ struct i40e_hw {
u16 dcbx_status;
/* DCBX info */
struct i40e_dcbx_config local_dcbx_config;
struct i40e_dcbx_config remote_dcbx_config;
struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
/* debug mask */
u32 debug_mask;
char err_str[16];
};
static inline bool i40e_is_vf(struct i40e_hw *hw)
static INLINE bool i40e_is_vf(struct i40e_hw *hw)
{
#ifdef X722_SUPPORT
return (hw->mac.type == I40E_MAC_VF ||
hw->mac.type == I40E_MAC_X722_VF);
#else
return hw->mac.type == I40E_MAC_VF;
#endif
}
struct i40e_driver_version {
@ -668,7 +733,11 @@ enum i40e_rx_desc_status_bits {
I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
#ifdef X722_SUPPORT
I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
#else
I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
#endif
I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
@ -676,12 +745,16 @@ enum i40e_rx_desc_status_bits {
I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
#ifdef X722_SUPPORT
I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
#else
I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
#endif
I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
};
#define I40E_RXD_QW1_STATUS_SHIFT 0
#define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
I40E_RXD_QW1_STATUS_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
@ -689,8 +762,7 @@ enum i40e_rx_desc_status_bits {
I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
#define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
@ -836,8 +908,7 @@ enum i40e_rx_ptype_payload_layer {
I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
I40E_RXD_QW1_LENGTH_SPH_SHIFT)
#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
#define I40E_RXD_QW1_NEXTP_SHIFT 38
#define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
@ -1040,12 +1111,11 @@ enum i40e_tx_ctx_desc_eipt_offload {
#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
@ -1057,6 +1127,10 @@ enum i40e_tx_ctx_desc_eipt_offload {
#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
I40E_TXD_CTX_QW0_DECTTL_SHIFT)
#ifdef X722_SUPPORT
#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
#endif
struct i40e_nop_desc {
__le64 rsvd;
__le64 dtype_cmd;
@ -1093,15 +1167,38 @@ struct i40e_filter_program_desc {
/* Packet Classifier Types for filters */
enum i40e_filter_pctype {
#ifdef X722_SUPPORT
/* Note: Values 0-28 are reserved for future use.
* Value 29, 30, 32 are not supported on XL710 and X710.
*/
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
#else
/* Note: Values 0-30 are reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
#ifdef X722_SUPPORT
I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
#else
/* Note: Value 32 is reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
#ifdef X722_SUPPORT
/* Note: Values 37-38 are reserved for future use.
* Value 39, 40, 42 are not supported on XL710 and X710.
*/
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
#else
/* Note: Values 37-40 are reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
#ifdef X722_SUPPORT
I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
#endif
I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
@ -1128,8 +1225,7 @@ enum i40e_filter_program_desc_fd_status {
};
#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
#define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
@ -1150,13 +1246,18 @@ enum i40e_filter_program_desc_pcmd {
#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
#ifdef X722_SUPPORT
#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
#endif
#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
@ -1263,6 +1364,9 @@ struct i40e_hw_port_stats {
/* flow director stats */
u64 fd_atr_match;
u64 fd_sb_match;
u64 fd_atr_tunnel_match;
u32 fd_atr_status;
u32 fd_sb_status;
/* EEE LPI */
u32 tx_lpi_status;
u32 rx_lpi_status;
@ -1288,6 +1392,7 @@ struct i40e_hw_port_stats {
#define I40E_SR_PBA_FLAGS 0x15
#define I40E_SR_PBA_BLOCK_PTR 0x16
#define I40E_SR_BOOT_CONFIG_PTR 0x17
#define I40E_NVM_OEM_VER_OFF 0x83
#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
#define I40E_SR_NVM_WAKE_ON_LAN 0x19
#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27

21
sys/dev/ixl/i40e_virtchnl.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2013-2014, Intel Corporation
Copyright (c) 2013-2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -89,7 +89,6 @@ enum i40e_virtchnl_ops {
I40E_VIRTCHNL_OP_GET_STATS = 15,
I40E_VIRTCHNL_OP_FCOE = 16,
I40E_VIRTCHNL_OP_EVENT = 17,
I40E_VIRTCHNL_OP_CONFIG_RSS = 18,
};
/* Virtual channel message descriptor. This overlays the admin queue
@ -118,7 +117,9 @@ struct i40e_virtchnl_msg {
* error regardless of version mismatch.
*/
#define I40E_VIRTCHNL_VERSION_MAJOR 1
#define I40E_VIRTCHNL_VERSION_MINOR 0
#define I40E_VIRTCHNL_VERSION_MINOR 1
#define I40E_VIRTCHNL_VERSION_MINOR_NO_VF_CAPS 0
struct i40e_virtchnl_version_info {
u32 major;
u32 minor;
@ -137,7 +138,8 @@ struct i40e_virtchnl_version_info {
*/
/* I40E_VIRTCHNL_OP_GET_VF_RESOURCES
* VF sends this request to PF with no parameters
* Version 1.0 VF sends this request to PF with no parameters
* Version 1.1 VF sends this request to PF with u32 bitmap of its capabilities
* PF responds with an indirect message containing
* i40e_virtchnl_vf_resource and one or more
* i40e_virtchnl_vsi_resource structures.
@ -151,10 +153,13 @@ struct i40e_virtchnl_vsi_resource {
u8 default_mac_addr[I40E_ETH_LENGTH_OF_ADDRESS];
};
/* VF offload flags */
#define I40E_VIRTCHNL_VF_OFFLOAD_L2 0x00000001
#define I40E_VIRTCHNL_VF_OFFLOAD_IWARP 0x00000002
#define I40E_VIRTCHNL_VF_OFFLOAD_FCOE 0x00000004
#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
#define I40E_VIRTCHNL_VF_OFFLOAD_L2 0x00000001
#define I40E_VIRTCHNL_VF_OFFLOAD_IWARP 0x00000002
#define I40E_VIRTCHNL_VF_OFFLOAD_FCOE 0x00000004
#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ 0x00000008
#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010
#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000
struct i40e_virtchnl_vf_resource {
u16 num_vsis;

179
sys/dev/ixl/if_ixl.c
View File

@ -48,7 +48,7 @@
/*********************************************************************
* Driver version
*********************************************************************/
char ixl_driver_version[] = "1.4.1";
char ixl_driver_version[] = "1.4.3";
/*********************************************************************
* PCI Device ID Table
@ -70,7 +70,14 @@ static ixl_vendor_info_t ixl_vendor_info_array[] =
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A, 0, 0, 0},
#ifdef X722_SUPPORT
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722, 0, 0, 0},
{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722, 0, 0, 0},
#endif
/* required last entry */
{0, 0, 0, 0, 0}
};
@ -238,12 +245,10 @@ DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0);
MODULE_DEPEND(ixl, pci, 1, 1, 1);
MODULE_DEPEND(ixl, ether, 1, 1, 1);
#ifdef DEV_NETMAP
MODULE_DEPEND(ixl, netmap, 1, 1, 1);
#endif /* DEV_NETMAP */
/*
** Global reset mutex
*/
@ -478,6 +483,22 @@ ixl_attach(device_t dev)
&ixl_dynamic_tx_itr, 0, "Dynamic TX ITR");
#ifdef IXL_DEBUG_SYSCTL
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0,
ixl_debug_info, "I", "Debug Information");
/* Debug shared-code message level */
SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "debug_mask", CTLFLAG_RW,
&pf->hw.debug_mask, 0, "Debug Message Level");
SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "vc_debug_level", CTLFLAG_RW, &pf->vc_debug_lvl,
0, "PF/VF Virtual Channel debug level");
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD,
@ -525,13 +546,6 @@ ixl_attach(device_t dev)
goto err_out;
}
/* Create for initial debugging use */
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0,
ixl_debug_info, "I", "Debug Information");
/* Establish a clean starting point */
i40e_clear_hw(hw);
error = i40e_pf_reset(hw);
@ -642,7 +656,7 @@ ixl_attach(device_t dev)
/* Determine link state */
i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
pf->link_up = i40e_get_link_status(hw);
i40e_get_link_status(hw, &pf->link_up);
/* Setup OS specific network interface */
if (ixl_setup_interface(dev, vsi) != 0) {
@ -702,7 +716,6 @@ ixl_attach(device_t dev)
#ifdef DEV_NETMAP
ixl_netmap_attach(vsi);
#endif /* DEV_NETMAP */
INIT_DEBUGOUT("ixl_attach: end");
return (0);
@ -1053,6 +1066,9 @@ ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
break;
case SIOCSIFMEDIA:
case SIOCGIFMEDIA:
#ifdef IFM_ETH_XTYPE
case SIOCGIFXMEDIA:
#endif
IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)");
error = ifmedia_ioctl(ifp, ifr, &vsi->media, command);
break;
@ -1426,7 +1442,7 @@ ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
IXL_PF_LOCK(pf);
hw->phy.get_link_info = TRUE;
pf->link_up = i40e_get_link_status(hw);
i40e_get_link_status(hw, &pf->link_up);
ixl_update_link_status(pf);
ifmr->ifm_status = IFM_AVALID;
@ -1457,12 +1473,7 @@ ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
ifmr->ifm_active |= IFM_1000_LX;
break;
/* 10 G */
case I40E_PHY_TYPE_10GBASE_CR1:
case I40E_PHY_TYPE_10GBASE_CR1_CU:
case I40E_PHY_TYPE_10GBASE_SFPP_CU:
/* Using this until a real KR media type */
case I40E_PHY_TYPE_10GBASE_KR:
case I40E_PHY_TYPE_10GBASE_KX4:
ifmr->ifm_active |= IFM_10G_TWINAX;
break;
case I40E_PHY_TYPE_10GBASE_SR:
@ -1485,16 +1496,49 @@ ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
case I40E_PHY_TYPE_40GBASE_LR4:
ifmr->ifm_active |= IFM_40G_LR4;
break;
/*
** Set these to CR4 because OS does not
** have types available yet.
*/
case I40E_PHY_TYPE_40GBASE_KR4:
case I40E_PHY_TYPE_XLAUI:
case I40E_PHY_TYPE_XLPPI:
case I40E_PHY_TYPE_40GBASE_AOC:
ifmr->ifm_active |= IFM_40G_CR4;
#ifndef IFM_ETH_XTYPE
case I40E_PHY_TYPE_1000BASE_KX:
ifmr->ifm_active |= IFM_1000_CX;
break;
case I40E_PHY_TYPE_10GBASE_CR1_CU:
case I40E_PHY_TYPE_10GBASE_CR1:
ifmr->ifm_active |= IFM_10G_TWINAX;
break;
case I40E_PHY_TYPE_10GBASE_KX4:
ifmr->ifm_active |= IFM_10G_CX4;
break;
case I40E_PHY_TYPE_10GBASE_KR:
ifmr->ifm_active |= IFM_10G_SR;
break;
case I40E_PHY_TYPE_40GBASE_KR4:
case I40E_PHY_TYPE_XLPPI:
ifmr->ifm_active |= IFM_40G_SR4;
break;
#else
case I40E_PHY_TYPE_1000BASE_KX:
ifmr->ifm_active |= IFM_1000_KX;
break;
/* ERJ: What's the difference between these? */
case I40E_PHY_TYPE_10GBASE_CR1_CU:
case I40E_PHY_TYPE_10GBASE_CR1:
ifmr->ifm_active |= IFM_10G_CR1;
break;
case I40E_PHY_TYPE_10GBASE_KX4:
ifmr->ifm_active |= IFM_10G_KX4;
break;
case I40E_PHY_TYPE_10GBASE_KR:
ifmr->ifm_active |= IFM_10G_KR;
break;
case I40E_PHY_TYPE_20GBASE_KR2:
ifmr->ifm_active |= IFM_20G_KR2;
break;
case I40E_PHY_TYPE_40GBASE_KR4:
ifmr->ifm_active |= IFM_40G_KR4;
break;
case I40E_PHY_TYPE_XLPPI:
ifmr->ifm_active |= IFM_40G_XLPPI;
break;
#endif
default:
ifmr->ifm_active |= IFM_UNKNOWN;
break;
@ -2417,13 +2461,8 @@ ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type)
if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_LX))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) ||
phy_type & (1 << I40E_PHY_TYPE_XAUI) ||
if (phy_type & (1 << I40E_PHY_TYPE_XAUI) ||
phy_type & (1 << I40E_PHY_TYPE_XFI) ||
phy_type & (1 << I40E_PHY_TYPE_SFI) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL);
@ -2438,15 +2477,55 @@ ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type)
phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) ||
phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) ||
phy_type & (1 << I40E_PHY_TYPE_XLAUI) ||
phy_type & (1 << I40E_PHY_TYPE_XLPPI) ||
/* KR4 uses CR4 until the OS has the real media type */
phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL);
#ifndef IFM_ETH_XTYPE
if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1) ||
phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) ||
phy_type & (1 << I40E_PHY_TYPE_SFI))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CX4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_XLPPI))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL);
#else
if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU)
|| phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CR1, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX_LONG, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_SFI))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KX4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_20GBASE_KR2))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_20G_KR2, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_KR4, 0, NULL);
if (phy_type & (1 << I40E_PHY_TYPE_XLPPI))
ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_XLPPI, 0, NULL);
#endif
}
/*********************************************************************
@ -2569,7 +2648,7 @@ ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e)
bool check;
hw->phy.get_link_info = TRUE;
check = i40e_get_link_status(hw);
i40e_get_link_status(hw, &check);
pf->link_up = check;
#ifdef IXL_DEBUG
printf("Link is %s\n", check ? "up":"down");
@ -3184,10 +3263,6 @@ ixl_add_hw_stats(struct ixl_pf *pf)
CTLFLAG_RD, &pf->admin_irq,
"Admin Queue IRQ Handled");
SYSCTL_ADD_INT(ctx, child, OID_AUTO, "vc_debug_level",
CTLFLAG_RW, &pf->vc_debug_lvl, 0,
"PF/VF Virtual Channel debug logging level");
ixl_add_vsi_sysctls(pf, &pf->vsi, ctx, "pf");
vsi_list = SYSCTL_CHILDREN(pf->vsi.vsi_node);
@ -3331,6 +3406,7 @@ ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx,
}
}
/*
** ixl_config_rss - setup RSS
** - note this is done for the single vsi
@ -4976,8 +5052,8 @@ static int
ixl_res_alloc_cmp(const void *a, const void *b)
{
const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two;
one = (struct i40e_aqc_switch_resource_alloc_element_resp *)a;
two = (struct i40e_aqc_switch_resource_alloc_element_resp *)b;
one = (const struct i40e_aqc_switch_resource_alloc_element_resp *)a;
two = (const struct i40e_aqc_switch_resource_alloc_element_resp *)b;
return ((int)one->resource_type - (int)two->resource_type);
}
@ -4994,7 +5070,7 @@ ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS)
u8 num_entries;
struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE];
buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
buf = sbuf_new_for_sysctl(NULL, NULL, 0, req);
if (!buf) {
device_printf(dev, "Could not allocate sbuf for output.\n");
return (ENOMEM);
@ -5038,7 +5114,13 @@ ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS)
error = sbuf_finish(buf);
if (error) {
device_printf(dev, "Error finishing sbuf: %d\n", error);
sbuf_delete(buf);
return error;
}
error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
if (error)
device_printf(dev, "sysctl error: %d\n", error);
sbuf_delete(buf);
return error;
}
@ -5096,7 +5178,7 @@ ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS)
struct i40e_aqc_get_switch_config_resp *sw_config;
sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
buf = sbuf_new_for_sysctl(NULL, NULL, 0, req);
if (!buf) {
device_printf(dev, "Could not allocate sbuf for sysctl output.\n");
return (ENOMEM);
@ -5115,7 +5197,6 @@ ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS)
nmbuf = sbuf_new_auto();
if (!nmbuf) {
device_printf(dev, "Could not allocate sbuf for name output.\n");
sbuf_delete(buf);
return (ENOMEM);
}
@ -5150,7 +5231,13 @@ ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS)
error = sbuf_finish(buf);
if (error) {
device_printf(dev, "Error finishing sbuf: %d\n", error);
sbuf_delete(buf);
return error;
}
error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
if (error)
device_printf(dev, "sysctl error: %d\n", error);
sbuf_delete(buf);
return (error);

36
sys/dev/ixl/if_ixlv.c
View File

@ -48,7 +48,7 @@
/*********************************************************************
* Driver version
*********************************************************************/
char ixlv_driver_version[] = "1.2.4";
char ixlv_driver_version[] = "1.2.6";
/*********************************************************************
* PCI Device ID Table
@ -1832,7 +1832,7 @@ ixlv_msix_adminq(void *arg)
mask = rd32(hw, I40E_VFINT_ICR0_ENA1);
reg = rd32(hw, I40E_VFINT_DYN_CTL01);
reg |= I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
reg |= I40E_VFINT_DYN_CTL01_CLEARPBA_MASK;
wr32(hw, I40E_VFINT_DYN_CTL01, reg);
/* schedule task */
@ -1879,7 +1879,7 @@ ixlv_enable_adminq_irq(struct i40e_hw *hw)
wr32(hw, I40E_VFINT_DYN_CTL01,
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA_ADMINQ_MASK);
wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK);
/* flush */
rd32(hw, I40E_VFGEN_RSTAT);
return;
@ -1891,7 +1891,7 @@ ixlv_enable_queue_irq(struct i40e_hw *hw, int id)
u32 reg;
reg = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;
I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;
wr32(hw, I40E_VFINT_DYN_CTLN1(id), reg);
}
@ -2375,8 +2375,8 @@ ixlv_local_timer(void *arg)
/*
** Check status on the queues for a hang
*/
mask = (I40E_VFINT_DYN_CTLN_INTENA_MASK |
I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK);
mask = (I40E_VFINT_DYN_CTLN1_INTENA_MASK |
I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK);
for (int i = 0; i < vsi->num_queues; i++,que++) {
/* Any queues with outstanding work get a sw irq */
@ -2742,33 +2742,33 @@ ixlv_do_adminq_locked(struct ixlv_sc *sc)
/* check for Admin queue errors */
oldreg = reg = rd32(hw, hw->aq.arq.len);
if (reg & I40E_VF_ARQLEN_ARQVFE_MASK) {
if (reg & I40E_VF_ARQLEN1_ARQVFE_MASK) {
device_printf(dev, "ARQ VF Error detected\n");
reg &= ~I40E_VF_ARQLEN_ARQVFE_MASK;
reg &= ~I40E_VF_ARQLEN1_ARQVFE_MASK;
}
if (reg & I40E_VF_ARQLEN_ARQOVFL_MASK) {
if (reg & I40E_VF_ARQLEN1_ARQOVFL_MASK) {
device_printf(dev, "ARQ Overflow Error detected\n");
reg &= ~I40E_VF_ARQLEN_ARQOVFL_MASK;
reg &= ~I40E_VF_ARQLEN1_ARQOVFL_MASK;
}
if (reg & I40E_VF_ARQLEN_ARQCRIT_MASK) {
if (reg & I40E_VF_ARQLEN1_ARQCRIT_MASK) {
device_printf(dev, "ARQ Critical Error detected\n");
reg &= ~I40E_VF_ARQLEN_ARQCRIT_MASK;
reg &= ~I40E_VF_ARQLEN1_ARQCRIT_MASK;
}
if (oldreg != reg)
wr32(hw, hw->aq.arq.len, reg);
oldreg = reg = rd32(hw, hw->aq.asq.len);
if (reg & I40E_VF_ATQLEN_ATQVFE_MASK) {
if (reg & I40E_VF_ATQLEN1_ATQVFE_MASK) {
device_printf(dev, "ASQ VF Error detected\n");
reg &= ~I40E_VF_ATQLEN_ATQVFE_MASK;
reg &= ~I40E_VF_ATQLEN1_ATQVFE_MASK;
}
if (reg & I40E_VF_ATQLEN_ATQOVFL_MASK) {
if (reg & I40E_VF_ATQLEN1_ATQOVFL_MASK) {
device_printf(dev, "ASQ Overflow Error detected\n");
reg &= ~I40E_VF_ATQLEN_ATQOVFL_MASK;
reg &= ~I40E_VF_ATQLEN1_ATQOVFL_MASK;
}
if (reg & I40E_VF_ATQLEN_ATQCRIT_MASK) {
if (reg & I40E_VF_ATQLEN1_ATQCRIT_MASK) {
device_printf(dev, "ASQ Critical Error detected\n");
reg &= ~I40E_VF_ATQLEN_ATQCRIT_MASK;
reg &= ~I40E_VF_ATQLEN1_ATQCRIT_MASK;
}
if (oldreg != reg)
wr32(hw, hw->aq.asq.len, reg);

1
sys/dev/ixl/ixlv.h
View File

@ -117,6 +117,7 @@ struct ixlv_sc {
struct ifmedia media;
struct callout timer;
int msix;
int pf_version;
int if_flags;
bool link_up;

20
sys/dev/ixl/ixlvc.c
View File

@ -249,9 +249,12 @@ ixlv_verify_api_ver(struct ixlv_sc *sc)
}
pf_vvi = (struct i40e_virtchnl_version_info *)event.msg_buf;
if ((pf_vvi->major != I40E_VIRTCHNL_VERSION_MAJOR) ||
(pf_vvi->minor != I40E_VIRTCHNL_VERSION_MINOR))
if ((pf_vvi->major > I40E_VIRTCHNL_VERSION_MAJOR) ||
((pf_vvi->major == I40E_VIRTCHNL_VERSION_MAJOR) &&
(pf_vvi->minor > I40E_VIRTCHNL_VERSION_MINOR)))
err = EIO;
else
sc->pf_version = pf_vvi->minor;
out_alloc:
free(event.msg_buf, M_DEVBUF);
@ -269,7 +272,18 @@ ixlv_verify_api_ver(struct ixlv_sc *sc)
int
ixlv_send_vf_config_msg(struct ixlv_sc *sc)
{
return ixlv_send_pf_msg(sc, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
u32 caps;
caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
if (sc->pf_version)
return ixlv_send_pf_msg(sc, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
(u8 *)&caps, sizeof(caps));
else
return ixlv_send_pf_msg(sc, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
NULL, 0);
}

2
sys/modules/ixl/Makefile
View File

@ -10,7 +10,7 @@ SRCS += if_ixl.c ixl_txrx.c i40e_osdep.c
# Shared source
SRCS += i40e_common.c i40e_nvm.c i40e_adminq.c i40e_lan_hmc.c i40e_hmc.c
CFLAGS += -DSMP
CFLAGS += -DSMP -DIXL_DEBUG_SYSCTL
# Add Flow Director support
# CFLAGS += -DIXL_FDIR

2
sys/modules/ixlv/Makefile
View File

@ -8,7 +8,7 @@ SRCS += opt_inet.h opt_inet6.h opt_rss.h
SRCS += if_ixlv.c ixlvc.c ixl_txrx.c i40e_osdep.c
# Shared source
SRCS += i40e_common.c i40e_nvm.c i40e_adminq.c i40e_lan_hmc.c i40e_hmc.c
SRCS += i40e_common.c i40e_nvm.c i40e_adminq.c
CFLAGS += -DSMP