From beb388db08f0770b400c9d4377ad8cfe89f0d0a7 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Mon, 3 Jun 2019 23:17:35 +0000 Subject: [PATCH] Emulate the AMD MSR_LS_CFG MSR used for various Ryzen errata. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Writes are ignored and reads always return zero. Submitted by: José Albornoz (write-only version) Reviewed by: Patrick Mooney, cem MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D19506 --- usr.sbin/bhyve/xmsr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/usr.sbin/bhyve/xmsr.c b/usr.sbin/bhyve/xmsr.c index a476a95665bf..f252714bf48c 100644 --- a/usr.sbin/bhyve/xmsr.c +++ b/usr.sbin/bhyve/xmsr.c @@ -72,6 +72,7 @@ emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t val) return (0); case MSR_NB_CFG1: + case MSR_LS_CFG: case MSR_IC_CFG: return (0); /* Ignore writes */ @@ -141,6 +142,7 @@ emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val) break; case MSR_NB_CFG1: + case MSR_LS_CFG: case MSR_IC_CFG: /* * The reset value is processor family dependent so