ofed/drivers: minor spelling fixes.
No functional change. Reviewed by: hselasky
This commit is contained in:
parent
2a392dd62b
commit
bf5cba36db
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=299179
@ -799,7 +799,7 @@ static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
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unsigned long command = vma->vm_pgoff & MLX4_IB_MMAP_CMD_MASK;
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if (command < MLX4_IB_MMAP_GET_CONTIGUOUS_PAGES) {
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/* compatability handling for commands 0 & 1*/
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/* compatibility handling for commands 0 & 1*/
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if (vma->vm_end - vma->vm_start != PAGE_SIZE)
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return -EINVAL;
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}
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@ -689,7 +689,7 @@ static void mlx4_ib_mcg_work_handler(struct work_struct *work)
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cur_join_state = group->rec.scope_join_state & 7;
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if (method == IB_MGMT_METHOD_GET_RESP) {
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/* successfull join */
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/* successful join */
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if (!cur_join_state && resp_join_state)
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--rc;
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} else if (!resp_join_state)
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@ -341,8 +341,8 @@ int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem,
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address for the start of the MR.
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*/
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/* umem_get aligned the start_va to a page
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boundry. Therefore, we need to align the
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start va to the same boundry */
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boundary. Therefore, we need to align the
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start va to the same boundary */
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/* misalignment_bits is needed to handle the
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case of a single memory region. In this
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case, the rest of the logic will not reduce
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@ -66,7 +66,7 @@ struct name { \
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struct type *lh_first; /* first element */ \
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}
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/* Interval between sucessive polls in the Tx routine when polling is used
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/* Interval between successive polls in the Tx routine when polling is used
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instead of interrupts (in per-core Tx rings) - should be power of 2 */
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#define SDP_TX_POLL_MODER 16
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#define SDP_TX_POLL_TIMEOUT (HZ / 20)
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@ -424,8 +424,8 @@ struct sdp_sock {
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/* SDP slow start */
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int recv_request_head; /* mark the rx_head when the resize request
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was recieved */
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int recv_request; /* XXX flag if request to resize was recieved */
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was received */
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int recv_request; /* XXX flag if request to resize was received */
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unsigned long tx_packets;
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unsigned long rx_packets;
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@ -328,7 +328,7 @@ sdp_poll_tx(struct sdp_sock *ssk)
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SDPSTATS_COUNTER_INC(tx_poll_hit);
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inflight = (u32) tx_ring_posted(ssk);
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sdp_prf1(ssk->socket, NULL, "finished tx proccessing. inflight = %d",
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sdp_prf1(ssk->socket, NULL, "finished tx processing. inflight = %d",
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inflight);
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/* If there are still packets in flight and the timer has not already
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@ -552,7 +552,7 @@ mlx4_en_rx_mb(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring,
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/* For cpu arch with cache line of 64B the performance is better when cqe size==64B
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* To enlarge cqe size from 32B to 64B --> 32B of garbage (i.e. 0xccccccc)
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* was added in the beginning of each cqe (the real data is in the corresponding 32B).
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* The following calc ensures that when factor==1, it means we are alligned to 64B
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* The following calc ensures that when factor==1, it means we are aligned to 64B
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* and we get the real cqe data*/
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#define CQE_FACTOR_INDEX(index, factor) ((index << factor) + factor)
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int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
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@ -1901,7 +1901,7 @@ void mlx4_opreq_action(struct work_struct *work)
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MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_err(dev, "Failed to retreive required operation: %d\n", err);
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mlx4_err(dev, "Failed to retrieve required operation: %d\n", err);
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return;
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}
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MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
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@ -159,7 +159,7 @@ MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate"
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static int fast_drop;
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module_param_named(fast_drop, fast_drop, int, 0444);
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MODULE_PARM_DESC(fast_drop,
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"Enable fast packet drop when no recieve WQEs are posted");
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"Enable fast packet drop when no receive WQEs are posted");
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int mlx4_enable_64b_cqe_eqe = 1;
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module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644);
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@ -2452,7 +2452,7 @@ EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
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void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx)
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{
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/* check if native or slave and deletes acordingly */
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/* check if native or slave and deletes accordingly */
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct counter_index *pf, *tmp_pf;
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struct counter_index *vf, *tmp_vf;
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@ -164,7 +164,7 @@ enum mlx4_res_tracker_free_type {
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/*
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*Virtual HCR structures.
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* mlx4_vhcr is the sw representation, in machine endianess
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* mlx4_vhcr is the sw representation, in machine endianness
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*
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* mlx4_vhcr_cmd is the formalized structure, the one that is passed
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* to FW to go through communication channel.
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@ -2916,7 +2916,7 @@ int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
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/* Call the SW implementation of write_mtt:
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* - Prepare a dummy mtt struct
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* - Translate inbox contents to simple addresses in host endianess */
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* - Translate inbox contents to simple addresses in host endianness */
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mtt.offset = 0; /* TBD this is broken but I don't handle it since
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we don't really use it */
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mtt.order = 0;
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