arm: allwinner: Fix audio for Allwinner H3/H5
Due to three conditions the codec driver for Allwinner A10/A20 and H3/H5 did not work properly here:
Wrong bit position for the analog audio reset
Hardware Reset of codec was not de-asserted correctly
Linux DTS file did not contain the address of the analog register the way as the driver was expecting it.
This patch proposes fixes for those three parts.
Submitted by: freebsdnewbie@freenet.de (Manuel Stühn)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D19910
This commit is contained in:
Emmanuel Vadot
parent
9a4eed0be2
commit
bfcf888a87
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=346334
@ -164,7 +164,7 @@ struct a10codec_chinfo {
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struct a10codec_info {
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device_t dev;
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struct resource *res[3];
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struct resource *res[2];
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struct mtx *lock;
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bus_dma_tag_t dmat;
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unsigned dmasize;
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@ -178,11 +178,12 @@ struct a10codec_info {
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static struct resource_spec a10codec_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg))
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#define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val))
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#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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@ -372,7 +373,7 @@ MIXER_DECLARE(a10_mixer);
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*/
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#define H3_PR_CFG 0x00
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#define H3_AC_PR_RST (1 << 18)
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#define H3_AC_PR_RST (1 << 28)
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#define H3_AC_PR_RW (1 << 24)
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#define H3_AC_PR_ADDR_SHIFT 16
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#define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT)
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@ -424,23 +425,23 @@ h3_pr_read(struct a10codec_info *sc, u_int addr)
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uint32_t val;
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/* Read current value */
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val = bus_read_4(sc->res[1], H3_PR_CFG);
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val = CODEC_ANALOG_READ(sc, H3_PR_CFG);
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/* De-assert reset */
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val |= H3_AC_PR_RST;
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Read mode */
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val &= ~H3_AC_PR_RW;
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Set address */
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val &= ~H3_AC_PR_ADDR_MASK;
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val |= (addr << H3_AC_PR_ADDR_SHIFT);
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Read data */
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return (bus_read_4(sc->res[1], H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK);
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return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK);
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}
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static void
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@ -449,25 +450,25 @@ h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data)
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uint32_t val;
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/* Read current value */
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val = bus_read_4(sc->res[1], H3_PR_CFG);
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val = CODEC_ANALOG_READ(sc, H3_PR_CFG);
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/* De-assert reset */
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val |= H3_AC_PR_RST;
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Set address */
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val &= ~H3_AC_PR_ADDR_MASK;
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val |= (addr << H3_AC_PR_ADDR_SHIFT);
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Write data */
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val &= ~H3_ACDA_PR_WDAT_MASK;
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val |= (data << H3_ACDA_PR_WDAT_SHIFT);
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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/* Write mode */
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val |= H3_AC_PR_RW;
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bus_write_4(sc->res[1], H3_PR_CFG, val);
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CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val);
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}
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static void
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@ -483,8 +484,28 @@ h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr)
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static int
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h3_mixer_init(struct snd_mixer *m)
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{
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int rid=1;
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pcell_t reg[2];
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phandle_t analogref;
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struct a10codec_info *sc = mix_getdevinfo(m);
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if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls",
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&analogref, sizeof(analogref)) <= 0) {
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return (ENXIO);
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}
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if (OF_getencprop(OF_node_from_xref(analogref), "reg",
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reg, sizeof(reg)) <= 0) {
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return (ENXIO);
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}
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sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0],
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reg[0]+reg[1], reg[1], RF_ACTIVE );
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if (sc->res[1] == NULL) {
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return (ENXIO);
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}
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mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV |
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SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1);
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mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 |
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@ -940,6 +961,7 @@ a10codec_chan_trigger(kobj_t obj, void *data, int go)
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switch (go) {
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case PCMTRIG_START:
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ch->run = 1;
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a10codec_stop(ch);
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a10codec_start(ch);
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break;
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case PCMTRIG_STOP:
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@ -1124,8 +1146,7 @@ a10codec_attach(device_t dev)
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}
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/* De-assert hwreset */
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if (hwreset_get_by_ofw_name(dev, 0, "apb", &rst) == 0 ||
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hwreset_get_by_ofw_name(dev, 0, "ahb", &rst) == 0) {
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if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
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error = hwreset_deassert(rst);
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if (error != 0) {
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device_printf(dev, "cannot de-assert reset\n");
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@ -1138,15 +1159,6 @@ a10codec_attach(device_t dev)
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val |= DAC_DPC_EN_DA;
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CODEC_WRITE(sc, AC_DAC_DPC(sc), val);
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#ifdef notdef
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error = snd_setup_intr(dev, sc->irq, INTR_MPSAFE, a10codec_intr, sc,
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&sc->ih);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler\n");
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goto fail;
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}
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#endif
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if (mixer_init(dev, sc->cfg->mixer_class, sc)) {
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device_printf(dev, "mixer_init failed\n");
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goto fail;
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