x86: consolidate hw watchpoint logic into new file
This is a prerequisite to using these functions outside of ddb, but also provides some cleanup and minor refactoring. This code is almost entirely duplicated between the two implementations, the only significant difference being the lack of dbreg synchronization on i386. Cleanups are: - demote some internal functions to static - use the constant NDBREGS instead of a '4' literal - remove K&R definitions - some added comments Reviewed by: kib, jhb Sponsored by: NetApp, Inc. Sponsored by: Klara, Inc. MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D29153
This commit is contained in:
Mitchell Horne
parent
a1d803c162
commit
c02c04f113
@ -128,11 +128,6 @@ static void db_nextframe(struct amd64_frame **, db_addr_t *, struct thread *);
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static void db_print_stack_entry(const char *, db_addr_t, void *);
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static void decode_syscall(int, struct thread *);
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static const char * watchtype_str(int type);
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int amd64_set_watch(int watchnum, unsigned long watchaddr, int size,
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int access, struct dbreg *d);
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int amd64_clr_watch(int watchnum, struct dbreg *d);
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static void
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db_print_stack_entry(const char *name, db_addr_t callpc, void *frame)
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{
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@ -391,223 +386,22 @@ db_trace_thread(struct thread *thr, int count)
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}
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int
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amd64_set_watch(watchnum, watchaddr, size, access, d)
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int watchnum;
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unsigned long watchaddr;
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int size;
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int access;
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struct dbreg *d;
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db_md_set_watchpoint(db_expr_t addr, db_expr_t size)
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{
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int i, len;
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if (watchnum == -1) {
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for (i = 0; i < 4; i++)
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if (!DBREG_DR7_ENABLED(d->dr[7], i))
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break;
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if (i < 4)
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watchnum = i;
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else
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return (-1);
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}
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switch (access) {
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case DBREG_DR7_EXEC:
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size = 1; /* size must be 1 for an execution breakpoint */
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/* fall through */
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case DBREG_DR7_WRONLY:
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case DBREG_DR7_RDWR:
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break;
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default:
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return (-1);
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}
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/*
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* we can watch a 1, 2, 4, or 8 byte sized location
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*/
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switch (size) {
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case 1:
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len = DBREG_DR7_LEN_1;
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break;
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case 2:
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len = DBREG_DR7_LEN_2;
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break;
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case 4:
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len = DBREG_DR7_LEN_4;
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break;
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case 8:
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len = DBREG_DR7_LEN_8;
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break;
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default:
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return (-1);
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}
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/* clear the bits we are about to affect */
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d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
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/* set drN register to the address, N=watchnum */
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DBREG_DRX(d, watchnum) = watchaddr;
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/* enable the watchpoint */
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d->dr[7] |= DBREG_DR7_SET(watchnum, len, access,
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DBREG_DR7_GLOBAL_ENABLE);
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return (watchnum);
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return (dbreg_set_watchpoint((vm_offset_t)addr, (vm_size_t)size));
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}
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int
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amd64_clr_watch(watchnum, d)
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int watchnum;
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struct dbreg *d;
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db_md_clr_watchpoint(db_expr_t addr, db_expr_t size)
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{
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if (watchnum < 0 || watchnum >= 4)
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return (-1);
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d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
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DBREG_DRX(d, watchnum) = 0;
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return (0);
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}
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int
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db_md_set_watchpoint(addr, size)
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db_expr_t addr;
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db_expr_t size;
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{
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struct dbreg *d;
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struct pcpu *pc;
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int avail, c, cpu, i, wsize;
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d = (struct dbreg *)PCPU_PTR(dbreg);
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cpu = PCPU_GET(cpuid);
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fill_dbregs(NULL, d);
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avail = 0;
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for (i = 0; i < 4; i++) {
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if (!DBREG_DR7_ENABLED(d->dr[7], i))
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avail++;
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}
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if (avail * 8 < size)
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return (-1);
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for (i = 0; i < 4 && size > 0; i++) {
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if (!DBREG_DR7_ENABLED(d->dr[7], i)) {
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if (size >= 8 || (avail == 1 && size > 4))
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wsize = 8;
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else if (size > 2)
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wsize = 4;
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else
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wsize = size;
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amd64_set_watch(i, addr, wsize, DBREG_DR7_WRONLY, d);
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addr += wsize;
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size -= wsize;
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avail--;
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}
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}
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set_dbregs(NULL, d);
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CPU_FOREACH(c) {
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if (c == cpu)
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continue;
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pc = pcpu_find(c);
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memcpy(pc->pc_dbreg, d, sizeof(*d));
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pc->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
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}
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return (0);
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}
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int
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db_md_clr_watchpoint(addr, size)
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db_expr_t addr;
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db_expr_t size;
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{
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struct dbreg *d;
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struct pcpu *pc;
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int i, c, cpu;
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d = (struct dbreg *)PCPU_PTR(dbreg);
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cpu = PCPU_GET(cpuid);
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fill_dbregs(NULL, d);
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for (i = 0; i < 4; i++) {
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if (DBREG_DR7_ENABLED(d->dr[7], i)) {
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if (DBREG_DRX((d), i) >= addr &&
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DBREG_DRX((d), i) < addr + size)
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amd64_clr_watch(i, d);
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}
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}
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set_dbregs(NULL, d);
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CPU_FOREACH(c) {
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if (c == cpu)
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continue;
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pc = pcpu_find(c);
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memcpy(pc->pc_dbreg, d, sizeof(*d));
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pc->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
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}
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return (0);
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}
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static const char *
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watchtype_str(type)
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int type;
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{
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switch (type) {
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case DBREG_DR7_EXEC : return "execute"; break;
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case DBREG_DR7_RDWR : return "read/write"; break;
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case DBREG_DR7_WRONLY : return "write"; break;
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default : return "invalid"; break;
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}
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return (dbreg_clr_watchpoint((vm_offset_t)addr, (vm_size_t)size));
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}
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void
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db_md_list_watchpoints(void)
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{
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struct dbreg d;
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int i, len, type;
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fill_dbregs(NULL, &d);
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db_printf("\nhardware watchpoints:\n");
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db_printf(" watch status type len address\n");
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db_printf(" ----- -------- ---------- --- ------------------\n");
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for (i = 0; i < 4; i++) {
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if (DBREG_DR7_ENABLED(d.dr[7], i)) {
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type = DBREG_DR7_ACCESS(d.dr[7], i);
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len = DBREG_DR7_LEN(d.dr[7], i);
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if (len == DBREG_DR7_LEN_8)
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len = 8;
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else
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len++;
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db_printf(" %-5d %-8s %10s %3d ",
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i, "enabled", watchtype_str(type), len);
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db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
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db_printf("\n");
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} else {
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db_printf(" %-5d disabled\n", i);
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}
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}
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db_printf("\ndebug register values:\n");
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for (i = 0; i < 8; i++)
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if (i != 4 && i != 5)
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db_printf(" dr%d 0x%016lx\n", i, DBREG_DRX(&d, i));
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db_printf("\n");
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}
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void
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amd64_db_resume_dbreg(void)
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{
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struct dbreg *d;
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switch (PCPU_GET(dbreg_cmd)) {
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case PC_DBREG_CMD_LOAD:
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d = (struct dbreg *)PCPU_PTR(dbreg);
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set_dbregs(NULL, d);
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PCPU_SET(dbreg_cmd, PC_DBREG_CMD_NONE);
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break;
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}
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dbreg_list_watchpoints();
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}
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@ -320,6 +320,7 @@ x86/x86/bus_machdep.c standard
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x86/x86/busdma_bounce.c standard
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x86/x86/busdma_machdep.c standard
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x86/x86/cpu_machdep.c standard
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x86/x86/dbreg.c optional ddb
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x86/x86/dump_machdep.c standard
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x86/x86/fdt_machdep.c optional fdt
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x86/x86/identcpu.c standard
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@ -198,11 +198,6 @@ static void db_print_stack_entry(const char *, int, char **, int *, db_addr_t,
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void *);
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static void decode_syscall(int, struct thread *);
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static const char * watchtype_str(int type);
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int i386_set_watch(int watchnum, unsigned int watchaddr, int size, int access,
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struct dbreg *d);
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int i386_clr_watch(int watchnum, struct dbreg *d);
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/*
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* Figure out how many arguments were passed into the frame at "fp".
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*/
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@ -618,180 +613,22 @@ db_trace_thread(struct thread *thr, int count)
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}
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int
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i386_set_watch(watchnum, watchaddr, size, access, d)
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int watchnum;
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unsigned int watchaddr;
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int size;
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int access;
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struct dbreg *d;
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db_md_set_watchpoint(db_expr_t addr, db_expr_t size)
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{
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int i, len;
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if (watchnum == -1) {
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for (i = 0; i < 4; i++)
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if (!DBREG_DR7_ENABLED(d->dr[7], i))
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break;
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if (i < 4)
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watchnum = i;
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else
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return (-1);
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}
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switch (access) {
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case DBREG_DR7_EXEC:
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size = 1; /* size must be 1 for an execution breakpoint */
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/* fall through */
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case DBREG_DR7_WRONLY:
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case DBREG_DR7_RDWR:
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break;
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default:
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return (-1);
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}
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/*
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* we can watch a 1, 2, or 4 byte sized location
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*/
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switch (size) {
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case 1:
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len = DBREG_DR7_LEN_1;
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break;
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case 2:
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len = DBREG_DR7_LEN_2;
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break;
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case 4:
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len = DBREG_DR7_LEN_4;
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break;
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default:
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return (-1);
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}
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/* clear the bits we are about to affect */
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d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
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/* set drN register to the address, N=watchnum */
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DBREG_DRX(d, watchnum) = watchaddr;
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/* enable the watchpoint */
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d->dr[7] |= DBREG_DR7_SET(watchnum, len, access,
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DBREG_DR7_GLOBAL_ENABLE);
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return (watchnum);
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return (dbreg_set_watchpoint((vm_offset_t)addr, (vm_size_t)size));
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}
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int
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i386_clr_watch(watchnum, d)
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int watchnum;
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struct dbreg *d;
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db_md_clr_watchpoint(db_expr_t addr, db_expr_t size)
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{
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if (watchnum < 0 || watchnum >= 4)
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return (-1);
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d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
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DBREG_DRX(d, watchnum) = 0;
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return (0);
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}
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int
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db_md_set_watchpoint(addr, size)
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db_expr_t addr;
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db_expr_t size;
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{
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struct dbreg d;
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int avail, i, wsize;
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fill_dbregs(NULL, &d);
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avail = 0;
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for(i = 0; i < 4; i++) {
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if (!DBREG_DR7_ENABLED(d.dr[7], i))
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avail++;
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}
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if (avail * 4 < size)
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return (-1);
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for (i = 0; i < 4 && (size > 0); i++) {
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if (!DBREG_DR7_ENABLED(d.dr[7], i)) {
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if (size > 2)
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wsize = 4;
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else
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wsize = size;
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i386_set_watch(i, addr, wsize,
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DBREG_DR7_WRONLY, &d);
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addr += wsize;
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size -= wsize;
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}
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}
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set_dbregs(NULL, &d);
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return(0);
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}
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int
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db_md_clr_watchpoint(addr, size)
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db_expr_t addr;
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db_expr_t size;
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{
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struct dbreg d;
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int i;
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fill_dbregs(NULL, &d);
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for(i = 0; i < 4; i++) {
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if (DBREG_DR7_ENABLED(d.dr[7], i)) {
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if ((DBREG_DRX((&d), i) >= addr) &&
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(DBREG_DRX((&d), i) < addr+size))
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i386_clr_watch(i, &d);
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}
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}
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set_dbregs(NULL, &d);
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return(0);
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}
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static const char *
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watchtype_str(type)
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int type;
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{
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switch (type) {
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case DBREG_DR7_EXEC : return "execute"; break;
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case DBREG_DR7_RDWR : return "read/write"; break;
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case DBREG_DR7_WRONLY : return "write"; break;
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default : return "invalid"; break;
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}
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return (dbreg_clr_watchpoint((vm_offset_t)addr, (vm_size_t)size));
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}
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void
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db_md_list_watchpoints(void)
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{
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struct dbreg d;
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int i, len, type;
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fill_dbregs(NULL, &d);
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db_printf("\nhardware watchpoints:\n");
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db_printf(" watch status type len address\n");
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db_printf(" ----- -------- ---------- --- ----------\n");
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for (i = 0; i < 4; i++) {
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if (DBREG_DR7_ENABLED(d.dr[7], i)) {
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type = DBREG_DR7_ACCESS(d.dr[7], i);
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len = DBREG_DR7_LEN(d.dr[7], i);
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db_printf(" %-5d %-8s %10s %3d ",
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i, "enabled", watchtype_str(type), len + 1);
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db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
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db_printf("\n");
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} else {
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db_printf(" %-5d disabled\n", i);
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}
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}
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db_printf("\ndebug register values:\n");
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for (i = 0; i < 8; i++)
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if (i != 4 && i != 5)
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db_printf(" dr%d 0x%08x\n", i, DBREG_DRX(&d, i));
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db_printf("\n");
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dbreg_list_watchpoints();
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}
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@ -120,6 +120,9 @@ vm_paddr_t cpu_getmaxphyaddr(void);
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bool cpu_mwait_usable(void);
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void cpu_probe_amdc1e(void);
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void cpu_setregs(void);
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int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size);
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int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size);
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void dbreg_list_watchpoints(void);
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bool disable_wp(void);
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void restore_wp(bool old_wp);
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void finishidentcpu(void);
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267
sys/x86/x86/dbreg.c
Normal file
267
sys/x86/x86/dbreg.c
Normal file
@ -0,0 +1,267 @@
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/*-
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* Mach Operating System
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* Copyright (c) 1991,1990 Carnegie Mellon University
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* All Rights Reserved.
|
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*
|
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* Permission to use, copy, modify and distribute this software and its
|
||||
* documentation is hereby granted, provided that both the copyright
|
||||
* notice and this permission notice appear in all copies of the
|
||||
* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
|
||||
*
|
||||
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
|
||||
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
|
||||
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
|
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*
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||||
* Carnegie Mellon requests users of this software to return to
|
||||
*
|
||||
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
|
||||
* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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||||
* any improvements or extensions that they make and grant Carnegie the
|
||||
* rights to redistribute these changes.
|
||||
*/
|
||||
|
||||
#include "opt_ddb.h"
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/pcpu.h>
|
||||
#include <sys/smp.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <machine/frame.h>
|
||||
#include <machine/md_var.h>
|
||||
|
||||
#include <ddb/ddb.h>
|
||||
#include <ddb/db_sym.h>
|
||||
|
||||
#define NDBREGS 4
|
||||
#ifdef __amd64__
|
||||
#define MAXWATCHSIZE 8
|
||||
#else
|
||||
#define MAXWATCHSIZE 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set a watchpoint in the debug register denoted by 'watchnum'.
|
||||
*/
|
||||
static void
|
||||
dbreg_set_watchreg(int watchnum, vm_offset_t watchaddr, vm_size_t size,
|
||||
int access, struct dbreg *d)
|
||||
{
|
||||
int len;
|
||||
|
||||
MPASS(watchnum >= 0 && watchnum < NDBREGS);
|
||||
|
||||
/* size must be 1 for an execution breakpoint */
|
||||
if (access == DBREG_DR7_EXEC)
|
||||
size = 1;
|
||||
|
||||
/*
|
||||
* we can watch a 1, 2, or 4 byte sized location
|
||||
*/
|
||||
switch (size) {
|
||||
case 1:
|
||||
len = DBREG_DR7_LEN_1;
|
||||
break;
|
||||
case 2:
|
||||
len = DBREG_DR7_LEN_2;
|
||||
break;
|
||||
case 4:
|
||||
len = DBREG_DR7_LEN_4;
|
||||
break;
|
||||
#if MAXWATCHSIZE >= 8
|
||||
case 8:
|
||||
len = DBREG_DR7_LEN_8;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
/* clear the bits we are about to affect */
|
||||
d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
|
||||
|
||||
/* set drN register to the address, N=watchnum */
|
||||
DBREG_DRX(d, watchnum) = watchaddr;
|
||||
|
||||
/* enable the watchpoint */
|
||||
d->dr[7] |= DBREG_DR7_SET(watchnum, len, access,
|
||||
DBREG_DR7_GLOBAL_ENABLE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove a watchpoint from the debug register denoted by 'watchnum'.
|
||||
*/
|
||||
static void
|
||||
dbreg_clr_watchreg(int watchnum, struct dbreg *d)
|
||||
{
|
||||
MPASS(watchnum >= 0 && watchnum < NDBREGS);
|
||||
|
||||
d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
|
||||
DBREG_DRX(d, watchnum) = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sync the debug registers. Other cores will read these values from the PCPU
|
||||
* area when they resume. See amd64_db_resume_dbreg() below.
|
||||
*/
|
||||
static void
|
||||
dbreg_sync(struct dbreg *dp)
|
||||
{
|
||||
#ifdef __amd64__
|
||||
struct pcpu *pc;
|
||||
int cpu, c;
|
||||
|
||||
cpu = PCPU_GET(cpuid);
|
||||
CPU_FOREACH(c) {
|
||||
if (c == cpu)
|
||||
continue;
|
||||
pc = pcpu_find(c);
|
||||
memcpy(pc->pc_dbreg, dp, sizeof(*dp));
|
||||
pc->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size)
|
||||
{
|
||||
struct dbreg *d;
|
||||
int avail, i, wsize;
|
||||
|
||||
#ifdef __amd64__
|
||||
d = (struct dbreg *)PCPU_PTR(dbreg);
|
||||
#else
|
||||
/* debug registers aren't stored in PCPU on i386. */
|
||||
struct dbreg d_temp;
|
||||
d = &d_temp;
|
||||
#endif
|
||||
|
||||
fill_dbregs(NULL, d);
|
||||
|
||||
/*
|
||||
* Check if there are enough available registers to cover the desired
|
||||
* area.
|
||||
*/
|
||||
avail = 0;
|
||||
for (i = 0; i < NDBREGS; i++) {
|
||||
if (!DBREG_DR7_ENABLED(d->dr[7], i))
|
||||
avail++;
|
||||
}
|
||||
|
||||
if (avail * MAXWATCHSIZE < size)
|
||||
return (-1);
|
||||
|
||||
for (i = 0; i < NDBREGS && size > 0; i++) {
|
||||
if (!DBREG_DR7_ENABLED(d->dr[7], i)) {
|
||||
if ((size >= 8 || (avail == 1 && size > 4)) &&
|
||||
MAXWATCHSIZE == 8)
|
||||
wsize = 8;
|
||||
else if (size > 2)
|
||||
wsize = 4;
|
||||
else
|
||||
wsize = size;
|
||||
dbreg_set_watchreg(i, addr, wsize, DBREG_DR7_WRONLY, d);
|
||||
addr += wsize;
|
||||
size -= wsize;
|
||||
avail--;
|
||||
}
|
||||
}
|
||||
|
||||
set_dbregs(NULL, d);
|
||||
dbreg_sync(d);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size)
|
||||
{
|
||||
struct dbreg *d;
|
||||
int i;
|
||||
|
||||
#ifdef __amd64__
|
||||
d = (struct dbreg *)PCPU_PTR(dbreg);
|
||||
#else
|
||||
/* debug registers aren't stored in PCPU on i386. */
|
||||
struct dbreg d_temp;
|
||||
d = &d_temp;
|
||||
#endif
|
||||
fill_dbregs(NULL, d);
|
||||
|
||||
for (i = 0; i < NDBREGS; i++) {
|
||||
if (DBREG_DR7_ENABLED(d->dr[7], i)) {
|
||||
if (DBREG_DRX((d), i) >= addr &&
|
||||
DBREG_DRX((d), i) < addr + size)
|
||||
dbreg_clr_watchreg(i, d);
|
||||
}
|
||||
}
|
||||
|
||||
set_dbregs(NULL, d);
|
||||
dbreg_sync(d);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef DDB
|
||||
static const char *
|
||||
watchtype_str(int type)
|
||||
{
|
||||
|
||||
switch (type) {
|
||||
case DBREG_DR7_EXEC:
|
||||
return ("execute");
|
||||
case DBREG_DR7_RDWR:
|
||||
return ("read/write");
|
||||
case DBREG_DR7_WRONLY:
|
||||
return ("write");
|
||||
default:
|
||||
return ("invalid");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
dbreg_list_watchpoints(void)
|
||||
{
|
||||
struct dbreg d;
|
||||
int i, len, type;
|
||||
|
||||
fill_dbregs(NULL, &d);
|
||||
|
||||
db_printf("\nhardware watchpoints:\n");
|
||||
db_printf(" watch status type len address\n");
|
||||
db_printf(" ----- -------- ---------- --- ----------\n");
|
||||
for (i = 0; i < NDBREGS; i++) {
|
||||
if (DBREG_DR7_ENABLED(d.dr[7], i)) {
|
||||
type = DBREG_DR7_ACCESS(d.dr[7], i);
|
||||
len = DBREG_DR7_LEN(d.dr[7], i);
|
||||
db_printf(" %-5d %-8s %10s %3d ",
|
||||
i, "enabled", watchtype_str(type), len + 1);
|
||||
db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
|
||||
db_printf("\n");
|
||||
} else {
|
||||
db_printf(" %-5d disabled\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __amd64__
|
||||
/* Sync debug registers when resuming from debugger. */
|
||||
void
|
||||
amd64_db_resume_dbreg(void)
|
||||
{
|
||||
struct dbreg *d;
|
||||
|
||||
switch (PCPU_GET(dbreg_cmd)) {
|
||||
case PC_DBREG_CMD_LOAD:
|
||||
d = (struct dbreg *)PCPU_PTR(dbreg);
|
||||
set_dbregs(NULL, d);
|
||||
PCPU_SET(dbreg_cmd, PC_DBREG_CMD_NONE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user