arm64: xilinx: gpio: Add support for ZynqMP SoC
Add support for the gpio controller found in the ZynqMP SoC. The registers are the same as the Zynq 7000, just the number of banks/pins per banks differs. Sponsored by: Beckhoff Automation GmbH & Co. KG MFC after: 2 weeks
This commit is contained in:
Emmanuel Vadot
parent
b07fed8180
commit
c15106da82
@ -70,30 +70,49 @@ __FBSDID("$FreeBSD$");
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#include "gpio_if.h"
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#define ZYNQ_MAX_BANK 4
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#define ZYNQ7_MAX_BANK 4
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#define ZYNQMP_MAX_BANK 6
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/* Zynq 7000 */
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#define ZYNQ_BANK0_PIN_MIN 0
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#define ZYNQ_BANK0_NPIN 32
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#define ZYNQ_BANK1_PIN_MIN 32
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#define ZYNQ_BANK1_NPIN 22
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#define ZYNQ_BANK2_PIN_MIN 64
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#define ZYNQ_BANK2_NPIN 32
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#define ZYNQ_BANK3_PIN_MIN 96
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#define ZYNQ_BANK3_NPIN 32
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#define ZYNQ_PIN_MIO_MIN 0
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#define ZYNQ_PIN_MIO_MAX 54
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#define ZYNQ_PIN_EMIO_MIN 64
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#define ZYNQ_PIN_EMIO_MAX 118
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#define ZYNQ7_BANK0_PIN_MIN 0
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#define ZYNQ7_BANK0_NPIN 32
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#define ZYNQ7_BANK1_PIN_MIN 32
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#define ZYNQ7_BANK1_NPIN 22
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#define ZYNQ7_BANK2_PIN_MIN 64
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#define ZYNQ7_BANK2_NPIN 32
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#define ZYNQ7_BANK3_PIN_MIN 96
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#define ZYNQ7_BANK3_NPIN 32
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#define ZYNQ7_PIN_MIO_MIN 0
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#define ZYNQ7_PIN_MIO_MAX 54
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#define ZYNQ7_PIN_EMIO_MIN 64
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#define ZYNQ7_PIN_EMIO_MAX 118
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#define ZYNQ_BANK_NPIN(bank) (ZYNQ_BANK##bank##_NPIN)
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#define ZYNQ_BANK_PIN_MIN(bank) (ZYNQ_BANK##bank##_PIN_MIN)
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#define ZYNQ_BANK_PIN_MAX(bank) (ZYNQ_BANK##bank##_PIN_MIN + ZYNQ_BANK##bank##_NPIN - 1)
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/* ZynqMP */
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#define ZYNQMP_BANK0_PIN_MIN 0
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#define ZYNQMP_BANK0_NPIN 26
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#define ZYNQMP_BANK1_PIN_MIN 26
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#define ZYNQMP_BANK1_NPIN 26
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#define ZYNQMP_BANK2_PIN_MIN 52
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#define ZYNQMP_BANK2_NPIN 26
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#define ZYNQMP_BANK3_PIN_MIN 78
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#define ZYNQMP_BANK3_NPIN 32
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#define ZYNQMP_BANK4_PIN_MIN 110
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#define ZYNQMP_BANK4_NPIN 32
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#define ZYNQMP_BANK5_PIN_MIN 142
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#define ZYNQMP_BANK5_NPIN 32
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#define ZYNQMP_PIN_MIO_MIN 0
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#define ZYNQMP_PIN_MIO_MAX 77
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#define ZYNQMP_PIN_EMIO_MIN 78
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#define ZYNQMP_PIN_EMIO_MAX 174
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#define ZYNQ_PIN_IS_MIO(pin) (pin >= ZYNQ_PIN_MIO_MIN && \
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pin <= ZYNQ_PIN_MIO_MAX)
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#define ZYNQ_PIN_IS_EMIO(pin) (pin >= ZYNQ_PIN_EMIO_MIN && \
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pin <= ZYNQ_PIN_EMIO_MAX)
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#define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN)
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#define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN)
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#define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank##_NPIN - 1)
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#define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \
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pin <= ZYNQ##type##_PIN_MIO_MAX)
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#define ZYNQ_PIN_IS_EMIO(type, pin) (pin >= ZYNQ##type##_PIN_EMIO_MIN && \
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pin <= ZYNQ##type##_PIN_EMIO_MAX)
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#define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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@ -102,12 +121,18 @@ __FBSDID("$FreeBSD$");
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"gpio", MTX_DEF)
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#define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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enum zynq_gpio_type {
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ZYNQ_7000 = 0,
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ZYNQMP,
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};
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struct zynq_gpio_conf {
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char *name;
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uint32_t nbanks;
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uint32_t maxpin;
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uint32_t bank_min[ZYNQ_MAX_BANK];
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uint32_t bank_max[ZYNQ_MAX_BANK];
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char *name;
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enum zynq_gpio_type type;
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uint32_t nbanks;
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uint32_t maxpin;
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uint32_t bank_min[ZYNQMP_MAX_BANK];
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uint32_t bank_max[ZYNQMP_MAX_BANK];
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};
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struct zy7_gpio_softc {
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@ -120,20 +145,41 @@ struct zy7_gpio_softc {
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static struct zynq_gpio_conf z7_gpio_conf = {
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.name = "Zynq-7000 GPIO Controller",
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.nbanks = ZYNQ_MAX_BANK,
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.maxpin = ZYNQ_PIN_EMIO_MAX,
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.bank_min[0] = ZYNQ_BANK_PIN_MIN(0),
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.bank_max[0] = ZYNQ_BANK_PIN_MAX(0),
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.bank_min[1] = ZYNQ_BANK_PIN_MIN(1),
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.bank_max[1] = ZYNQ_BANK_PIN_MAX(1),
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.bank_min[2] = ZYNQ_BANK_PIN_MIN(2),
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.bank_max[2] = ZYNQ_BANK_PIN_MAX(2),
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.bank_min[3] = ZYNQ_BANK_PIN_MIN(3),
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.bank_max[3] = ZYNQ_BANK_PIN_MAX(3),
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.type = ZYNQ_7000,
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.nbanks = ZYNQ7_MAX_BANK,
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.maxpin = ZYNQ7_PIN_EMIO_MAX,
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.bank_min[0] = ZYNQ_BANK_PIN_MIN(7, 0),
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.bank_max[0] = ZYNQ_BANK_PIN_MAX(7, 0),
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.bank_min[1] = ZYNQ_BANK_PIN_MIN(7, 1),
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.bank_max[1] = ZYNQ_BANK_PIN_MAX(7, 1),
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.bank_min[2] = ZYNQ_BANK_PIN_MIN(7, 2),
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.bank_max[2] = ZYNQ_BANK_PIN_MAX(7, 2),
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.bank_min[3] = ZYNQ_BANK_PIN_MIN(7, 3),
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.bank_max[3] = ZYNQ_BANK_PIN_MAX(7, 3),
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};
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static struct zynq_gpio_conf zynqmp_gpio_conf = {
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.name = "ZynqMP GPIO Controller",
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.type = ZYNQMP,
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.nbanks = ZYNQMP_MAX_BANK,
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.maxpin = ZYNQMP_PIN_EMIO_MAX,
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.bank_min[0] = ZYNQ_BANK_PIN_MIN(MP, 0),
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.bank_max[0] = ZYNQ_BANK_PIN_MAX(MP, 0),
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.bank_min[1] = ZYNQ_BANK_PIN_MIN(MP, 1),
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.bank_max[1] = ZYNQ_BANK_PIN_MAX(MP, 1),
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.bank_min[2] = ZYNQ_BANK_PIN_MIN(MP, 2),
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.bank_max[2] = ZYNQ_BANK_PIN_MAX(MP, 2),
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.bank_min[3] = ZYNQ_BANK_PIN_MIN(MP, 3),
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.bank_max[3] = ZYNQ_BANK_PIN_MAX(MP, 3),
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.bank_min[4] = ZYNQ_BANK_PIN_MIN(MP, 4),
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.bank_max[4] = ZYNQ_BANK_PIN_MAX(MP, 4),
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.bank_min[5] = ZYNQ_BANK_PIN_MIN(MP, 5),
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.bank_max[5] = ZYNQ_BANK_PIN_MAX(MP, 5),
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};
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static struct ofw_compat_data compat_data[] = {
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{"xlnx,zy7_gpio", (uintptr_t)&z7_gpio_conf},
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{"xlnx,zynqmp-gpio-1.0", (uintptr_t)&zynqmp_gpio_conf},
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{NULL, 0},
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};
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@ -212,15 +258,31 @@ zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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static int
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zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct zy7_gpio_softc *sc;
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uint32_t emio_min;
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bool is_mio;
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sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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if (ZYNQ_PIN_IS_MIO(pin)) {
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switch (sc->conf->type) {
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case ZYNQ_7000:
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is_mio = ZYNQ_PIN_IS_MIO(7, pin);
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emio_min = ZYNQ7_PIN_EMIO_MIN;
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break;
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case ZYNQMP:
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is_mio = ZYNQ_PIN_IS_MIO(MP, pin);
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emio_min = ZYNQMP_PIN_EMIO_MIN;
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break;
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default:
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return (EINVAL);
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}
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if (is_mio) {
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snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
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name[GPIOMAXNAME - 1] = '\0';
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} else {
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snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - ZYNQ_PIN_EMIO_MIN);
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snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - emio_min);
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name[GPIOMAXNAME - 1] = '\0';
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}
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@ -692,3 +692,4 @@ arm64/rockchip/clk/rk3568_pmucru.c optional fdt soc_rockchip_rk3568
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# Xilinx
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arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq fdt
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arm/xilinx/zy7_gpio.c optional gpio soc_xilinx_zynq fdt
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