e1000: consistently use the hw variables
It's rather confusing when adapter->hw and hw are mixed and matched
within a particular function.
Some of this was missed in cd1cf2fc1d
and r353778 respectively.
This commit is contained in:
Marius Strobl
parent
f1c010d9f9
commit
c1655b0f89
@ -828,7 +828,7 @@ em_if_attach_pre(if_ctx_t ctx)
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device_printf(dev, "attach_pre capping queues at %d\n",
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scctx->isc_ntxqsets_max);
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if (adapter->hw.mac.type >= igb_mac_min) {
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if (hw.mac.type >= igb_mac_min) {
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scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
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scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
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scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
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@ -840,7 +840,7 @@ em_if_attach_pre(if_ctx_t ctx)
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scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
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scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
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CSUM_IP6_TCP | CSUM_IP6_UDP;
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if (adapter->hw.mac.type != e1000_82575)
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if (hw.mac.type != e1000_82575)
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scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
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/*
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** Some new devices, as with ixgbe, now may
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@ -848,7 +848,7 @@ em_if_attach_pre(if_ctx_t ctx)
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** track of which is used.
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*/
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scctx->isc_msix_bar = pci_msix_table_bar(dev);
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} else if (adapter->hw.mac.type >= em_mac_min) {
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} else if (hw.mac.type >= em_mac_min) {
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scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
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scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
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scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
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@ -880,7 +880,7 @@ em_if_attach_pre(if_ctx_t ctx)
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* We support MSI-X with 82574 only, but indicate to iflib(4)
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* that it shall give MSI at least a try with other devices.
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*/
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if (adapter->hw.mac.type == e1000_82574) {
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if (hw.mac.type == e1000_82574) {
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scctx->isc_msix_bar = pci_msix_table_bar(dev);;
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} else {
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scctx->isc_msix_bar = -1;
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@ -894,7 +894,7 @@ em_if_attach_pre(if_ctx_t ctx)
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scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
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scctx->isc_txrx = &lem_txrx;
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scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
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if (adapter->hw.mac.type < e1000_82543)
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if (hw.mac.type < e1000_82543)
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scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
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/* INTx only */
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scctx->isc_msix_bar = 0;
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@ -987,9 +987,9 @@ em_if_attach_pre(if_ctx_t ctx)
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hw->phy.autoneg_wait_to_complete = FALSE;
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hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
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if (adapter->hw.mac.type < em_mac_min) {
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e1000_init_script_state_82541(&adapter->hw, TRUE);
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e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
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if (hw.mac.type < em_mac_min) {
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e1000_init_script_state_82541(hw, TRUE);
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e1000_set_tbi_compatibility_82543(hw, TRUE);
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}
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/* Copper options */
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if (hw->phy.media_type == e1000_media_type_copper) {
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@ -1002,7 +1002,7 @@ em_if_attach_pre(if_ctx_t ctx)
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* Set the frame limits assuming
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* standard ethernet sized frames.
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*/
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scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
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scctx->isc_max_frame_size = hw.mac.max_frame_size =
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ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
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/*
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@ -1205,7 +1205,7 @@ em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
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struct adapter *adapter = iflib_get_softc(ctx);
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if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
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IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
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IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
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switch (adapter->hw.mac.type) {
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case e1000_82571:
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@ -1793,7 +1793,7 @@ em_if_update_admin_status(if_ctx_t ctx)
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break;
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case e1000_media_type_internal_serdes:
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e1000_check_for_link(hw);
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link_check = adapter->hw.mac.serdes_has_link;
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link_check = hw.mac.serdes_has_link;
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break;
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/* VF device is type_unknown */
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case e1000_media_type_unknown:
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@ -1840,8 +1840,8 @@ em_if_update_admin_status(if_ctx_t ctx)
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(hw->phy.id == I210_I_PHY_ID))
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msec_delay(I210_LINK_DELAY);
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/* Reset if the media type changed. */
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if ((hw->dev_spec._82575.media_changed) &&
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(adapter->hw.mac.type >= igb_mac_min)) {
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if (hw->dev_spec._82575.media_changed &&
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hw.mac.type >= igb_mac_min) {
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hw->dev_spec._82575.media_changed = false;
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adapter->flags |= IGB_MEDIA_RESET;
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em_reset(ctx);
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@ -1864,8 +1864,7 @@ em_if_update_admin_status(if_ctx_t ctx)
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lem_smartspeed(adapter);
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else if (hw->mac.type == e1000_82574 &&
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adapter->intr_type == IFLIB_INTR_MSIX)
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E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
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E1000_IMS_LSC);
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E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
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}
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static void
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@ -2089,13 +2088,13 @@ igb_configure_queues(struct adapter *adapter)
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u32 tmp, ivar = 0, newitr = 0;
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/* First turn on RSS capability */
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if (adapter->hw.mac.type != e1000_82575)
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if (hw.mac.type != e1000_82575)
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E1000_WRITE_REG(hw, E1000_GPIE,
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E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
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E1000_GPIE_PBA | E1000_GPIE_NSICR);
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/* Turn on MSI-X */
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switch (adapter->hw.mac.type) {
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switch (hw.mac.type) {
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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@ -2494,7 +2493,7 @@ em_reset(if_ctx_t ctx)
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case e1000_ich9lan:
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case e1000_ich10lan:
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/* Boost Receive side for jumbo frames */
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if (adapter->hw.mac.max_frame_size > 4096)
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if (hw.mac.max_frame_size > 4096)
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pba = E1000_PBA_14K;
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else
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pba = E1000_PBA_10K;
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@ -2526,7 +2525,7 @@ em_reset(if_ctx_t ctx)
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pba = E1000_PBA_34K;
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break;
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default:
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if (adapter->hw.mac.max_frame_size > 8192)
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if (hw.mac.max_frame_size > 8192)
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pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
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else
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pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
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@ -2538,11 +2537,11 @@ em_reset(if_ctx_t ctx)
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pba = E1000_READ_REG(hw, E1000_PBA);
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tx_space = pba >> 16;
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pba &= 0xffff;
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min_tx = (adapter->hw.mac.max_frame_size +
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min_tx = (hw.mac.max_frame_size +
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sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
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min_tx = roundup2(min_tx, 1024);
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min_tx >>= 10;
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min_rx = adapter->hw.mac.max_frame_size;
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min_rx = hw.mac.max_frame_size;
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min_rx = roundup2(min_rx, 1024);
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min_rx >>= 10;
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if (tx_space < min_tx &&
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@ -2559,7 +2558,7 @@ em_reset(if_ctx_t ctx)
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}
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if (hw->mac.type < igb_mac_min)
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E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
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E1000_WRITE_REG(hw, E1000_PBA, pba);
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INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
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@ -2579,7 +2578,7 @@ em_reset(if_ctx_t ctx)
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*/
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rx_buffer_size = (pba & 0xffff) << 10;
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hw->fc.high_water = rx_buffer_size -
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roundup2(adapter->hw.mac.max_frame_size, 1024);
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roundup2(hw.mac.max_frame_size, 1024);
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hw->fc.low_water = hw->fc.high_water - 1500;
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if (adapter->fc) /* locally set flow control value? */
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@ -2654,7 +2653,7 @@ em_reset(if_ctx_t ctx)
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/* Issue a global reset */
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e1000_reset_hw(hw);
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if (adapter->hw.mac.type >= igb_mac_min) {
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if (hw.mac.type >= igb_mac_min) {
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E1000_WRITE_REG(hw, E1000_WUC, 0);
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} else {
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E1000_WRITE_REG(hw, E1000_WUFC, 0);
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@ -2670,7 +2669,7 @@ em_reset(if_ctx_t ctx)
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device_printf(dev, "Hardware Initialization Failed\n");
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return;
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}
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if (adapter->hw.mac.type >= igb_mac_min)
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if (hw.mac.type >= igb_mac_min)
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igb_init_dmac(adapter, pba);
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E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
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@ -2735,7 +2734,7 @@ igb_initialize_rss_mapping(struct adapter *adapter)
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u32 rss_key[10], mrqc, shift = 0;
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/* XXX? */
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if (adapter->hw.mac.type == e1000_82575)
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if (hw.mac.type == e1000_82575)
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shift = 6;
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/*
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@ -2844,11 +2843,11 @@ em_setup_interface(if_ctx_t ctx)
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* Specify the media types supported by this adapter and register
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* callbacks to update media and link information
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*/
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if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
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(adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
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if (hw.phy.media_type == e1000_media_type_fiber ||
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hw.phy.media_type == e1000_media_type_internal_serdes) {
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u_char fiber_type = IFM_1000_SX; /* default type */
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if (adapter->hw.mac.type == e1000_82545)
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if (hw.mac.type == e1000_82545)
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fiber_type = IFM_1000_LX;
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ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
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ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
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@ -2857,7 +2856,7 @@ em_setup_interface(if_ctx_t ctx)
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ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
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ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
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ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
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if (adapter->hw.phy.type != e1000_phy_ife) {
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if (hw.phy.type != e1000_phy_ife) {
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ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
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ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
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}
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@ -3032,8 +3031,8 @@ em_initialize_transmit_unit(if_ctx_t ctx)
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E1000_WRITE_REG(hw, E1000_TDH(i), 0);
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HW_DEBUGOUT2("Base = %x, Length = %x\n",
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E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
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E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
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E1000_READ_REG(hw, E1000_TDBAL(i)),
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E1000_READ_REG(hw, E1000_TDLEN(i)));
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txdctl = 0; /* clear txdctl */
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txdctl |= 0x1f; /* PTHRESH */
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@ -3047,7 +3046,7 @@ em_initialize_transmit_unit(if_ctx_t ctx)
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}
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/* Set the default values for the Tx Inter Packet Gap timer */
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switch (adapter->hw.mac.type) {
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switch (hw.mac.type) {
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case e1000_80003es2lan:
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tipg = DEFAULT_82543_TIPG_IPGR1;
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tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
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@ -3059,9 +3058,8 @@ em_initialize_transmit_unit(if_ctx_t ctx)
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tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
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break;
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default:
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if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
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(adapter->hw.phy.media_type ==
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e1000_media_type_internal_serdes))
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if (hw.phy.media_type == e1000_media_type_fiber ||
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hw.phy.media_type == e1000_media_type_internal_serdes)
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tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
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else
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tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
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@ -3069,51 +3067,50 @@ em_initialize_transmit_unit(if_ctx_t ctx)
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tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
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}
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E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
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E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
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E1000_WRITE_REG(hw, E1000_TIPG, tipg);
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E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
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if(adapter->hw.mac.type >= e1000_82540)
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E1000_WRITE_REG(&adapter->hw, E1000_TADV,
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if(hw.mac.type >= e1000_82540)
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E1000_WRITE_REG(hw, E1000_TADV,
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adapter->tx_abs_int_delay.value);
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if ((adapter->hw.mac.type == e1000_82571) ||
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(adapter->hw.mac.type == e1000_82572)) {
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tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
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if (hw.mac.type == e1000_82571 || hw.mac.type == e1000_82572) {
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tarc = E1000_READ_REG(hw, E1000_TARC(0));
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tarc |= TARC_SPEED_MODE_BIT;
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
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} else if (adapter->hw.mac.type == e1000_80003es2lan) {
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E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
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} else if (hw.mac.type == e1000_80003es2lan) {
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/* errata: program both queues to unweighted RR */
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tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
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tarc = E1000_READ_REG(hw, E1000_TARC(0));
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tarc |= 1;
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
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tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
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E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
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tarc = E1000_READ_REG(hw, E1000_TARC(1));
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tarc |= 1;
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
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} else if (adapter->hw.mac.type == e1000_82574) {
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tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
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E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
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} else if (hw.mac.type == e1000_82574) {
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tarc = E1000_READ_REG(hw, E1000_TARC(0));
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tarc |= TARC_ERRATA_BIT;
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if ( adapter->tx_num_queues > 1) {
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tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
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E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
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E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
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} else
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E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
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E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
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}
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if (adapter->tx_int_delay.value > 0)
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adapter->txd_cmd |= E1000_TXD_CMD_IDE;
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/* Program the Transmit Control Register */
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tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
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tctl = E1000_READ_REG(hw, E1000_TCTL);
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tctl &= ~E1000_TCTL_CT;
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tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
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(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
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if (adapter->hw.mac.type >= e1000_82571)
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if (hw.mac.type >= e1000_82571)
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tctl |= E1000_TCTL_MULR;
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/* This write will effectively turn on the transmit unit. */
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E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
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E1000_WRITE_REG(hw, E1000_TCTL, tctl);
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/* SPT and KBL errata workarounds */
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if (hw->mac.type == e1000_pch_spt) {
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@ -3176,9 +3173,9 @@ em_initialize_receive_unit(if_ctx_t ctx)
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if (!em_disable_crc_stripping)
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rctl |= E1000_RCTL_SECRC;
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if (adapter->hw.mac.type >= e1000_82540) {
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E1000_WRITE_REG(&adapter->hw, E1000_RADV,
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adapter->rx_abs_int_delay.value);
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if (hw.mac.type >= e1000_82540) {
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E1000_WRITE_REG(hw, E1000_RADV,
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adapter->rx_abs_int_delay.value);
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/*
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* Set the interrupt throttling rate. Value is calculated
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@ -3186,8 +3183,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
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*/
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E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
|
||||
}
|
||||
E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
|
||||
adapter->rx_int_delay.value);
|
||||
E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
|
||||
|
||||
/* Use extended rx descriptor formats */
|
||||
rfctl = E1000_READ_REG(hw, E1000_RFCTL);
|
||||
@ -3207,9 +3203,9 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
|
||||
rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
|
||||
if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
|
||||
adapter->hw.mac.type >= e1000_82543) {
|
||||
hw.mac.type >= e1000_82543) {
|
||||
if (adapter->tx_num_queues > 1) {
|
||||
if (adapter->hw.mac.type >= igb_mac_min) {
|
||||
if (hw.mac.type >= igb_mac_min) {
|
||||
rxcsum |= E1000_RXCSUM_PCSD;
|
||||
if (hw->mac.type != e1000_82575)
|
||||
rxcsum |= E1000_RXCSUM_CRCOFL;
|
||||
@ -3218,11 +3214,11 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
E1000_RXCSUM_IPOFL |
|
||||
E1000_RXCSUM_PCSD;
|
||||
} else {
|
||||
if (adapter->hw.mac.type >= igb_mac_min)
|
||||
if (hw.mac.type >= igb_mac_min)
|
||||
rxcsum |= E1000_RXCSUM_IPPCSE;
|
||||
else
|
||||
rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
|
||||
if (adapter->hw.mac.type > e1000_82575)
|
||||
if (hw.mac.type > e1000_82575)
|
||||
rxcsum |= E1000_RXCSUM_CRCOFL;
|
||||
}
|
||||
} else
|
||||
@ -3231,7 +3227,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
|
||||
|
||||
if (adapter->rx_num_queues > 1) {
|
||||
if (adapter->hw.mac.type >= igb_mac_min)
|
||||
if (hw.mac.type >= igb_mac_min)
|
||||
igb_initialize_rss_mapping(adapter);
|
||||
else
|
||||
em_initialize_rss_mapping(adapter);
|
||||
@ -3271,14 +3267,11 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
* Only write to RXDCTL(1) if there is a need for different
|
||||
* settings.
|
||||
*/
|
||||
|
||||
if (((adapter->hw.mac.type == e1000_ich9lan) ||
|
||||
(adapter->hw.mac.type == e1000_pch2lan) ||
|
||||
(adapter->hw.mac.type == e1000_ich10lan)) &&
|
||||
(if_getmtu(ifp) > ETHERMTU)) {
|
||||
if ((hw.mac.type == e1000_ich9lan || hw.mac.type == e1000_pch2lan ||
|
||||
hw.mac.type == e1000_ich10lan) && (if_getmtu(ifp) > ETHERMTU)) {
|
||||
u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
|
||||
E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
|
||||
} else if (adapter->hw.mac.type == e1000_82574) {
|
||||
} else if (hw.mac.type == e1000_82574) {
|
||||
for (int i = 0; i < adapter->rx_num_queues; i++) {
|
||||
u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
|
||||
rxdctl |= 0x20; /* PTHRESH */
|
||||
@ -3287,7 +3280,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
rxdctl |= 1 << 24; /* Switch to granularity */
|
||||
E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
|
||||
}
|
||||
} else if (adapter->hw.mac.type >= igb_mac_min) {
|
||||
} else if (hw.mac.type >= igb_mac_min) {
|
||||
u32 psize, srrctl = 0;
|
||||
|
||||
if (if_getmtu(ifp) > ETHERMTU) {
|
||||
@ -3303,7 +3296,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
/* are we on a vlan? */
|
||||
if (ifp->if_vlantrunk != NULL)
|
||||
psize += VLAN_TAG_SIZE;
|
||||
E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
|
||||
E1000_WRITE_REG(hw, E1000_RLPML, psize);
|
||||
} else {
|
||||
srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
|
||||
rctl |= E1000_RCTL_SZ_2048;
|
||||
@ -3349,7 +3342,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
rxdctl |= IGB_RX_WTHRESH << 16;
|
||||
E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
|
||||
}
|
||||
} else if (adapter->hw.mac.type >= e1000_pch2lan) {
|
||||
} else if (hw.mac.type >= e1000_pch2lan) {
|
||||
if (if_getmtu(ifp) > ETHERMTU)
|
||||
e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
|
||||
else
|
||||
@ -3359,7 +3352,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
|
||||
/* Make sure VLAN Filters are off */
|
||||
rctl &= ~E1000_RCTL_VFE;
|
||||
|
||||
if (adapter->hw.mac.type < igb_mac_min) {
|
||||
if (hw.mac.type < igb_mac_min) {
|
||||
if (adapter->rx_mbuf_sz == MCLBYTES)
|
||||
rctl |= E1000_RCTL_SZ_2048;
|
||||
else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
|
||||
@ -3822,7 +3815,7 @@ em_enable_phy_wakeup(struct adapter *adapter)
|
||||
e1000_copy_rx_addrs_to_phy_ich8lan(hw);
|
||||
|
||||
/* copy MAC MTA to PHY MTA */
|
||||
for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
|
||||
for (int i = 0; i < hw.mac.mta_reg_count; i++) {
|
||||
mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
|
||||
e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
|
||||
e1000_write_phy_reg(hw, BM_MTA(i) + 1,
|
||||
@ -3830,7 +3823,7 @@ em_enable_phy_wakeup(struct adapter *adapter)
|
||||
}
|
||||
|
||||
/* configure PHY Rx Control register */
|
||||
e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
|
||||
e1000_read_phy_reg(hw, BM_RCTL, &preg);
|
||||
mreg = E1000_READ_REG(hw, E1000_RCTL);
|
||||
if (mreg & E1000_RCTL_UPE)
|
||||
preg |= BM_RCTL_UPE;
|
||||
@ -3847,7 +3840,7 @@ em_enable_phy_wakeup(struct adapter *adapter)
|
||||
mreg = E1000_READ_REG(hw, E1000_CTRL);
|
||||
if (mreg & E1000_CTRL_RFCE)
|
||||
preg |= BM_RCTL_RFCE;
|
||||
e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
|
||||
e1000_write_phy_reg(hw, BM_RCTL, preg);
|
||||
|
||||
/* enable PHY wakeup in MAC register */
|
||||
E1000_WRITE_REG(hw, E1000_WUC,
|
||||
@ -3855,8 +3848,8 @@ em_enable_phy_wakeup(struct adapter *adapter)
|
||||
E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
|
||||
|
||||
/* configure and enable PHY wakeup in PHY registers */
|
||||
e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
|
||||
e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
|
||||
e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
|
||||
e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
|
||||
|
||||
/* activate PHY wakeup */
|
||||
ret = hw->phy.ops.acquire(hw);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user