Intel QPI chipsets actually provide two extra "non-core" PCI buses that
provide PCI devices for various hardware such as memory controllers, etc. These PCI buses are not enumerated via ACPI however. Add qpi(4) psuedo bus and Host-PCI bridge drivers to enumerate these buses. Currently the driver uses the CPU ID to determine the bridges' presence. In collaboration with: Joseph Golio @ Isilon Systems MFC after: 2 weeks
This commit is contained in:
John Baldwin
parent
3e1700a5f8
commit
c2175767b7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=211820
@ -317,6 +317,7 @@ x86/isa/isa.c standard
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x86/isa/isa_dma.c standard
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x86/isa/nmi.c standard
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x86/isa/orm.c optional isa
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x86/pci/qpi.c standard
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x86/x86/io_apic.c standard
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x86/x86/local_apic.c standard
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x86/x86/mca.c standard
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@ -394,6 +394,7 @@ x86/isa/isa.c optional isa
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x86/isa/isa_dma.c optional isa
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x86/isa/nmi.c standard
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x86/isa/orm.c optional isa
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x86/pci/qpi.c standard
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x86/x86/io_apic.c optional apic
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x86/x86/local_apic.c optional apic
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x86/x86/mca.c standard
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286
sys/x86/pci/qpi.c
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286
sys/x86/pci/qpi.c
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@ -0,0 +1,286 @@
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/*-
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* Copyright (c) 2010 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This driver provides a psuedo-bus to enumerate the PCI buses
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* present on a sytem using a QPI chipset. It creates a qpi0 bus that
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* is a child of nexus0 and then creates two Host-PCI bridges as a
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* child of that.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/specialreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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struct qpi_device {
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int qd_pcibus;
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};
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static MALLOC_DEFINE(M_QPI, "qpidrv", "qpi system device");
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static void
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qpi_identify(driver_t *driver, device_t parent)
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{
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/* Check CPUID to ensure this is an i7 CPU of some sort. */
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if (!(cpu_vendor_id == CPU_VENDOR_INTEL && CPUID_TO_FAMILY(cpu_id) &&
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(CPUID_TO_MODEL(cpu_id) == 0x1a || CPUID_TO_MODEL(cpu_id) == 0x2c)))
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return;
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/* PCI config register access is required. */
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if (pci_cfgregopen() == 0)
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return;
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/* Add a qpi bus device. */
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if (BUS_ADD_CHILD(parent, 20, "qpi", -1) == NULL)
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panic("Failed to add qpi bus");
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}
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static int
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qpi_probe(device_t dev)
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{
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device_set_desc(dev, "QPI system bus");
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return (BUS_PROBE_SPECIFIC);
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}
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static int
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qpi_attach(device_t dev)
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{
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struct qpi_device *qdev;
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device_t child;
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/*
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* Add two Host-PCI bridge devices, one for PCI bus 254 and
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* one for PCI bus 255.
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*/
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child = BUS_ADD_CHILD(dev, 0, "pcib", -1);
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if (child == NULL)
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panic("%s: failed to add pci bus 254",
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device_get_nameunit(dev));
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qdev = malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK);
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qdev->qd_pcibus = 254;
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device_set_ivars(child, qdev);
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child = BUS_ADD_CHILD(dev, 0, "pcib", -1);
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if (child == NULL)
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panic("%s: failed to add pci bus 255",
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device_get_nameunit(dev));
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qdev = malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK);
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qdev->qd_pcibus = 255;
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device_set_ivars(child, qdev);
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return (bus_generic_attach(dev));
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}
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static int
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qpi_print_child(device_t bus, device_t child)
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{
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struct qpi_device *qdev;
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int retval = 0;
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qdev = device_get_ivars(child);
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retval += bus_print_child_header(bus, child);
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if (qdev->qd_pcibus != -1)
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retval += printf(" pcibus %d", qdev->qd_pcibus);
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retval += bus_print_child_footer(bus, child);
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return (retval);
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}
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static int
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qpi_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct qpi_device *qdev;
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qdev = device_get_ivars(child);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = qdev->qd_pcibus;
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break;
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default:
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return (ENOENT);
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}
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return (0);
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}
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static device_method_t qpi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, qpi_identify),
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DEVMETHOD(device_probe, qpi_probe),
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DEVMETHOD(device_attach, qpi_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, qpi_print_child),
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DEVMETHOD(bus_add_child, bus_generic_add_child),
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DEVMETHOD(bus_read_ivar, qpi_read_ivar),
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DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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{ 0, 0 }
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};
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static devclass_t qpi_devclass;
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DEFINE_CLASS_0(qpi, qpi_driver, qpi_methods, 0);
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DRIVER_MODULE(qpi, nexus, qpi_driver, qpi_devclass, 0, 0);
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static int
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qpi_pcib_probe(device_t dev)
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{
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device_set_desc(dev, "QPI Host-PCI bridge");
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return (BUS_PROBE_SPECIFIC);
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}
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static int
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qpi_pcib_attach(device_t dev)
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{
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device_add_child(dev, "pci", pcib_get_bus(dev));
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return (bus_generic_attach(dev));
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}
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static int
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qpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = pcib_get_bus(dev);
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return (0);
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default:
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return (ENOENT);
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}
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}
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static uint32_t
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qpi_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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return (pci_cfgregread(bus, slot, func, reg, bytes));
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}
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static void
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qpi_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t data, int bytes)
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{
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pci_cfgregwrite(bus, slot, func, reg, data, bytes);
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}
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static int
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qpi_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
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int *irqs)
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{
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device_t bus;
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bus = device_get_parent(pcib);
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return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
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irqs));
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}
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static int
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qpi_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
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{
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device_t bus;
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bus = device_get_parent(pcib);
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return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
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}
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static int
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qpi_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
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uint32_t *data)
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{
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device_t bus;
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bus = device_get_parent(pcib);
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return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
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}
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static device_method_t qpi_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, qpi_pcib_probe),
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DEVMETHOD(device_attach, qpi_pcib_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, qpi_pcib_read_ivar),
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DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, qpi_pcib_read_config),
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DEVMETHOD(pcib_write_config, qpi_pcib_write_config),
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DEVMETHOD(pcib_alloc_msi, qpi_pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, pcib_release_msi),
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DEVMETHOD(pcib_alloc_msix, qpi_pcib_alloc_msix),
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DEVMETHOD(pcib_release_msix, pcib_release_msix),
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DEVMETHOD(pcib_map_msi, qpi_pcib_map_msi),
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{0, 0}
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};
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static devclass_t qpi_pcib_devclass;
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DEFINE_CLASS_0(pcib, qpi_pcib_driver, qpi_pcib_methods, 0);
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DRIVER_MODULE(pcib, qpi, qpi_pcib_driver, qpi_pcib_devclass, 0, 0);
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