Pull in r352607 from upstream llvm trunk (by Craig Topper):
[X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r352608 from upstream llvm trunk (by Craig Topper): [X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code. I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences. Pull in r353015 from upstream llvm trunk (by Craig Topper): [X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. Pull in r353061 from upstream llvm trunk (by Craig Topper): [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206
This commit is contained in:
Dimitry Andric
parent
8e69ae1c97
commit
c232a6c2f7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang800-import/; revision=343955
@ -1115,8 +1115,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
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}
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// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
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if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
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RegNo = X86::ST0;
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if (RegNo == X86::ST0) {
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Parser.Lex(); // Eat 'st'
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// Check to see if we have '(4)' after %st.
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@ -200,3 +200,14 @@ void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
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O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
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<< markup(">");
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}
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void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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unsigned Reg = Op.getReg();
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// Override the default printing to print st(0) instead st.
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if (Reg == X86::ST0)
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OS << markup("<reg:") << "%st(0)" << markup(">");
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else
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printRegName(OS, Reg);
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}
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@ -44,6 +44,7 @@ class X86ATTInstPrinter final : public X86InstPrinterCommon {
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void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
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void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
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void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
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void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printMemReference(MI, OpNo, O);
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@ -160,3 +160,14 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
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O << formatImm(MI->getOperand(Op).getImm() & 0xff);
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}
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void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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unsigned Reg = Op.getReg();
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// Override the default printing to print st(0) instead st.
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if (Reg == X86::ST0)
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OS << "st(0)";
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else
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printRegName(OS, Reg);
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}
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@ -39,6 +39,7 @@ class X86IntelInstPrinter final : public X86InstPrinterCommon {
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void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
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void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printMemReference(MI, OpNo, O);
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@ -42507,6 +42507,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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if (StringRef("{flags}").equals_lower(Constraint))
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return std::make_pair(X86::EFLAGS, &X86::CCRRegClass);
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// dirflag -> DF
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if (StringRef("{dirflag}").equals_lower(Constraint))
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return std::make_pair(X86::DF, &X86::DFCCRRegClass);
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// fpsr -> FPSW
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if (StringRef("{fpsr}").equals_lower(Constraint))
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return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
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// 'A' means [ER]AX + [ER]DX.
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if (Constraint == "A") {
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if (Subtarget.is64Bit())
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@ -230,7 +230,7 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
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} // mayLoad = 1, hasSideEffects = 1
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}
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let Defs = [FPSW] in {
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let Defs = [FPSW], Uses = [FPCW] in {
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// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
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// resources.
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let hasNoSchedulingInfo = 1 in {
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@ -258,42 +258,42 @@ defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
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} // Defs = [FPSW]
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class FPST0rInst<Format fp, string asm>
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: FPI<0xD8, fp, (outs), (ins RST:$op), asm>;
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: FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
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class FPrST0Inst<Format fp, string asm>
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: FPI<0xDC, fp, (outs), (ins RST:$op), asm>;
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: FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;
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class FPrST0PInst<Format fp, string asm>
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: FPI<0xDE, fp, (outs), (ins RST:$op), asm>;
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: FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>;
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// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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let SchedRW = [WriteFAdd] in {
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def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
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def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
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def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
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def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
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def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
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def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
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def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
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def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
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def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
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let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in {
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def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
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def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
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def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
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def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;
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def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;
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def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;
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def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
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def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
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def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFCom] in {
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let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in {
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def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
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def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
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} // SchedRW
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let SchedRW = [WriteFMul] in {
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def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;
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def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">;
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def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">;
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let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in {
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def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;
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def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;
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def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFDiv] in {
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def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
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def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
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def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;
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def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
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def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
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def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
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let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in {
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def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;
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def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;
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def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
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def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">;
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def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">;
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def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">;
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} // SchedRW
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// Unary operations.
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@ -307,7 +307,7 @@ def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
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}
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let Defs = [FPSW] in {
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let Defs = [FPSW], Uses = [FPCW] in {
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let SchedRW = [WriteFSign] in {
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defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
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@ -335,7 +335,7 @@ def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
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// Versions of FP instructions that take a single memory operand. Added for the
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// disassembler; remove as they are included with patterns elsewhere.
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let SchedRW = [WriteFComLd] in {
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let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in {
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def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
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def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
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@ -398,22 +398,22 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
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"fcmovb\t{$op, %st(0)|st(0), $op}">;
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def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op),
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"fcmovbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op),
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"fcmove\t{$op, %st(0)|st(0), $op}">;
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def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
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"fcmovu\t{$op, %st(0)|st(0), $op}">;
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def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
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"fcmovnb\t{$op, %st(0)|st(0), $op}">;
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def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op),
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"fcmovnbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op),
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"fcmovne\t{$op, %st(0)|st(0), $op}">;
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def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
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"fcmovnu\t{$op, %st(0)|st(0), $op}">;
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def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
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"fcmovb\t{$op, %st|st, $op}">;
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def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op),
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"fcmovbe\t{$op, %st|st, $op}">;
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def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op),
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"fcmove\t{$op, %st|st, $op}">;
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def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op),
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"fcmovu\t{$op, %st|st, $op}">;
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def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),
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"fcmovnb\t{$op, %st|st, $op}">;
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def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),
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"fcmovnbe\t{$op, %st|st, $op}">;
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def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
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"fcmovne\t{$op, %st|st, $op}">;
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def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
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"fcmovnu\t{$op, %st|st, $op}">;
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} // Predicates = [HasCMov]
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} // SchedRW
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@ -454,7 +454,7 @@ def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i64))]>;
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} // SchedRW
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let SchedRW = [WriteStore] in {
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let SchedRW = [WriteStore], Uses = [FPCW] in {
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def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
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[(store RFP32:$src, addr:$op)]>;
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def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
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@ -489,7 +489,7 @@ def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
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def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
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def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
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} // mayStore
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} // SchedRW
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} // SchedRW, Uses = [FPCW]
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let mayLoad = 1, SchedRW = [WriteLoad] in {
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
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@ -499,7 +499,7 @@ def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
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}
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let mayStore = 1, SchedRW = [WriteStore] in {
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let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
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def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
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@ -513,7 +513,7 @@ def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
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}
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// FISTTP requires SSE3 even though it's a FPStack op.
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let Predicates = [HasSSE3], SchedRW = [WriteStore] in {
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let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in {
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def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
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[(X86fp_to_i16mem RFP32:$src, addr:$op)]>;
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def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
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@ -534,7 +534,7 @@ def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
|
||||
[(X86fp_to_i64mem RFP80:$src, addr:$op)]>;
|
||||
} // Predicates = [HasSSE3]
|
||||
|
||||
let mayStore = 1, SchedRW = [WriteStore] in {
|
||||
let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
|
||||
def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
|
||||
def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
|
||||
def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
|
||||
@ -542,10 +542,10 @@ def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">
|
||||
|
||||
// FP Stack manipulation instructions.
|
||||
let SchedRW = [WriteMove] in {
|
||||
def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">;
|
||||
def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op">;
|
||||
def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">;
|
||||
def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">;
|
||||
def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
|
||||
def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
|
||||
def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;
|
||||
def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
|
||||
}
|
||||
|
||||
// Floating point constant loads.
|
||||
@ -570,7 +570,7 @@ def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
|
||||
let SchedRW = [WriteFLD1] in
|
||||
def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
|
||||
|
||||
let SchedRW = [WriteFLDC], Defs = [FPSW] in {
|
||||
let SchedRW = [WriteFLDC] in {
|
||||
def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
|
||||
def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
|
||||
def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
|
||||
@ -579,7 +579,7 @@ def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
|
||||
} // SchedRW
|
||||
|
||||
// Floating point compares.
|
||||
let SchedRW = [WriteFCom] in {
|
||||
let SchedRW = [WriteFCom], Uses = [FPCW] in {
|
||||
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
|
||||
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
@ -591,37 +591,37 @@ def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
|
||||
let SchedRW = [WriteFCom] in {
|
||||
// CC = ST(0) cmp ST(i)
|
||||
let Defs = [EFLAGS, FPSW] in {
|
||||
let Predicates = [FPStackf32, HasCMov] in
|
||||
def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>;
|
||||
let Predicates = [FPStackf64, HasCMov] in
|
||||
def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>;
|
||||
let Predicates = [HasCMov] in
|
||||
let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
|
||||
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
|
||||
Requires<[FPStackf32, HasCMov]>;
|
||||
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>,
|
||||
Requires<[FPStackf64, HasCMov]>;
|
||||
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
|
||||
[(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>,
|
||||
Requires<[HasCMov]>;
|
||||
}
|
||||
|
||||
let Defs = [FPSW], Uses = [ST0] in {
|
||||
let Defs = [FPSW], Uses = [ST0, FPCW] in {
|
||||
def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
|
||||
(outs), (ins RST:$reg), "fucom\t$reg">;
|
||||
(outs), (ins RSTi:$reg), "fucom\t$reg">;
|
||||
def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
|
||||
(outs), (ins RST:$reg), "fucomp\t$reg">;
|
||||
(outs), (ins RSTi:$reg), "fucomp\t$reg">;
|
||||
def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
|
||||
(outs), (ins), "fucompp">;
|
||||
}
|
||||
|
||||
let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
|
||||
let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {
|
||||
def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
|
||||
(outs), (ins RST:$reg), "fucomi\t$reg">;
|
||||
(outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">;
|
||||
def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
|
||||
(outs), (ins RST:$reg), "fucompi\t$reg">;
|
||||
}
|
||||
(outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">;
|
||||
|
||||
let Defs = [EFLAGS, FPSW] in {
|
||||
def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">;
|
||||
def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">;
|
||||
def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg),
|
||||
"fcomi\t{$reg, %st|st, $reg}">;
|
||||
def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),
|
||||
"fcompi\t{$reg, %st|st, $reg}">;
|
||||
}
|
||||
} // SchedRW
|
||||
|
||||
@ -631,12 +631,12 @@ let Defs = [AX], Uses = [FPSW] in
|
||||
def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
|
||||
(outs), (ins), "fnstsw\t{%ax|ax}",
|
||||
[(set AX, (X86fp_stsw FPSW))]>;
|
||||
let Defs = [FPSW] in
|
||||
let Defs = [FPSW], Uses = [FPCW] in
|
||||
def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
|
||||
(outs), (ins i16mem:$dst), "fnstcw\t$dst",
|
||||
[(X86fp_cwd_get16 addr:$dst)]>;
|
||||
} // SchedRW
|
||||
let Defs = [FPSW], mayLoad = 1 in
|
||||
let Defs = [FPSW,FPCW], mayLoad = 1 in
|
||||
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
|
||||
(outs), (ins i16mem:$dst), "fldcw\t$dst", []>,
|
||||
Sched<[WriteLoad]>;
|
||||
@ -645,8 +645,8 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
|
||||
let SchedRW = [WriteMicrocoded] in {
|
||||
let Defs = [FPSW] in {
|
||||
def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
|
||||
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">;
|
||||
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">;
|
||||
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
|
||||
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
|
||||
|
||||
// Clear exceptions
|
||||
def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
|
||||
|
||||
@ -3231,39 +3231,39 @@ def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
|
||||
// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
|
||||
// gas.
|
||||
multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
|
||||
(Inst RST:$op), EmitAlias>;
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t$op"),
|
||||
(Inst RSTi:$op), EmitAlias>;
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"),
|
||||
(Inst ST0), EmitAlias>;
|
||||
}
|
||||
|
||||
defm : FpUnaryAlias<"fadd", ADD_FST0r>;
|
||||
defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fsub", SUB_FST0r>;
|
||||
defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
|
||||
defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
|
||||
defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
|
||||
defm : FpUnaryAlias<"fmul", MUL_FST0r>;
|
||||
defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
|
||||
defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
|
||||
defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
|
||||
defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
|
||||
defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
|
||||
defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>;
|
||||
defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>;
|
||||
defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
|
||||
defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
|
||||
defm : FpUnaryAlias<"fcompi", COM_FIPr>;
|
||||
defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
|
||||
defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>;
|
||||
defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>;
|
||||
|
||||
|
||||
// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
|
||||
// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they
|
||||
// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
|
||||
// solely because gas supports it.
|
||||
def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
|
||||
def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>;
|
||||
def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>;
|
||||
def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>;
|
||||
def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>;
|
||||
def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>;
|
||||
def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>;
|
||||
|
||||
def : InstAlias<"fnstsw" , (FNSTSW16r), 0>;
|
||||
|
||||
|
||||
@ -497,6 +497,9 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
const X86FrameLowering *TFI = getFrameLowering(MF);
|
||||
|
||||
// Set the floating point control register as reserved.
|
||||
Reserved.set(X86::FPCW);
|
||||
|
||||
// Set the stack-pointer register and its aliases as reserved.
|
||||
for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
|
||||
++I)
|
||||
|
||||
@ -278,7 +278,7 @@ def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>;
|
||||
// pseudo registers, but we still mark them as aliasing FP registers. That
|
||||
// way both kinds can be live without exceeding the stack depth. ST registers
|
||||
// are only live around inline assembly.
|
||||
def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
|
||||
def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>;
|
||||
def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>;
|
||||
@ -288,7 +288,10 @@ def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Floating-point status word
|
||||
def FPSW : X86Reg<"fpsw", 0>;
|
||||
def FPSW : X86Reg<"fpsr", 0>;
|
||||
|
||||
// Floating-point control word
|
||||
def FPCW : X86Reg<"fpcr", 0>;
|
||||
|
||||
// Status flags register.
|
||||
//
|
||||
@ -539,6 +542,9 @@ def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
|
||||
let isAllocatable = 0;
|
||||
}
|
||||
|
||||
// Helper to allow %st to print as %st(0) when its encoded in the instruction.
|
||||
def RSTi : RegisterOperand<RST, "printSTiRegOperand">;
|
||||
|
||||
// Generic vector registers: VR64 and VR128.
|
||||
// Ensure that float types are declared first - only float is legal on SSE1.
|
||||
def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
|
||||
|
||||
@ -842,6 +842,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
|
||||
TYPE("f32mem", TYPE_M)
|
||||
TYPE("ssmem", TYPE_M)
|
||||
TYPE("RST", TYPE_ST)
|
||||
TYPE("RSTi", TYPE_ST)
|
||||
TYPE("i128mem", TYPE_M)
|
||||
TYPE("i256mem", TYPE_M)
|
||||
TYPE("i512mem", TYPE_M)
|
||||
@ -964,6 +965,7 @@ OperandEncoding
|
||||
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("RST", ENCODING_FP)
|
||||
ENCODING("RSTi", ENCODING_FP)
|
||||
ENCODING("GR16", ENCODING_RM)
|
||||
ENCODING("GR32", ENCODING_RM)
|
||||
ENCODING("GR32orGR64", ENCODING_RM)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user