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Correct wrong definition of PM timer mask and adjust L1/PM timer

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value. While I'm here enable all clocks before initializing
controller. This change should fix lockup issue seen on AR8152
v1.1 PCIe Fast Ethernet controller.

PR:	kern/154076
MFC after:	3 days
This commit is contained in:
Pyun YongHyeon 2011-01-20 18:26:33 +00:00
parent 40a4c1f85d
commit c27d7a76fc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=217649
2 changed files with 16 additions and 4 deletions
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5
sys/dev/alc/if_alc.c
View File

@ -677,7 +677,7 @@ alc_aspm(struct alc_softc *sc, int media)
pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
pmcfg |= PM_CFG_MAC_ASPM_CHK;
pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB;
pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
@ -3148,6 +3148,9 @@ alc_init_locked(struct alc_softc *sc)
alc_init_cmb(sc);
alc_init_smb(sc);
/* Enable all clocks. */
CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
/* Reprogram the station address. */
bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
CSR_WRITE_4(sc, ALC_PAR0,

15
sys/dev/alc/if_alcreg.h
View File

@ -109,7 +109,7 @@
#define PM_CFG_PCIE_RECV 0x00008000
#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
#define PM_CFG_SA_DLY_ENB 0x20000000
#define PM_CFG_MAC_ASPM_CHK 0x40000000
@ -120,8 +120,9 @@
#define PM_CFG_LCKDET_TIMER_SHIFT 24
#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 12
#define PM_CFG_PM_REQ_TIMER_DEFAULT 1
#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
#define PM_CFG_LCKDET_TIMER_DEFAULT 12
#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
#define ALC_LTSSM_ID_CFG 0x12FC
#define LTSSM_ID_WRO_ENB 0x00001000
@ -724,6 +725,14 @@
#define ALC_TX_MIB_BASE 0x1760
#define ALC_CLK_GATING_CFG 0x1814
#define CLK_GATING_DMAW_ENB 0x0001
#define CLK_GATING_DMAR_ENB 0x0002
#define CLK_GATING_TXQ_ENB 0x0004
#define CLK_GATING_RXQ_ENB 0x0008
#define CLK_GATING_TXMAC_ENB 0x0010
#define CLK_GATING_RXMAC_ENB 0x0020
#define ALC_DEBUG_DATA0 0x1900
#define ALC_DEBUG_DATA1 0x1904