Backport svn r124339 from gcc 4.3 and add opteron-sse3, athlon64-sse3
and k8-sse3 cpu-types for -march=/-mtune= gcc options. These new cpu-types include the SSE3 instruction set that is supported by all newer AMD Athlon 64 and Opteron processors. All three cpu-types are supported by clang and all gcc versions starting with 4.3 SVN rev 124339 (at that time GPLv2 licensed). PR: gnu/154906 Discussed with: kib, kan, dim Obtained from: gcc 4.3 (r124339, GPLv2 licensed) MFC after: 2 weeks
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=218895
@ -1523,10 +1523,19 @@ override_options (void)
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| PTA_SSE | PTA_SSE2 },
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{"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
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{"k8-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
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| PTA_SSE3 },
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{"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
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{"opteron-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
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| PTA_SSE3 },
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{"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
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{"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
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| PTA_SSE3 },
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{"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
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{"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
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@ -129,7 +129,7 @@
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.\" ========================================================================
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.\"
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.IX Title "GCC 1"
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.TH GCC 1 "2007-07-19" "gcc-4.2.1" "GNU"
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.TH GCC 1 "2011-02-20" "gcc-4.2.1" "GNU"
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.SH "NAME"
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gcc \- GNU project C and C++ compiler
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.SH "SYNOPSIS"
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@ -8751,6 +8751,9 @@ instruction set support.
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.IX Item "k8, opteron, athlon64, athlon-fx"
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\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets
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\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
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.IP "\fIk8-sse3, opteron-sse3, athlon64-sse3\fR" 4
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.IX Item "k8-sse3, opteron-sse3, athlon64-sse3"
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Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support.
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.IP "\fIwinchip\-c6\fR" 4
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.IX Item "winchip-c6"
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\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
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@ -9382,6 +9382,8 @@ instruction set support.
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@item k8, opteron, athlon64, athlon-fx
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AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
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MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
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@item k8-sse3, opteron-sse3, athlon64-sse3
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Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
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@item winchip-c6
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IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
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set support.
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