Update dis_tables.c to the latest Illumos version.
This includes decodes of recent Intel instructions, in particular VT-x and related instructions. This allows the FBT provider to locate the exit points of routines that include these new instructions. Illumos issues: 3414 Need a new word of AT_SUN_HWCAP bits 3415 Add isainfo support for f16c and rdrand 3416 Need disassembler support for rdrand and f16c 3413 isainfo -v overflows 80 columns 3417 mdb disassembler confuses rdtscp for invlpg 1518 dis should support AMD SVM/AMD-V/Pacifica instructions 1096 i386 disassembler should understand complex nops 1362 add kvmstat for monitoring of KVM statistics 1363 add vmregs[] variable to DTrace 1364 need disassembler support for VMX instructions 1365 mdb needs 16-bit disassembler support This corresponds to Illumos-gate (github) version eb23829ff08a873c612ac45d191d559394b4b408 Reviewed by: markj MFC after: 1 week
This commit is contained in:
parent
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commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=266103
@ -21,6 +21,7 @@
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*/
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/*
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* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, Joyent, Inc. All rights reserved.
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*/
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/*
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@ -104,16 +105,18 @@ enum {
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Mv,
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Mw,
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M, /* register or memory */
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MG9, /* register or memory in group 9 (prefix optional) */
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Mb, /* register or memory, always byte sized */
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MO, /* memory only (no registers) */
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PREF,
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SWAPGS,
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SWAPGS_RDTSCP,
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MONITOR_MWAIT,
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R,
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RA,
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SEG,
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MR,
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RM,
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RM_66r, /* RM, but with a required 0x66 prefix */
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IA,
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MA,
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SD,
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@ -228,7 +231,10 @@ enum {
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VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
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VEX_RM, /* VEX mod_reg -> mod_rm */
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VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
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VEX_RMX /* VEX VEX.vvvv, mod_rm -> mod_reg */
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VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
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VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
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VMxo, /* VMx instruction with optional prefix */
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SVM /* AMD SVM instructions */
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};
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/*
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@ -496,8 +502,8 @@ const instable_t dis_op0F00[8] = {
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*/
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const instable_t dis_op0F01[8] = {
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/* [0] */ TNSZ("sgdt",MO,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",MO,6),
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/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS),
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/* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
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/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
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};
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/*
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@ -528,15 +534,44 @@ const instable_t dis_op0FBA[8] = {
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};
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/*
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* Decode table for 0x0FC7 opcode
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* Decode table for 0x0FC7 opcode (group 9)
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*/
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const instable_t dis_op0FC7[8] = {
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/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
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/* [4] */ INVALID, INVALID, INVALID, INVALID,
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/* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
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};
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/*
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* Decode table for 0x0FC7 opcode (group 9) mode 3
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*/
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const instable_t dis_op0FC7m3[8] = {
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/* [0] */ INVALID, INVALID, INVALID, INVALID,
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/* [4] */ INVALID, INVALID, TNS("rdrand",MG9), INVALID,
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};
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/*
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* Decode table for 0x0FC7 opcode with 0x66 prefix
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*/
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const instable_t dis_op660FC7[8] = {
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/* [0] */ INVALID, INVALID, INVALID, INVALID,
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/* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
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};
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/*
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* Decode table for 0x0FC7 opcode with 0xF3 prefix
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*/
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const instable_t dis_opF30FC7[8] = {
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/* [0] */ INVALID, INVALID, INVALID, INVALID,
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/* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
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};
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/*
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* Decode table for 0x0FC8 opcode -- 486 bswap instruction
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@ -1147,7 +1182,7 @@ const instable_t dis_op0F38[256] = {
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/* [78] */ INVALID, INVALID, INVALID, INVALID,
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/* [7C] */ INVALID, INVALID, INVALID, INVALID,
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/* [80] */ INVALID, INVALID, INVALID, INVALID,
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/* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID,
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/* [84] */ INVALID, INVALID, INVALID, INVALID,
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/* [88] */ INVALID, INVALID, INVALID, INVALID,
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/* [8C] */ INVALID, INVALID, INVALID, INVALID,
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@ -1193,7 +1228,7 @@ const instable_t dis_opAVX660F38[256] = {
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/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
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/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
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/* [10] */ INVALID, INVALID, INVALID, INVALID,
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/* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
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/* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16),
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/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
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/* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
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@ -1359,7 +1394,7 @@ const instable_t dis_opAVX660F3A[256] = {
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/* [10] */ INVALID, INVALID, INVALID, INVALID,
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/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
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/* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
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/* [1C] */ INVALID, INVALID, INVALID, INVALID,
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/* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
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/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
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/* [24] */ INVALID, INVALID, INVALID, INVALID,
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@ -1446,7 +1481,7 @@ const instable_t dis_op0F[16][16] = {
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/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
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/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
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/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
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/* [1C] */ INVALID, INVALID, INVALID, TS("nopw", Mw),
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/* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
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}, {
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/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
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/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
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@ -1475,7 +1510,7 @@ const instable_t dis_op0F[16][16] = {
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}, {
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/* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
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/* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
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/* [78] */ TNS("INVALID",XMMO), TNS("INVALID",XMMO), INVALID, INVALID,
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/* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
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/* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
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}, {
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/* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
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@ -1859,14 +1894,14 @@ const instable_t dis_distable[16][16] = {
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/* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
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}, {
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/* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
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/* [2,4] */ TNS("andb",IA), TS("and",IA), TNS("%es:",OVERRIDE), TNSx("daa",NORM),
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/* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM),
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/* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
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/* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
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}, {
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/* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
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/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNS("%ss:",OVERRIDE), TNSx("aaa",NORM),
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/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM),
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/* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
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/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNS("%ds:",OVERRIDE), TNSx("aas",NORM),
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/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM),
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}, {
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/* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
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/* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
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@ -2905,6 +2940,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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goto error;
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#endif
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switch (dp->it_adrmode) {
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case RM_66r:
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case XMM_66r:
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case XMMM_66r:
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if (opnd_size_prefix == 0) {
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@ -3054,6 +3090,59 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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}
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break;
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case MG9:
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/*
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* More horribleness: the group 9 (0xF0 0xC7) instructions are
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* allowed an optional prefix of 0x66 or 0xF3. This is similar
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* to the SIMD business described above, but with a different
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* addressing mode (and an indirect table), so we deal with it
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* separately (if similarly).
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*
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* Intel further complicated this with the release of Ivy Bridge
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* where they overloaded these instructions based on the ModR/M
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* bytes. The VMX instructions have a mode of 0 since they are
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* memory instructions but rdrand instructions have a mode of
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* 0b11 (REG_ONLY) because they only operate on registers. While
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* there are different prefix formats, for now it is sufficient
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* to use a single different table.
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*/
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/*
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* Calculate our offset in dis_op0FC7 (the group 9 table)
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*/
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if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
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goto error;
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off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
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sizeof (instable_t);
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/*
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* If we have a mode of 0b11 then we have to rewrite this.
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*/
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dtrace_get_modrm(x, &mode, ®, &r_m);
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if (mode == REG_ONLY) {
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dp = (instable_t *)&dis_op0FC7m3[off];
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break;
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}
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/*
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* Rewrite if this instruction used one of the magic prefixes.
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*/
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if (rep_prefix) {
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if (rep_prefix == 0xf3)
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dp = (instable_t *)&dis_opF30FC7[off];
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else
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goto error;
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rep_prefix = 0;
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} else if (opnd_size_prefix) {
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dp = (instable_t *)&dis_op660FC7[off];
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opnd_size_prefix = 0;
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if (opnd_size == SIZE16)
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opnd_size = SIZE32;
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}
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break;
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case MMOSH:
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/*
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* As with the "normal" SIMD instructions, the MMX
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@ -3434,14 +3523,21 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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dtrace_get_operand(x, mode, r_m, wbit, 0);
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break;
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case SWAPGS:
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case SWAPGS_RDTSCP:
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if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
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#ifdef DIS_TEXT
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(void) strncpy(x->d86_mnem, "swapgs", OPLEN);
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#endif
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NOMEM;
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break;
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} else if (mode == 3 && r_m == 1) {
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#ifdef DIS_TEXT
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(void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
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#endif
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NOMEM;
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break;
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}
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/*FALLTHROUGH*/
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/* prefetch instruction - memory operand, but no memory acess */
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@ -3451,6 +3547,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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/* single memory or register operand */
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case M:
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case MG9:
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wbit = LONG_OPND;
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goto just_mem;
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@ -3459,6 +3556,76 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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wbit = BYTE_OPND;
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goto just_mem;
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case VMx:
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if (mode == 3) {
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#ifdef DIS_TEXT
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char *vminstr;
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switch (r_m) {
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case 1:
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vminstr = "vmcall";
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break;
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case 2:
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vminstr = "vmlaunch";
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break;
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case 3:
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vminstr = "vmresume";
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break;
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case 4:
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vminstr = "vmxoff";
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break;
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default:
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goto error;
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}
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(void) strncpy(x->d86_mnem, vminstr, OPLEN);
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#else
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if (r_m < 1 || r_m > 4)
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goto error;
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#endif
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NOMEM;
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break;
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}
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/*FALLTHROUGH*/
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case SVM:
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if (mode == 3) {
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#ifdef DIS_TEXT
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char *vinstr;
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switch (r_m) {
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case 0:
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vinstr = "vmrun";
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break;
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case 1:
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vinstr = "vmmcall";
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break;
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case 2:
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vinstr = "vmload";
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break;
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case 3:
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vinstr = "vmsave";
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break;
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case 4:
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vinstr = "stgi";
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break;
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case 5:
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vinstr = "clgi";
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break;
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case 6:
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vinstr = "skinit";
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break;
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case 7:
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vinstr = "invlpga";
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break;
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}
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(void) strncpy(x->d86_mnem, vinstr, OPLEN);
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#endif
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NOMEM;
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break;
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}
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/*FALLTHROUGH*/
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case MONITOR_MWAIT:
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if (mode == 3) {
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if (r_m == 0) {
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@ -3597,6 +3764,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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break;
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case RM:
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case RM_66r:
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wbit = LONG_OPND;
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STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
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break;
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@ -4300,7 +4468,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
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dtrace_get_operand(x, mode, r_m, wbit, 0);
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} else if ((dp == &dis_opAVXF30F[0xE6]) ||
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(dp == &dis_opAVX0F[0x5][0xA])) {
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(dp == &dis_opAVX0F[0x5][0xA]) ||
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(dp == &dis_opAVX660F38[0x13])) {
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/* vcvtdq2pd <xmm>, <ymm> */
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/* or vcvtps2pd <xmm>, <ymm> */
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dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
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@ -4385,7 +4554,9 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
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case VEX_RX:
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/* ModR/M.rm := op(ModR/M.reg) */
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if (dp == &dis_opAVX660F3A[0x19]) { /* vextractf128 */
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/* vextractf128 || vcvtps2ph */
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if (dp == &dis_opAVX660F3A[0x19] ||
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dp == &dis_opAVX660F3A[0x1d]) {
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x->d86_numopnds = 3;
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dtrace_get_modrm(x, &mode, ®, &r_m);
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