aw_nmi: add support for a31/a83t's r_intc
We currently support the a83t's r_intc in a somewhat hack-ish way; our .dts describes it as nmi_intc, and uses a subset of the actual register space to make it line up with a20/a31 nmi offsets. This breaks with the recent 4.14 update describing r_intc using the full register space, so update aw_nmi to use the correct register offsets with the right compat data in a way that doesn't break our current dts with nmi_intc or upstream with r_intc described. Reviewed by: manu Approved by: emaste (mentor) Differential Revision: https://reviews.freebsd.org/D13122
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6be8e27be0
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c4717ac049
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=325991
@ -57,6 +57,10 @@ __FBSDID("$FreeBSD$");
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#define A31_NMI_IRQ_ENABLE_REG 0x34
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#define NMI_IRQ_ENABLE (1U << 0)
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#define R_NMI_IRQ_CTRL_REG 0x0c
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#define R_NMI_IRQ_PENDING_REG 0x10
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#define R_NMI_IRQ_ENABLE_REG 0x40
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#define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg)
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#define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val)
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@ -73,21 +77,43 @@ struct aw_nmi_intr {
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enum intr_trigger tri;
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};
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struct aw_nmi_reg_cfg {
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uint8_t ctrl_reg;
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uint8_t pending_reg;
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uint8_t enable_reg;
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};
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struct aw_nmi_softc {
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device_t dev;
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struct resource * res[2];
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void * intrcookie;
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struct aw_nmi_intr intr;
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uint8_t enable_reg;
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struct aw_nmi_reg_cfg * cfg;
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};
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#define A20_NMI 1
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#define A31_NMI 2
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static struct aw_nmi_reg_cfg a20_nmi_cfg = {
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.ctrl_reg = NMI_IRQ_CTRL_REG,
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.pending_reg = NMI_IRQ_PENDING_REG,
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.enable_reg = A20_NMI_IRQ_ENABLE_REG,
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};
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static struct aw_nmi_reg_cfg a31_nmi_cfg = {
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.ctrl_reg = NMI_IRQ_CTRL_REG,
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.pending_reg = NMI_IRQ_PENDING_REG,
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.enable_reg = A31_NMI_IRQ_ENABLE_REG,
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};
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static struct aw_nmi_reg_cfg a83t_r_nmi_cfg = {
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.ctrl_reg = R_NMI_IRQ_CTRL_REG,
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.pending_reg = R_NMI_IRQ_PENDING_REG,
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.enable_reg = R_NMI_IRQ_ENABLE_REG,
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};
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun7i-a20-sc-nmi", A20_NMI},
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{"allwinner,sun6i-a31-sc-nmi", A31_NMI},
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{"allwinner,sun7i-a20-sc-nmi", (uintptr_t)&a20_nmi_cfg},
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{"allwinner,sun6i-a31-sc-nmi", (uintptr_t)&a31_nmi_cfg},
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{"allwinner,sun6i-a31-r-intc", (uintptr_t)&a83t_r_nmi_cfg},
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{"allwinner,sun8i-a83t-r-intc", (uintptr_t)&a83t_r_nmi_cfg},
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{NULL, 0},
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};
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@ -98,13 +124,13 @@ aw_nmi_intr(void *arg)
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sc = arg;
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if (SC_NMI_READ(sc, NMI_IRQ_PENDING_REG) == 0) {
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if (SC_NMI_READ(sc, sc->cfg->pending_reg) == 0) {
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device_printf(sc->dev, "Spurious interrupt\n");
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return (FILTER_HANDLED);
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}
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if (intr_isrc_dispatch(&sc->intr.isrc, curthread->td_intr_frame) != 0) {
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SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE);
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device_printf(sc->dev, "Stray interrupt, NMI disabled\n");
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}
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@ -118,7 +144,7 @@ aw_nmi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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sc = device_get_softc(dev);
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SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, sc->cfg->enable_reg, NMI_IRQ_ENABLE);
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}
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static void
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@ -128,7 +154,7 @@ aw_nmi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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sc = device_get_softc(dev);
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SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE);
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}
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static int
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@ -254,7 +280,7 @@ aw_nmi_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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icfg = NMI_IRQ_LOW_EDGE;
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}
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SC_NMI_WRITE(sc, NMI_IRQ_CTRL_REG, icfg);
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SC_NMI_WRITE(sc, sc->cfg->ctrl_reg, icfg);
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return (0);
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}
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@ -271,7 +297,7 @@ aw_nmi_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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sc->intr.pol = INTR_POLARITY_CONFORM;
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sc->intr.tri = INTR_TRIGGER_CONFORM;
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SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE);
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}
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return (0);
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@ -284,7 +310,7 @@ aw_nmi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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sc = device_get_softc(dev);
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aw_nmi_disable_intr(dev, isrc);
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SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK);
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SC_NMI_WRITE(sc, sc->cfg->pending_reg, NMI_IRQ_ACK);
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}
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static void
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@ -303,7 +329,7 @@ aw_nmi_post_filter(device_t dev, struct intr_irqsrc *isrc)
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sc = device_get_softc(dev);
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arm_irq_memory_barrier(0);
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SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK);
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SC_NMI_WRITE(sc, sc->cfg->pending_reg, NMI_IRQ_ACK);
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}
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static int
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@ -327,6 +353,8 @@ aw_nmi_attach(device_t dev)
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->cfg = (struct aw_nmi_reg_cfg *)
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ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (bus_alloc_resources(dev, aw_nmi_res_spec, sc->res) != 0) {
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device_printf(dev, "can't allocate device resources\n");
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@ -339,18 +367,9 @@ aw_nmi_attach(device_t dev)
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return (ENXIO);
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}
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switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
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case A20_NMI:
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sc->enable_reg = A20_NMI_IRQ_ENABLE_REG;
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break;
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case A31_NMI:
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sc->enable_reg = A31_NMI_IRQ_ENABLE_REG;
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break;
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}
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/* Disable and clear interrupts */
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SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK);
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SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE);
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SC_NMI_WRITE(sc, sc->cfg->pending_reg, NMI_IRQ_ACK);
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xref = OF_xref_from_node(ofw_bus_get_node(dev));
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/* Register our isrc */
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