Import device-tree files from Linux 6.4
This commit is contained in:
Emmanuel Vadot
parent
4a8223f297
commit
c47d0ea183
@ -19,7 +19,7 @@ rules:
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colons: {max-spaces-before: 0, max-spaces-after: 1}
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commas: {min-spaces-after: 1, max-spaces-after: 1}
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comments:
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require-starting-space: false
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require-starting-space: true
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min-spaces-from-content: 1
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comments-indentation: disable
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document-start:
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@ -153,17 +153,27 @@ properties:
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- description: Boards with the Amlogic Meson G12B A311D SoC
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items:
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- enum:
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- bananapi,bpi-m2s
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- khadas,vim3
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- radxa,zero2
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- const: amlogic,a311d
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- const: amlogic,g12b
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- description: Boards using the BPI-CM4 module with Amlogic Meson G12B A311D SoC
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items:
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- enum:
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- bananapi,bpi-cm4io
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- const: bananapi,bpi-cm4
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- const: amlogic,a311d
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- const: amlogic,g12b
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- description: Boards with the Amlogic Meson G12B S922X SoC
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items:
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- enum:
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- azw,gsking-x
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- azw,gtking
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- azw,gtking-pro
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- bananapi,bpi-m2s
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- hardkernel,odroid-go-ultra
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- hardkernel,odroid-n2
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- hardkernel,odroid-n2l
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@ -2,8 +2,8 @@
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson Firmware registers Interface
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface
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@ -19,6 +19,12 @@ description: |
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- MacBook Air (M1, 2020)
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- iMac (24-inch, M1, 2021)
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Devices based on the "M2" SoC:
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- MacBook Air (M2, 2022)
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- MacBook Pro (13-inch, M2, 2022)
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- Mac mini (M2, 2023)
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And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
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- MacBook Pro (14-inch, M1 Pro, 2021)
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@ -70,6 +76,15 @@ properties:
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- const: apple,t8103
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- const: apple,arm-platform
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- description: Apple M2 SoC based platforms
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items:
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- enum:
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- apple,j413 # MacBook Air (M2, 2022)
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- apple,j473 # Mac mini (M2, 2023)
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- apple,j493 # MacBook Pro (13-inch, M2, 2022)
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- const: apple,t8112
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- const: apple,arm-platform
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- description: Apple M1 Pro SoC based platforms
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items:
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- enum:
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@ -23,6 +23,7 @@ properties:
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items:
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- enum:
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- apple,t8103-pmgr
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- apple,t8112-pmgr
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- apple,t6000-pmgr
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- const: apple,pmgr
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- const: syscon
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@ -144,6 +144,7 @@ patternProperties:
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it is stricter and always has two compatibles.
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type: object
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$ref: '/schemas/simple-bus.yaml'
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unevaluatedProperties: false
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properties:
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compatible:
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@ -30,6 +30,7 @@ properties:
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clocks:
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type: object
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additionalProperties: false
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properties:
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compatible:
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@ -47,6 +48,7 @@ properties:
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reset:
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type: object
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additionalProperties: false
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properties:
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compatible:
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@ -63,6 +65,7 @@ properties:
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pwm:
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type: object
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additionalProperties: false
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properties:
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compatible:
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@ -76,8 +79,6 @@ properties:
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- compatible
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- "#pwm-cells"
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additionalProperties: false
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required:
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- compatible
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- mboxes
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@ -85,6 +85,8 @@ properties:
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compatible:
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enum:
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- apple,avalanche
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- apple,blizzard
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- apple,icestorm
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- apple,firestorm
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- arm,arm710t
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@ -139,6 +141,7 @@ properties:
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- arm,cortex-a77
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- arm,cortex-a78
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- arm,cortex-a78ae
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- arm,cortex-a78c
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- arm,cortex-a510
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- arm,cortex-a710
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- arm,cortex-a715
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@ -151,6 +154,7 @@ properties:
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- arm,cortex-r5
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- arm,cortex-r7
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- arm,cortex-x1
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- arm,cortex-x1c
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- arm,cortex-x2
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- arm,cortex-x3
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- arm,neoverse-e1
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@ -28,7 +28,8 @@ properties:
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maxItems: 1
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description: |
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This interrupt which is used to signal an event by the secure world
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software is expected to be edge-triggered.
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software is expected to be either a per-cpu interrupt or an
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edge-triggered peripheral interrupt.
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method:
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enum: [smc, hvc]
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@ -300,6 +300,7 @@ properties:
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- variscite,dt6customboard
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- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
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- ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board
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- ysoft,imx6q-yapp4-pegasus # i.MX6 Quad Y Soft IOTA Pegasus board
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- zealz,imx6q-gk802 # Zealz GK802
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- zii,imx6q-zii-rdu2 # ZII RDU2 Board
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- const: fsl,imx6q
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@ -410,6 +411,7 @@ properties:
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- prt,prtwd3 # Protonic WD3 board
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- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
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- ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board
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- ysoft,imx6qp-yapp4-pegasus-plus # i.MX6 Quad Plus Y Soft IOTA Pegasus+ board
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- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
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- const: fsl,imx6qp
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@ -474,9 +476,11 @@ properties:
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- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
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- vdl,lanmcu # Van der Laan LANMCU board
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- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
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- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
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- ysoft,imx6dl-yapp4-draco # i.MX6 Solo Y Soft IOTA Draco board
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- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
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- ysoft,imx6dl-yapp4-lynx # i.MX6 DualLite Y Soft IOTA Lynx board
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- ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board
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- ysoft,imx6dl-yapp4-phoenix # i.MX6 DualLite Y Soft IOTA Phoenix board
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- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
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- const: fsl,imx6dl
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@ -581,6 +585,7 @@ properties:
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- kobo,aura2
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- kobo,tolino-shine2hd
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- kobo,tolino-shine3
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- kobo,tolino-vision
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- kobo,tolino-vision5
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- revotics,imx6sl-warp # Revotics WaRP Board
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- const: fsl,imx6sl
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@ -702,6 +707,15 @@ properties:
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- const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
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- const: fsl,imx6ull
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- description: i.MX6ULL chargebyte Tarragon Boards
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items:
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- enum:
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- chargebyte,imx6ull-tarragon-master
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- chargebyte,imx6ull-tarragon-micro
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- chargebyte,imx6ull-tarragon-slave
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- chargebyte,imx6ull-tarragon-slavext
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- const: fsl,imx6ull
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- description: i.MX6ULL DHCOM SoM based Boards
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items:
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- enum:
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@ -1002,6 +1016,7 @@ properties:
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items:
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- enum:
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- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
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- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
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- fsl,imx8mp-evk # i.MX8MP EVK Board
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- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
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- polyhex,imx8mp-debix # Polyhex Debix boards
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@ -1020,7 +1035,9 @@ properties:
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- description: i.MX8MP DHCOM based Boards
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items:
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- const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
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- enum:
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- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
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- dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board
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- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
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- const: fsl,imx8mp
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@ -1119,6 +1136,25 @@ properties:
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items:
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- enum:
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- fsl,imx8qm-mek # i.MX8QM MEK Board
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- toradex,apalis-imx8 # Apalis iMX8 Modules
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- toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
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- const: fsl,imx8qm
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- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
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items:
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- enum:
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- toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board
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- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
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- const: toradex,apalis-imx8
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- const: fsl,imx8qm
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- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
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items:
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- enum:
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- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board
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- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
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- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
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- const: toradex,apalis-imx8-v1.1
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- const: fsl,imx8qm
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- description: i.MX8QXP based Boards
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@ -1135,10 +1171,13 @@ properties:
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- fsl,imx8dxl-evk # i.MX8DXL EVK Board
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- const: fsl,imx8dxl
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- description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
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- description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules
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items:
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- enum:
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- toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board
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- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
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- toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board
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- toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2
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- const: toradex,colibri-imx8x
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- const: fsl,imx8qxp
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Infrastructure System Configuration Controller
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek mmsys controller
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIE Mirror Controller for MT7622
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
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@ -20,6 +20,7 @@ properties:
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items:
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- enum:
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- mediatek,mt7622-wed
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- mediatek,mt7981-wed
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- mediatek,mt7986-wed
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- const: syscon
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIE WED Controller for MT7986
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8186
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek System Clock Controller for MT8186
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8192
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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|
||||
title: MediaTek System Clock Controller for MT8192
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8195
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8195
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Peripheral Configuration Controller
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 CPU Complex
|
||||
|
||||
@ -25,7 +25,7 @@ properties:
|
||||
- nvidia,tegra194-ccplex
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Specifies the bpmp node that needs to be queried to get
|
||||
operating point data for all CPUs.
|
||||
|
||||
@ -20,6 +20,8 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- apm,potenza-pmu
|
||||
- apple,avalanche-pmu
|
||||
- apple,blizzard-pmu
|
||||
- apple,firestorm-pmu
|
||||
- apple,icestorm-pmu
|
||||
- arm,armv8-pmuv3 # Only for s/w models
|
||||
|
||||
@ -30,8 +30,10 @@ description: |
|
||||
apq8084
|
||||
apq8096
|
||||
ipq4018
|
||||
ipq5332
|
||||
ipq6018
|
||||
ipq8074
|
||||
ipq9574
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8916
|
||||
@ -45,7 +47,10 @@ description: |
|
||||
msm8996
|
||||
msm8998
|
||||
qcs404
|
||||
qcm2290
|
||||
qdu1000
|
||||
qrb2210
|
||||
qrb4210
|
||||
qru1000
|
||||
sa8155p
|
||||
sa8540p
|
||||
@ -80,6 +85,9 @@ description: |
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
adp
|
||||
ap-al02-c7
|
||||
ap-mi01.2
|
||||
ap-mi01.6
|
||||
cdp
|
||||
cp01-c1
|
||||
dragonboard
|
||||
@ -90,6 +98,7 @@ description: |
|
||||
liquid
|
||||
mtp
|
||||
qrd
|
||||
rb2
|
||||
ride
|
||||
sbc
|
||||
x100
|
||||
@ -226,6 +235,7 @@ properties:
|
||||
- thwc,uf896
|
||||
- thwc,ufi001c
|
||||
- wingtech,wt88047
|
||||
- yiming,uz801-v3
|
||||
- const: qcom,msm8916
|
||||
|
||||
- items:
|
||||
@ -320,6 +330,12 @@ properties:
|
||||
- qcom,ipq4019-dk04.1-c1
|
||||
- const: qcom,ipq4019
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5332-ap-mi01.2
|
||||
- qcom,ipq5332-ap-mi01.6
|
||||
- const: qcom,ipq5332
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- mikrotik,rb3011
|
||||
@ -333,12 +349,24 @@ properties:
|
||||
- qcom,ipq8074-hk10-c2
|
||||
- const: qcom,ipq8074
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq9574-ap-al02-c7
|
||||
- const: qcom,ipq9574
|
||||
|
||||
- description: Sierra Wireless MangOH Green with WP8548 Module
|
||||
items:
|
||||
- const: swir,mangoh-green-wp8548
|
||||
- const: swir,wp8548
|
||||
- const: qcom,mdm9615
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Robotics RB1
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qrb2210-rb1
|
||||
- const: qcom,qrb2210
|
||||
- const: qcom,qcm2290
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
|
||||
items:
|
||||
- enum:
|
||||
@ -848,6 +876,12 @@ properties:
|
||||
- oneplus,billie2
|
||||
- const: qcom,sm4250
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qrb4210-rb2
|
||||
- const: qcom,qrb4210
|
||||
- const: qcom,sm4250
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,j606f
|
||||
@ -857,6 +891,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- sony,pdx201
|
||||
- xiaomi,laurel-sprout
|
||||
- const: qcom,sm6125
|
||||
|
||||
- items:
|
||||
@ -913,6 +948,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8550-mtp
|
||||
- qcom,sm8550-qrd
|
||||
- const: qcom,sm8550
|
||||
|
||||
# Board compatibles go above
|
||||
|
||||
@ -185,9 +185,11 @@ properties:
|
||||
- const: firefly,rk3566-roc-pc
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: FriendlyElec NanoPi R2S
|
||||
- description: FriendlyElec NanoPi R2 series boards
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r2s
|
||||
- enum:
|
||||
- friendlyarm,nanopi-r2c
|
||||
- friendlyarm,nanopi-r2s
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
@ -201,6 +203,13 @@ properties:
|
||||
- friendlyarm,nanopi-r4s-enterprise
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: FriendlyElec NanoPi R5 series boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,nanopi-r5c
|
||||
- friendlyarm,nanopi-r5s
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: GeekBuying GeekBox
|
||||
items:
|
||||
- const: geekbuying,geekbox
|
||||
@ -533,6 +542,11 @@ properties:
|
||||
- khadas,edge-v
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Khadas Edge2 series boards
|
||||
items:
|
||||
- const: khadas,edge2
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Kobol Helios64
|
||||
items:
|
||||
- const: kobol,helios64
|
||||
@ -817,9 +831,11 @@ properties:
|
||||
- const: tronsmart,orion-r68-meta
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Xunlong Orange Pi R1 Plus
|
||||
- description: Xunlong Orange Pi R1 Plus / LTS
|
||||
items:
|
||||
- const: xunlong,orangepi-r1-plus
|
||||
- enum:
|
||||
- xunlong,orangepi-r1-plus
|
||||
- xunlong,orangepi-r1-plus-lts
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: Zkmagic A95X Z2
|
||||
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- st,stm32-syscfg
|
||||
- st,stm32-power-config
|
||||
- st,stm32-tamp
|
||||
- st,stm32f4-gcan
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: st,stm32-tamp
|
||||
@ -42,6 +43,7 @@ if:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32mp157-syscfg
|
||||
- st,stm32f4-gcan
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
|
||||
@ -366,6 +366,12 @@ properties:
|
||||
- const: lamobo,lamobo-r1
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Lctech Pi F1C200s
|
||||
items:
|
||||
- const: lctech,pi-f1c200s
|
||||
- const: allwinner,suniv-f1c200s
|
||||
- const: allwinner,suniv-f1c100s
|
||||
|
||||
- description: Libre Computer Board ALL-H3-CC H2+
|
||||
items:
|
||||
- const: libretech,all-h3-cc-h2-plus
|
||||
@ -807,6 +813,13 @@ properties:
|
||||
- const: sinlinx,sina33
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: SourceParts PopStick v1.1
|
||||
items:
|
||||
- const: sourceparts,popstick-v1.1
|
||||
- const: sourceparts,popstick
|
||||
- const: allwinner,suniv-f1c200s
|
||||
- const: allwinner,suniv-f1c100s
|
||||
|
||||
- description: SL631 Action Camera with IMX179
|
||||
items:
|
||||
- const: allwinner,sl631-imx179
|
||||
@ -843,6 +856,11 @@ properties:
|
||||
- const: wexler,tab7200
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: MangoPi MQ-R board
|
||||
items:
|
||||
- const: widora,mangopi-mq-r-t113
|
||||
- const: allwinner,sun8i-t113s
|
||||
|
||||
- description: WITS A31 Colombus Evaluation Board
|
||||
items:
|
||||
- const: wits,colombus
|
||||
|
||||
@ -167,5 +167,14 @@ properties:
|
||||
- const: nvidia,p3737-0000+p3701-0000
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson Orin NX
|
||||
items:
|
||||
- const: nvidia,p3767-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson Orin NX Engineering Reference Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3768-0000+p3767-0000
|
||||
- const: nvidia,p3767-0000
|
||||
- const: nvidia,tegra234
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra CPU COMPLEX CLUSTER area
|
||||
|
||||
@ -29,7 +29,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Specifies the BPMP node that needs to be queried to get
|
||||
operating point data for all CPUs.
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 AXI2APB bridge
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 CBB 1.0
|
||||
|
||||
@ -64,13 +64,13 @@ properties:
|
||||
- description: secure interrupt
|
||||
|
||||
nvidia,axi2apb:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Specifies the node having all axi2apb bridges which need to be checked
|
||||
for any error logged in their status register.
|
||||
|
||||
nvidia,apbmisc:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Specifies the apbmisc node which need to be used for reading the ERD
|
||||
register.
|
||||
|
||||
@ -234,6 +234,7 @@ properties:
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
clocks:
|
||||
@ -252,6 +253,9 @@ properties:
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra CBB 2.0
|
||||
|
||||
|
||||
@ -28,7 +28,9 @@ properties:
|
||||
- description: K3 AM625 SoC
|
||||
items:
|
||||
- enum:
|
||||
- beagle,am625-beagleplay
|
||||
- ti,am625-sk
|
||||
- ti,am62-lp-sk
|
||||
- const: ti,am625
|
||||
|
||||
- description: K3 AM642 SoC
|
||||
|
||||
@ -8,7 +8,7 @@ title: Common Properties for Serial ATA AHCI controllers
|
||||
|
||||
maintainers:
|
||||
- Hans de Goede <hdegoede@redhat.com>
|
||||
- Damien Le Moal <damien.lemoal@opensource.wdc.com>
|
||||
- Damien Le Moal <dlemoal@kernel.org>
|
||||
|
||||
description:
|
||||
This document defines device tree properties for a common AHCI SATA
|
||||
@ -59,7 +59,7 @@ properties:
|
||||
const: sata-phy
|
||||
|
||||
hba-cap:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Bitfield of the HBA generic platform capabilities like Staggered
|
||||
Spin-up or Mechanical Presence Switch support. It can be used to
|
||||
@ -67,7 +67,7 @@ properties:
|
||||
in case if the system firmware hasn't done it.
|
||||
|
||||
ports-implemented:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Mask that indicates which ports the HBA supports. Useful if PI is not
|
||||
programmed by the BIOS, which is true for some embedded SoC's.
|
||||
@ -110,7 +110,7 @@ $defs:
|
||||
description: Power regulator for SATA port target device
|
||||
|
||||
hba-port-cap:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Bitfield of the HBA port-specific platform capabilities like Hot
|
||||
plugging, eSATA, FIS-based Switching, etc (see AHCI specification
|
||||
|
||||
@ -30,12 +30,12 @@ select:
|
||||
- marvell,armada-3700-ahci
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- socionext,uniphier-pro4-ahci
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: "ahci-common.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
@ -45,6 +45,9 @@ properties:
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- socionext,uniphier-pro4-ahci
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
- const: generic-ahci
|
||||
- enum:
|
||||
- cavium,octeon-7130-ahci
|
||||
@ -74,7 +77,8 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
patternProperties:
|
||||
"^sata-port@[0-9a-f]+$":
|
||||
@ -91,6 +95,43 @@ required:
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: socionext,uniphier-pro4-ahci
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: reset line for the parent
|
||||
- description: reset line for the glue logic
|
||||
- description: reset line for the controller
|
||||
required:
|
||||
- resets
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: reset for the glue logic
|
||||
- description: reset for the controller
|
||||
required:
|
||||
- resets
|
||||
else:
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -32,7 +32,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
maxItems: 4
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car Serial-ATA Interface
|
||||
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Robin van der Gracht <robin@protonic.nl>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/input/matrix-keymap.yaml#"
|
||||
- $ref: /schemas/input/matrix-keymap.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -72,7 +72,7 @@ examples:
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
i2c1 {
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@ -46,6 +46,7 @@ patternProperties:
|
||||
# All other properties should be child nodes with unit-address and 'reg'
|
||||
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -45,6 +45,7 @@ properties:
|
||||
patternProperties:
|
||||
"^.*@[0-9a-fA-F]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
54
Bindings/bus/microsoft,vmbus.yaml
Normal file
54
Bindings/bus/microsoft,vmbus.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/microsoft,vmbus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microsoft Hyper-V VMBus
|
||||
|
||||
maintainers:
|
||||
- Saurabh Sengar <ssengar@linux.microsoft.com>
|
||||
|
||||
description:
|
||||
VMBus is a software bus that implement the protocols for communication
|
||||
between the root or host OS and guest OSs (virtual machines).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microsoft,vmbus
|
||||
|
||||
ranges: true
|
||||
|
||||
'#address-cells':
|
||||
const: 2
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ranges
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
bus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vmbus@ff0000000 {
|
||||
compatible = "microsoft,vmbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -36,6 +36,7 @@ patternProperties:
|
||||
# All other properties should be child nodes with unit-address and 'reg'
|
||||
"@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
82
Bindings/bus/xlnx,versal-net-cdx.yaml
Normal file
82
Bindings/bus/xlnx,versal-net-cdx.yaml
Normal file
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: AMD CDX bus controller
|
||||
|
||||
description: |
|
||||
CDX bus controller for AMD devices is implemented to dynamically
|
||||
detect CDX bus and devices using the firmware.
|
||||
The CDX bus manages multiple FPGA based hardware devices, which
|
||||
can support network, crypto or any other specialized type of
|
||||
devices. These FPGA based devices can be added/modified dynamically
|
||||
on run-time.
|
||||
|
||||
All devices on the CDX bus will have a unique streamid (for IOMMU)
|
||||
and a unique device ID (for MSI) corresponding to a requestor ID
|
||||
(one to one associated with the device). The streamid and deviceid
|
||||
are used to configure SMMU and GIC-ITS respectively.
|
||||
|
||||
iommu-map property is used to define the set of stream ids
|
||||
corresponding to each device and the associated IOMMU.
|
||||
|
||||
The MSI writes are accompanied by sideband data (Device ID).
|
||||
The msi-map property is used to associate the devices with the
|
||||
device ID as well as the associated ITS controller.
|
||||
|
||||
rproc property (xlnx,rproc) is used to identify the remote processor
|
||||
with which APU (Application Processor Unit) interacts to find out
|
||||
the bus and device configuration.
|
||||
|
||||
maintainers:
|
||||
- Nipun Gupta <nipun.gupta@amd.com>
|
||||
- Nikhil Agarwal <nikhil.agarwal@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,versal-net-cdx
|
||||
|
||||
iommu-map: true
|
||||
|
||||
msi-map: true
|
||||
|
||||
xlnx,rproc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the remoteproc_r5 rproc node using which APU interacts
|
||||
with remote processor.
|
||||
|
||||
ranges: true
|
||||
|
||||
"#address-cells":
|
||||
enum: [1, 2]
|
||||
|
||||
"#size-cells":
|
||||
enum: [1, 2]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- iommu-map
|
||||
- msi-map
|
||||
- xlnx,rproc
|
||||
- ranges
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cdx {
|
||||
compatible = "xlnx,versal-net-cdx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* define map for RIDs 250-259 */
|
||||
iommu-map = <250 &smmu 250 10>;
|
||||
/* define msi map for RIDs 250-259 */
|
||||
msi-map = <250 &its 250 10>;
|
||||
xlnx,rproc = <&remoteproc_r5>;
|
||||
ranges;
|
||||
};
|
||||
63
Bindings/cache/baikal,bt1-l2-ctl.yaml
vendored
Normal file
63
Bindings/cache/baikal,bt1-l2-ctl.yaml
vendored
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 L2-cache Control Block
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
By means of the System Controller Baikal-T1 SoC exposes a few settings to
|
||||
tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
|
||||
to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
|
||||
L2-cache controller block is responsible for the tuning. Its DT node is
|
||||
supposed to be a child of the system controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: baikal,bt1-l2-ctl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
baikal,l2-ws-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Way-select RAM accesses
|
||||
default: 0
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
baikal,l2-tag-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Tag RAM accesses
|
||||
default: 0
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
baikal,l2-data-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Data RAM accesses
|
||||
default: 1
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
l2@1f04d028 {
|
||||
compatible = "baikal,bt1-l2-ctl";
|
||||
reg = <0x1f04d028 0x004>;
|
||||
|
||||
baikal,l2-ws-latency = <1>;
|
||||
baikal,l2-tag-latency = <1>;
|
||||
baikal,l2-data-latency = <2>;
|
||||
};
|
||||
...
|
||||
55
Bindings/cache/freescale-l2cache.txt
vendored
Normal file
55
Bindings/cache/freescale-l2cache.txt
vendored
Normal file
@ -0,0 +1,55 @@
|
||||
Freescale L2 Cache Controller
|
||||
|
||||
L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
|
||||
The cache bindings explained below are Devicetree Specification compliant
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible : Should include one of the following:
|
||||
"fsl,b4420-l2-cache-controller"
|
||||
"fsl,b4860-l2-cache-controller"
|
||||
"fsl,bsc9131-l2-cache-controller"
|
||||
"fsl,bsc9132-l2-cache-controller"
|
||||
"fsl,c293-l2-cache-controller"
|
||||
"fsl,mpc8536-l2-cache-controller"
|
||||
"fsl,mpc8540-l2-cache-controller"
|
||||
"fsl,mpc8541-l2-cache-controller"
|
||||
"fsl,mpc8544-l2-cache-controller"
|
||||
"fsl,mpc8548-l2-cache-controller"
|
||||
"fsl,mpc8555-l2-cache-controller"
|
||||
"fsl,mpc8560-l2-cache-controller"
|
||||
"fsl,mpc8568-l2-cache-controller"
|
||||
"fsl,mpc8569-l2-cache-controller"
|
||||
"fsl,mpc8572-l2-cache-controller"
|
||||
"fsl,p1010-l2-cache-controller"
|
||||
"fsl,p1011-l2-cache-controller"
|
||||
"fsl,p1012-l2-cache-controller"
|
||||
"fsl,p1013-l2-cache-controller"
|
||||
"fsl,p1014-l2-cache-controller"
|
||||
"fsl,p1015-l2-cache-controller"
|
||||
"fsl,p1016-l2-cache-controller"
|
||||
"fsl,p1020-l2-cache-controller"
|
||||
"fsl,p1021-l2-cache-controller"
|
||||
"fsl,p1022-l2-cache-controller"
|
||||
"fsl,p1023-l2-cache-controller"
|
||||
"fsl,p1024-l2-cache-controller"
|
||||
"fsl,p1025-l2-cache-controller"
|
||||
"fsl,p2010-l2-cache-controller"
|
||||
"fsl,p2020-l2-cache-controller"
|
||||
"fsl,t2080-l2-cache-controller"
|
||||
"fsl,t4240-l2-cache-controller"
|
||||
and "cache".
|
||||
- reg : Address and size of L2 cache controller registers
|
||||
- cache-size : Size of the entire L2 cache
|
||||
- interrupts : Error interrupt of L2 controller
|
||||
- cache-line-size : Size of L2 cache lines
|
||||
|
||||
Example:
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,bsc9132-l2-cache-controller", "cache";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 1 0>;
|
||||
};
|
||||
242
Bindings/cache/l2c2x0.yaml
vendored
Normal file
242
Bindings/cache/l2c2x0.yaml
vendored
Normal file
@ -0,0 +1,242 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM L2 Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description: |+
|
||||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
|
||||
PL220/PL310 and variants) based level 2 cache controller. All these various
|
||||
implementations of the L2 cache controller have compatible programming
|
||||
models (Note 1). Some of the properties that are just prefixed "cache-*" are
|
||||
taken from section 3.7.3 of the Devicetree Specification which can be found
|
||||
at:
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
||||
integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
|
||||
in the kernel at all.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
- items:
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- const: marvell,tauros3-cache
|
||||
- const: arm,pl310-cache
|
||||
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
cache-unified: true
|
||||
cache-size: true
|
||||
cache-sets: true
|
||||
cache-block-size: true
|
||||
cache-line-size: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,data-latency:
|
||||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,tag-latency:
|
||||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,dirty-latency:
|
||||
description: Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 8
|
||||
|
||||
arm,filter-ranges:
|
||||
description: <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
I/O coherent mode. Valid only when the arm,pl310-cache compatible
|
||||
string is used.
|
||||
type: boolean
|
||||
|
||||
interrupts:
|
||||
# Either a single combined interrupt or up to 9 individual interrupts
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
cache-id-part:
|
||||
description: cache id part number to be used if it is not present
|
||||
on hardware
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
wt-override:
|
||||
description: If present then L2 is forced to Write through mode
|
||||
type: boolean
|
||||
|
||||
arm,double-linefill:
|
||||
description: Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-incr:
|
||||
description: Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-wrap:
|
||||
description: Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-drop:
|
||||
description: Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-offset:
|
||||
description: Override prefetch offset value.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
|
||||
|
||||
arm,shared-override:
|
||||
description: The default behavior of the L220 or PL310 cache
|
||||
controllers with respect to the shareable attribute is to transform "normal
|
||||
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
||||
or "write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must
|
||||
be specified to indicate that such transforms are precluded.
|
||||
type: boolean
|
||||
|
||||
arm,parity-enable:
|
||||
description: enable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,parity-disable:
|
||||
description: disable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
marvell,ecc-enable:
|
||||
description: enable ECC protection on the L2 cache
|
||||
type: boolean
|
||||
|
||||
arm,outer-sync-disable:
|
||||
description: disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
|
||||
type: boolean
|
||||
|
||||
prefetch-data:
|
||||
description: |
|
||||
Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
prefetch-instr:
|
||||
description: |
|
||||
Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,dynamic-clock-gating:
|
||||
description: |
|
||||
L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,standby-mode:
|
||||
description: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,early-bresp-disable:
|
||||
description: Disable the CA9 optimization Early BRESP (PL310)
|
||||
type: boolean
|
||||
|
||||
arm,full-line-zero-disable:
|
||||
description: Disable the CA9 optimization Full line of zero
|
||||
write (PL310)
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cache-unified
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cache-controller@fff12000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x80000000 0x8000000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
interrupts = <45>;
|
||||
};
|
||||
|
||||
...
|
||||
16
Bindings/cache/marvell,feroceon-cache.txt
vendored
Normal file
16
Bindings/cache/marvell,feroceon-cache.txt
vendored
Normal file
@ -0,0 +1,16 @@
|
||||
* Marvell Feroceon Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be either "marvell,feroceon-cache" or
|
||||
"marvell,kirkwood-cache".
|
||||
|
||||
Optional properties:
|
||||
- reg : Address of the L2 cache control register. Mandatory for
|
||||
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
|
||||
|
||||
|
||||
Example:
|
||||
l2: l2-cache@20128 {
|
||||
compatible = "marvell,kirkwood-cache";
|
||||
reg = <0x20128 0x4>;
|
||||
};
|
||||
17
Bindings/cache/marvell,tauros2-cache.txt
vendored
Normal file
17
Bindings/cache/marvell,tauros2-cache.txt
vendored
Normal file
@ -0,0 +1,17 @@
|
||||
* Marvell Tauros2 Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,tauros2-cache".
|
||||
- marvell,tauros2-cache-features : Specify the features supported for the
|
||||
tauros2 cache.
|
||||
The features including
|
||||
CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
The definition can be found at
|
||||
arch/arm/include/asm/hardware/cache-tauros2.h
|
||||
|
||||
Example:
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
169
Bindings/cache/qcom,llcc.yaml
vendored
Normal file
169
Bindings/cache/qcom,llcc.yaml
vendored
Normal file
@ -0,0 +1,169 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Last Level Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
|
||||
that can be shared by multiple clients. Clients here are different cores in the
|
||||
SoC, the idea is to minimize the local caches at the clients and migrate to
|
||||
common pool of memory. Cache memory is divided into partitions called slices
|
||||
which are assigned to clients. Clients can query the slice details, activate
|
||||
and deactivate them.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
- qcom,sc8280xp-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm7150-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
- qcom,sm8350-llcc
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 9
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 9
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sm6350-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc8180x-llcc
|
||||
- qcom,sc8280xp-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC4 base register region
|
||||
- description: LLCC5 base register region
|
||||
- description: LLCC6 base register region
|
||||
- description: LLCC7 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc4_base
|
||||
- const: llcc5_base
|
||||
- const: llcc6_base
|
||||
- const: llcc7_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
- qcom,sm8350-llcc
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
system-cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
|
||||
<0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
|
||||
<0 0x01300000 0 0x50000>;
|
||||
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
|
||||
"llcc3_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
170
Bindings/cache/sifive,ccache0.yaml
vendored
Normal file
170
Bindings/cache/sifive,ccache0.yaml
vendored
Normal file
@ -0,0 +1,170 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 SiFive, Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SiFive Composable Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
|
||||
description:
|
||||
The SiFive Composable Cache Controller is used to provide access to fast copies
|
||||
of memory for masters in a Core Complex. The Composable Cache Controller also
|
||||
acts as directory-based coherency manager.
|
||||
All the properties in ePAPR/DeviceTree specification applies for this platform.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- sifive,ccache0
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sifive,ccache0
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
- const: cache
|
||||
- items:
|
||||
- const: starfive,jh7110-ccache
|
||||
- const: sifive,ccache0
|
||||
- const: cache
|
||||
- items:
|
||||
- const: microchip,mpfs-ccache
|
||||
- const: sifive,fu540-c000-ccache
|
||||
- const: cache
|
||||
|
||||
cache-block-size:
|
||||
const: 64
|
||||
|
||||
cache-level:
|
||||
enum: [2, 3]
|
||||
|
||||
cache-sets:
|
||||
enum: [1024, 2048]
|
||||
|
||||
cache-size:
|
||||
const: 2097152
|
||||
|
||||
cache-unified: true
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
items:
|
||||
- description: DirError interrupt
|
||||
- description: DataError interrupt
|
||||
- description: DataFail interrupt
|
||||
- description: DirFail interrupt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
next-level-cache: true
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
|
||||
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- sifive,fu740-c000-ccache
|
||||
- starfive,jh7110-ccache
|
||||
- microchip,mpfs-ccache
|
||||
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError, DataFail, DirFail signals.
|
||||
minItems: 4
|
||||
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- sifive,fu740-c000-ccache
|
||||
- starfive,jh7110-ccache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 2048
|
||||
|
||||
else:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 1024
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: sifive,ccache0
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-level:
|
||||
enum: [2, 3]
|
||||
|
||||
else:
|
||||
properties:
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cache-block-size
|
||||
- cache-level
|
||||
- cache-sets
|
||||
- cache-size
|
||||
- cache-unified
|
||||
- interrupts
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
cache-controller@2010000 {
|
||||
compatible = "sifive,fu540-c000-ccache", "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-sets = <1024>;
|
||||
cache-size = <2097152>;
|
||||
cache-unified;
|
||||
reg = <0x2010000 0x1000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <1>,
|
||||
<2>,
|
||||
<3>;
|
||||
next-level-cache = <&L25>;
|
||||
memory-region = <&l2_lim>;
|
||||
};
|
||||
101
Bindings/cache/socionext,uniphier-system-cache.yaml
vendored
Normal file
101
Bindings/cache/socionext,uniphier-system-cache.yaml
vendored
Normal file
@ -0,0 +1,101 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: UniPhier outer cache controller
|
||||
|
||||
description: |
|
||||
UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
|
||||
controller system. All of them have a level 2 cache controller, and some
|
||||
have a level 3 cache controller as well.
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: socionext,uniphier-system-cache
|
||||
|
||||
reg:
|
||||
description: |
|
||||
should contain 3 regions: control register, revision register,
|
||||
operation register, in this order.
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
Interrupts can be used to notify the completion of cache operations.
|
||||
The number of interrupts should match to the number of CPU cores.
|
||||
The specified interrupts correspond to CPU0, CPU1, ... in this order.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
cache-unified: true
|
||||
|
||||
cache-size: true
|
||||
|
||||
cache-sets: true
|
||||
|
||||
cache-line-size: true
|
||||
|
||||
cache-level:
|
||||
minimum: 2
|
||||
maximum: 3
|
||||
|
||||
next-level-cache: true
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- cache-unified
|
||||
- cache-size
|
||||
- cache-sets
|
||||
- cache-line-size
|
||||
- cache-level
|
||||
|
||||
examples:
|
||||
- |
|
||||
// System with L2.
|
||||
cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x140000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
- |
|
||||
// System with L2 and L3.
|
||||
// L2 should specify the next level cache by 'next-level-cache'.
|
||||
l2: cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
|
||||
interrupts = <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
l3: cache-controller@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
@ -41,7 +41,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |+
|
||||
spi0 {
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi0 {
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
- enum:
|
||||
- apple,t6000-nco
|
||||
- apple,t8103-nco
|
||||
- apple,t8112-nco
|
||||
- const: apple,nco
|
||||
|
||||
clocks:
|
||||
|
||||
@ -81,11 +81,11 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
lock-offset:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Offset to the unlocking register for the oscillator
|
||||
|
||||
vco-offset:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Offset to the VCO register for the oscillator
|
||||
deprecated: true
|
||||
|
||||
|
||||
40
Bindings/clock/brcm,bcm63268-timer-clocks.yaml
Normal file
40
Bindings/clock/brcm,bcm63268-timer-clocks.yaml
Normal file
@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm63268-timer-clocks
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer_clk: clock-controller@100000ac {
|
||||
compatible = "brcm,bcm63268-timer-clocks";
|
||||
reg = <0x100000ac 0x4>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Canaan Kendryte K210 Clock
|
||||
|
||||
maintainers:
|
||||
- Damien Le Moal <damien.lemoal@wdc.com>
|
||||
- Damien Le Moal <dlemoal@kernel.org>
|
||||
|
||||
description: |
|
||||
Canaan Kendryte K210 SoC clocks driver bindings. The clock
|
||||
|
||||
79
Bindings/clock/imx8mp-audiomix.yaml
Normal file
79
Bindings/clock/imx8mp-audiomix.yaml
Normal file
@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8MP AudioMIX Block Control Binding
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
|
||||
used to control Audio related clock on the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-audio-blk-ctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ahb
|
||||
- const: sai1
|
||||
- const: sai2
|
||||
- const: sai3
|
||||
- const: sai5
|
||||
- const: sai6
|
||||
- const: sai7
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
|
||||
for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
|
||||
clock-controller@30e20000 {
|
||||
compatible = "fsl,imx8mp-audio-blk-ctrl";
|
||||
reg = <0x30e20000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
|
||||
<&clk IMX8MP_CLK_SAI1>,
|
||||
<&clk IMX8MP_CLK_SAI2>,
|
||||
<&clk IMX8MP_CLK_SAI3>,
|
||||
<&clk IMX8MP_CLK_SAI5>,
|
||||
<&clk IMX8MP_CLK_SAI6>,
|
||||
<&clk IMX8MP_CLK_SAI7>;
|
||||
clock-names = "ahb",
|
||||
"sai1", "sai2", "sai3",
|
||||
"sai5", "sai6", "sai7";
|
||||
power-domains = <&pgc_audio>;
|
||||
};
|
||||
|
||||
...
|
||||
45
Bindings/clock/loongson,ls1x-clk.yaml
Normal file
45
Bindings/clock/loongson,ls1x-clk.yaml
Normal file
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Loongson-1 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Keguang Zhang <keguang.zhang@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- loongson,ls1b-clk
|
||||
- loongson,ls1c-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clkc: clock-controller@1fe78030 {
|
||||
compatible = "loongson,ls1b-clk";
|
||||
reg = <0x1fe78030 0x8>;
|
||||
|
||||
clocks = <&xtal>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek AP Mixedsys Controller
|
||||
|
||||
|
||||
@ -16,7 +16,12 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8186-fhctl
|
||||
enum:
|
||||
- mediatek,mt6795-fhctl
|
||||
- mediatek,mt8173-fhctl
|
||||
- mediatek,mt8186-fhctl
|
||||
- mediatek,mt8192-fhctl
|
||||
- mediatek,mt8195-fhctl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
71
Bindings/clock/mediatek,mt8188-clock.yaml
Normal file
71
Bindings/clock/mediatek,mt8188-clock.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8188
|
||||
|
||||
maintainers:
|
||||
- Garmin Chang <garmin.chang@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The devices provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8188-adsp-audio26m
|
||||
- mediatek,mt8188-camsys
|
||||
- mediatek,mt8188-camsys-rawa
|
||||
- mediatek,mt8188-camsys-rawb
|
||||
- mediatek,mt8188-camsys-yuva
|
||||
- mediatek,mt8188-camsys-yuvb
|
||||
- mediatek,mt8188-ccusys
|
||||
- mediatek,mt8188-imgsys
|
||||
- mediatek,mt8188-imgsys-wpe1
|
||||
- mediatek,mt8188-imgsys-wpe2
|
||||
- mediatek,mt8188-imgsys-wpe3
|
||||
- mediatek,mt8188-imgsys1-dip-nr
|
||||
- mediatek,mt8188-imgsys1-dip-top
|
||||
- mediatek,mt8188-imp-iic-wrap-c
|
||||
- mediatek,mt8188-imp-iic-wrap-en
|
||||
- mediatek,mt8188-imp-iic-wrap-w
|
||||
- mediatek,mt8188-ipesys
|
||||
- mediatek,mt8188-mfgcfg
|
||||
- mediatek,mt8188-vdecsys
|
||||
- mediatek,mt8188-vdecsys-soc
|
||||
- mediatek,mt8188-vencsys
|
||||
- mediatek,mt8188-vppsys0
|
||||
- mediatek,mt8188-vppsys1
|
||||
- mediatek,mt8188-wpesys
|
||||
- mediatek,mt8188-wpesys-vpp0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11283000 {
|
||||
compatible = "mediatek,mt8188-imp-iic-wrap-c";
|
||||
reg = <0x11283000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
55
Bindings/clock/mediatek,mt8188-sys-clock.yaml
Normal file
55
Bindings/clock/mediatek,mt8188-sys-clock.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8188
|
||||
|
||||
maintainers:
|
||||
- Garmin Chang <garmin.chang@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
|
||||
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
The mcusys provides mux control to select the clock source in AP MCU.
|
||||
The device nodes also provide the system control capacity for configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8188-apmixedsys
|
||||
- mediatek,mt8188-infracfg-ao
|
||||
- mediatek,mt8188-pericfg-ao
|
||||
- mediatek,mt8188-topckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@10000000 {
|
||||
compatible = "mediatek,mt8188-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Top Clock Generator Controller
|
||||
|
||||
|
||||
@ -16,6 +16,7 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq5332-a53pll
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,msm8916-a53pll
|
||||
@ -45,14 +46,14 @@ required:
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
#Example 1 - A53 PLL found on MSM8916 devices
|
||||
# Example 1 - A53 PLL found on MSM8916 devices
|
||||
- |
|
||||
a53pll: clock@b016000 {
|
||||
compatible = "qcom,msm8916-a53pll";
|
||||
reg = <0xb016000 0x40>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
#Example 2 - A53 PLL found on IPQ6018 devices
|
||||
# Example 2 - A53 PLL found on IPQ6018 devices
|
||||
- |
|
||||
a53pll_ipq: clock-controller@b116000 {
|
||||
compatible = "qcom,ipq6018-a53pll";
|
||||
|
||||
53
Bindings/clock/qcom,gcc-ipq4019.yaml
Normal file
53
Bindings/clock/qcom,gcc-ipq4019.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ4019
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
- Robert Marko <robert.markoo@sartura.hr>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ4019.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq4019
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
|
||||
- description: sleep clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-ipq4019";
|
||||
reg = <0x1800000 0x60000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xo>, <&sleep_clk>;
|
||||
clock-names = "xo", "sleep_clk";
|
||||
};
|
||||
...
|
||||
@ -4,20 +4,25 @@
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8909
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
|
||||
|
||||
maintainers:
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8909.
|
||||
domains on MSM8909, MSM8917 or QM215.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8917.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8909
|
||||
enum:
|
||||
- qcom,gcc-msm8909
|
||||
- qcom,gcc-msm8917
|
||||
- qcom,gcc-qm215
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@ -15,7 +15,6 @@ description: |
|
||||
domains.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
include/dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
@ -29,7 +28,6 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8953
|
||||
|
||||
@ -15,6 +15,7 @@ description: |
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
|
||||
@ -27,6 +28,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sa8775p-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
|
||||
53
Bindings/clock/qcom,ipq5332-gcc.yaml
Normal file
53
Bindings/clock/qcom,ipq5332-gcc.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ5332
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ5332.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq5332-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO clock source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 2lane PHY pipe clock source
|
||||
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,ipq5332-gcc";
|
||||
reg = <0x01800000 0x80000>;
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_2lane_phy_pipe_clk>,
|
||||
<&pcie_2lane_phy_pipe_clk_x1>,
|
||||
<&usb_pcie_wrapper_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
61
Bindings/clock/qcom,ipq9574-gcc.yaml
Normal file
61
Bindings/clock/qcom,ipq9574-gcc.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ9574
|
||||
|
||||
maintainers:
|
||||
- Anusha Rao <quic_anusha@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ9574
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,ipq9574-gcc.h
|
||||
include/dt-bindings/reset/qcom,ipq9574-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq9574-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: Bias PLL ubi clock source
|
||||
- description: PCIE30 PHY0 pipe clock source
|
||||
- description: PCIE30 PHY1 pipe clock source
|
||||
- description: PCIE30 PHY2 pipe clock source
|
||||
- description: PCIE30 PHY3 pipe clock source
|
||||
- description: USB3 PHY pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,ipq9574-gcc";
|
||||
reg = <0x01800000 0x80000>;
|
||||
clocks = <&xo_board_clk>,
|
||||
<&sleep_clk>,
|
||||
<&bias_pll_ubi_nc_clk>,
|
||||
<&pcie30_phy0_pipe_clk>,
|
||||
<&pcie30_phy1_pipe_clk>,
|
||||
<&pcie30_phy2_pipe_clk>,
|
||||
<&pcie30_phy3_pipe_clk>,
|
||||
<&usb3phy_0_cc_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
72
Bindings/clock/qcom,kpss-acc-v1.yaml
Normal file
72
Bindings/clock/qcom,kpss-acc-v1.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
|
||||
There is one ACC register region per CPU within the KPSS remapped region as
|
||||
well as an alias register region that remaps accesses to the ACC associated
|
||||
with the CPU accessing the region. ACC v1 is currently used as a
|
||||
clock-controller for enabling the cpu and hanling the aux clocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kpss-acc-v1
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base address and size of the register region
|
||||
- description: Optional base address and size of the alias register region
|
||||
minItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll8_vote
|
||||
- const: pxo
|
||||
|
||||
clock-output-names:
|
||||
description: Name of the aux clock. Krait can have at most 4 cpu.
|
||||
enum:
|
||||
- acpu0_aux
|
||||
- acpu1_aux
|
||||
- acpu2_aux
|
||||
- acpu3_aux
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- clock-output-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu0_aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
...
|
||||
88
Bindings/clock/qcom,kpss-gcc.yaml
Normal file
88
Bindings/clock/qcom,kpss-gcc.yaml
Normal file
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
|
||||
to control L2 mux (in the current implementation) and provide access
|
||||
to the kpss-gcc registers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,kpss-gcc-ipq8064
|
||||
- qcom,kpss-gcc-apq8064
|
||||
- qcom,kpss-gcc-msm8974
|
||||
- qcom,kpss-gcc-msm8960
|
||||
- qcom,kpss-gcc-msm8660
|
||||
- qcom,kpss-gcc-mdm9615
|
||||
- const: qcom,kpss-gcc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll8_vote
|
||||
- const: pxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kpss-gcc-ipq8064
|
||||
- qcom,kpss-gcc-apq8064
|
||||
- qcom,kpss-gcc-msm8974
|
||||
- qcom,kpss-gcc-msm8960
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
else:
|
||||
properties:
|
||||
clock: false
|
||||
clock-names: false
|
||||
'#clock-cells': false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
|
||||
clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
|
||||
reg = <0x2011000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
- |
|
||||
clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
|
||||
reg = <0x02011000 0x1000>;
|
||||
};
|
||||
...
|
||||
@ -31,6 +31,7 @@ properties:
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8909
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
@ -107,6 +108,7 @@ allOf:
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
|
||||
@ -41,6 +41,12 @@ properties:
|
||||
- const: qdsp6ss
|
||||
- const: top_cc
|
||||
|
||||
qcom,adsp-pil-mode:
|
||||
description:
|
||||
Indicates if the LPASS would be brought out of reset using
|
||||
remoteproc peripheral loader.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -60,6 +66,7 @@ examples:
|
||||
reg-names = "qdsp6ss", "top_cc";
|
||||
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
|
||||
clock-names = "iface";
|
||||
qcom,adsp-pil-mode;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
58
Bindings/clock/qcom,sm6115-gpucc.yaml
Normal file
58
Bindings/clock/qcom,sm6115-gpucc.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6115
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 main div source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6115-gpucc";
|
||||
reg = <0x05990000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
64
Bindings/clock/qcom,sm6125-gpucc.yaml
Normal file
64
Bindings/clock/qcom,sm6125-gpucc.yaml
Normal file
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6125
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks and power domains on
|
||||
Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6125-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6125-gpucc";
|
||||
reg = <0x05990000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
60
Bindings/clock/qcom,sm6375-gpucc.yaml
Normal file
60
Bindings/clock/qcom,sm6375-gpucc.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM6375
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6375-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
- description: SNoC DVM GFX source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,sm6375-gpucc";
|
||||
reg = <0 0x05990000 0 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
52
Bindings/clock/qcom,sm7150-gcc.yaml
Normal file
52
Bindings/clock/qcom,sm7150-gcc.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM7150
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Danila Tikhonov <danila@jiaxyga.com>
|
||||
- David Wronek <davidwronek@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM7150
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm7150-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO Active-Only source
|
||||
- description: Sleep clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm7150-gcc";
|
||||
reg = <0x00100000 0x001f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -16,6 +16,11 @@ description: |
|
||||
- 9FGV0241:
|
||||
0 -- DIF0
|
||||
1 -- DIF1
|
||||
- 9FGV0441:
|
||||
0 -- DIF0
|
||||
1 -- DIF1
|
||||
2 -- DIF2
|
||||
3 -- DIF3
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
@ -24,6 +29,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,9fgv0241
|
||||
- renesas,9fgv0441
|
||||
|
||||
reg:
|
||||
description: I2C device address
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Renesas RZ/N1D (R9A06G032) System Controller
|
||||
|
||||
maintainers:
|
||||
- Gareth Williams <gareth.williams.jx@renesas.com>
|
||||
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car USB 2.0 clock selector
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
|
||||
@ -37,6 +37,7 @@ properties:
|
||||
- samsung,exynos850-cmu-cmgp
|
||||
- samsung,exynos850-cmu-core
|
||||
- samsung,exynos850-cmu-dpu
|
||||
- samsung,exynos850-cmu-g3d
|
||||
- samsung,exynos850-cmu-hsi
|
||||
- samsung,exynos850-cmu-is
|
||||
- samsung,exynos850-cmu-mfcmscl
|
||||
@ -169,6 +170,24 @@ allOf:
|
||||
- const: oscclk
|
||||
- const: dout_dpu
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-g3d
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: G3D clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_g3d_switch
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -183,7 +202,7 @@ allOf:
|
||||
- description: External RTC clock (32768 Hz)
|
||||
- description: CMU_HSI bus clock (from CMU_TOP)
|
||||
- description: SD card clock (from CMU_TOP)
|
||||
- description: "USB 2.0 DRD clock (from CMU_TOP)"
|
||||
- description: USB 2.0 DRD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
||||
59
Bindings/clock/skyworks,si521xx.yaml
Normal file
59
Bindings/clock/skyworks,si521xx.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/skyworks,si521xx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Skyworks Si521xx I2C PCIe clock generators
|
||||
|
||||
description: |
|
||||
The Skyworks Si521xx are I2C PCIe clock generators providing
|
||||
from 4 to 9 output clocks.
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- skyworks,si52144
|
||||
- skyworks,si52146
|
||||
- skyworks,si52147
|
||||
|
||||
reg:
|
||||
const: 0x6b
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XTal input clock
|
||||
|
||||
skyworks,out-amplitude-microvolt:
|
||||
enum: [ 300000, 400000, 500000, 600000, 700000, 800000, 900000, 1000000 ]
|
||||
description: Output clock signal amplitude
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-generator@6b {
|
||||
compatible = "skyworks,si52144";
|
||||
reg = <0x6b>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ref25m>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -2,8 +2,8 @@
|
||||
# Copyright 2019 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SC9863A Clock Control Unit
|
||||
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
# Copyright 2022 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: UMS512 Soc clock controller
|
||||
|
||||
|
||||
107
Bindings/clock/starfive,jh7110-aoncrg.yaml
Normal file
107
Bindings/clock/starfive,jh7110-aoncrg.yaml
Normal file
@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7110 Always-On Clock and Reset Generator
|
||||
|
||||
maintainers:
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7110-aoncrg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
oneOf:
|
||||
- items:
|
||||
- description: Main Oscillator (24 MHz)
|
||||
- description: GMAC0 RMII reference or GMAC0 RGMII RX
|
||||
- description: STG AXI/AHB
|
||||
- description: APB Bus
|
||||
- description: GMAC0 GTX
|
||||
|
||||
- items:
|
||||
- description: Main Oscillator (24 MHz)
|
||||
- description: GMAC0 RMII reference or GMAC0 RGMII RX
|
||||
- description: STG AXI/AHB or GMAC0 RGMII RX
|
||||
- description: APB Bus or STG AXI/AHB
|
||||
- description: GMAC0 GTX or APB Bus
|
||||
- description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
|
||||
|
||||
- items:
|
||||
- description: Main Oscillator (24 MHz)
|
||||
- description: GMAC0 RMII reference
|
||||
- description: GMAC0 RGMII RX
|
||||
- description: STG AXI/AHB
|
||||
- description: APB Bus
|
||||
- description: GMAC0 GTX
|
||||
- description: RTC Oscillator (32.768 kHz)
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- minItems: 5
|
||||
items:
|
||||
- const: osc
|
||||
- enum:
|
||||
- gmac0_rmii_refin
|
||||
- gmac0_rgmii_rxin
|
||||
- const: stg_axiahb
|
||||
- const: apb_bus
|
||||
- const: gmac0_gtxclk
|
||||
- const: rtc_osc
|
||||
|
||||
- minItems: 6
|
||||
items:
|
||||
- const: osc
|
||||
- const: gmac0_rmii_refin
|
||||
- const: gmac0_rgmii_rxin
|
||||
- const: stg_axiahb
|
||||
- const: apb_bus
|
||||
- const: gmac0_gtxclk
|
||||
- const: rtc_osc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/starfive,jh7110-crg.h>
|
||||
|
||||
clock-controller@17000000 {
|
||||
compatible = "starfive,jh7110-aoncrg";
|
||||
reg = <0x17000000 0x10000>;
|
||||
clocks = <&osc>, <&gmac0_rmii_refin>,
|
||||
<&gmac0_rgmii_rxin>,
|
||||
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
|
||||
<&syscrg JH7110_SYSCLK_APB_BUS>,
|
||||
<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
|
||||
<&rtc_osc>;
|
||||
clock-names = "osc", "gmac0_rmii_refin",
|
||||
"gmac0_rgmii_rxin", "stg_axiahb",
|
||||
"apb_bus", "gmac0_gtxclk",
|
||||
"rtc_osc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
104
Bindings/clock/starfive,jh7110-syscrg.yaml
Normal file
104
Bindings/clock/starfive,jh7110-syscrg.yaml
Normal file
@ -0,0 +1,104 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7110 System Clock and Reset Generator
|
||||
|
||||
maintainers:
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7110-syscrg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
oneOf:
|
||||
- items:
|
||||
- description: Main Oscillator (24 MHz)
|
||||
- description: GMAC1 RMII reference or GMAC1 RGMII RX
|
||||
- description: External I2S TX bit clock
|
||||
- description: External I2S TX left/right channel clock
|
||||
- description: External I2S RX bit clock
|
||||
- description: External I2S RX left/right channel clock
|
||||
- description: External TDM clock
|
||||
- description: External audio master clock
|
||||
|
||||
- items:
|
||||
- description: Main Oscillator (24 MHz)
|
||||
- description: GMAC1 RMII reference
|
||||
- description: GMAC1 RGMII RX
|
||||
- description: External I2S TX bit clock
|
||||
- description: External I2S TX left/right channel clock
|
||||
- description: External I2S RX bit clock
|
||||
- description: External I2S RX left/right channel clock
|
||||
- description: External TDM clock
|
||||
- description: External audio master clock
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: osc
|
||||
- enum:
|
||||
- gmac1_rmii_refin
|
||||
- gmac1_rgmii_rxin
|
||||
- const: i2stx_bclk_ext
|
||||
- const: i2stx_lrck_ext
|
||||
- const: i2srx_bclk_ext
|
||||
- const: i2srx_lrck_ext
|
||||
- const: tdm_ext
|
||||
- const: mclk_ext
|
||||
|
||||
- items:
|
||||
- const: osc
|
||||
- const: gmac1_rmii_refin
|
||||
- const: gmac1_rgmii_rxin
|
||||
- const: i2stx_bclk_ext
|
||||
- const: i2stx_lrck_ext
|
||||
- const: i2srx_bclk_ext
|
||||
- const: i2srx_lrck_ext
|
||||
- const: tdm_ext
|
||||
- const: mclk_ext
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@13020000 {
|
||||
compatible = "starfive,jh7110-syscrg";
|
||||
reg = <0x13020000 0x10000>;
|
||||
clocks = <&osc>, <&gmac1_rmii_refin>,
|
||||
<&gmac1_rgmii_rxin>,
|
||||
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
|
||||
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
|
||||
<&tdm_ext>, <&mclk_ext>;
|
||||
clock-names = "osc", "gmac1_rmii_refin",
|
||||
"gmac1_rgmii_rxin",
|
||||
"i2stx_bclk_ext", "i2stx_lrck_ext",
|
||||
"i2srx_bclk_ext", "i2srx_lrck_ext",
|
||||
"tdm_ext", "mclk_ext";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -160,7 +160,7 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx clocking wizard
|
||||
|
||||
|
||||
@ -20,12 +20,20 @@ properties:
|
||||
oneOf:
|
||||
- description: v1 of CPUFREQ HW
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qcm2290-cpufreq-hw
|
||||
- qcom,sc7180-cpufreq-hw
|
||||
- qcom,sdm845-cpufreq-hw
|
||||
- qcom,sm6115-cpufreq-hw
|
||||
- qcom,sm6350-cpufreq-hw
|
||||
- qcom,sm8150-cpufreq-hw
|
||||
- const: qcom,cpufreq-hw
|
||||
|
||||
- description: v2 of CPUFREQ HW (EPSS)
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sa8775p-cpufreq-epss
|
||||
- qcom,sc7280-cpufreq-epss
|
||||
- qcom,sc8280xp-cpufreq-epss
|
||||
- qcom,sm6375-cpufreq-epss
|
||||
@ -36,14 +44,14 @@ properties:
|
||||
- const: qcom,cpufreq-epss
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Frequency domain 0 register region
|
||||
- description: Frequency domain 1 register region
|
||||
- description: Frequency domain 2 register region
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
items:
|
||||
- const: freq-domain0
|
||||
- const: freq-domain1
|
||||
@ -85,6 +93,111 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcm2290-cpufreq-hw
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sc7180-cpufreq-hw
|
||||
- qcom,sc8280xp-cpufreq-epss
|
||||
- qcom,sdm845-cpufreq-hw
|
||||
- qcom,sm6115-cpufreq-hw
|
||||
- qcom,sm6350-cpufreq-hw
|
||||
- qcom,sm6375-cpufreq-epss
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
minItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-cpufreq-epss
|
||||
- qcom,sm8250-cpufreq-epss
|
||||
- qcom,sm8350-cpufreq-epss
|
||||
- qcom,sm8450-cpufreq-epss
|
||||
- qcom,sm8550-cpufreq-epss
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8150-cpufreq-hw
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
# On some SoCs the Prime core shares the LMH irq with Big cores
|
||||
interrupts:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
minItems: 2
|
||||
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
@ -235,7 +348,7 @@ examples:
|
||||
#size-cells = <1>;
|
||||
|
||||
cpufreq@17d43000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
|
||||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
|
||||
156
Bindings/crypto/fsl,sec-v4.0-mon.yaml
Normal file
156
Bindings/crypto/fsl,sec-v4.0-mon.yaml
Normal file
@ -0,0 +1,156 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Secure Non-Volatile Storage (SNVS)
|
||||
|
||||
maintainers:
|
||||
- '"Horia Geantă" <horia.geanta@nxp.com>'
|
||||
- Pankaj Gupta <pankaj.gupta@nxp.com>
|
||||
- Gaurav Jain <gaurav.jain@nxp.com>
|
||||
|
||||
description:
|
||||
Node defines address range and the associated interrupt for the SNVS function.
|
||||
This function monitors security state information & reports security
|
||||
violations. This also included rtc, system power off and ON/OFF key.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v4.0-mon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: fsl,sec-v5.0-mon
|
||||
- const: fsl,sec-v4.0-mon
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,sec-v5.3-mon
|
||||
- fsl,sec-v5.4-mon
|
||||
- const: fsl,sec-v5.0-mon
|
||||
- const: fsl,sec-v4.0-mon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
snvs-rtc-lp:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,sec-v4.0-mon-rtc-lp
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: snvs-rtc
|
||||
|
||||
interrupts:
|
||||
# VFxxx has only one. What is the 2nd one?
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
regmap:
|
||||
description: Parent node containing registers
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
offset:
|
||||
description: LP register offset
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x34
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupts
|
||||
- regmap
|
||||
|
||||
snvs-powerkey:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
The snvs-pwrkey is designed to enable POWER key function which controlled
|
||||
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
|
||||
system if pressed after system suspend.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,sec-v4.0-pwrkey
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: snvs-pwrkey
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
regmap:
|
||||
description: Parent node containing registers
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
linux,keycode:
|
||||
default: 116
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupts
|
||||
- regmap
|
||||
|
||||
snvs-lpgpr:
|
||||
$ref: /schemas/nvmem/snvs-lpgpr.yaml#
|
||||
|
||||
snvs-poweroff:
|
||||
description:
|
||||
The SNVS could drive signal to PMIC to turn off system power by setting
|
||||
SNVS_LP LPCR register.
|
||||
$ref: /schemas/power/reset/syscon-poweroff.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/imx7d-clock.h>
|
||||
|
||||
sec_mon: sec-mon@314000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
||||
reg = <0x314000 0x1000>;
|
||||
|
||||
snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&sec_mon>;
|
||||
offset = <0x34>;
|
||||
clocks = <&clks IMX7D_SNVS_CLK>;
|
||||
clock-names = "snvs-rtc";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&sec_mon>;
|
||||
clocks = <&clks IMX7D_SNVS_CLK>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
linux,keycode = <116>; /* KEY_POWER */
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
266
Bindings/crypto/fsl,sec-v4.0.yaml
Normal file
266
Bindings/crypto/fsl,sec-v4.0.yaml
Normal file
@ -0,0 +1,266 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale SEC 4
|
||||
|
||||
maintainers:
|
||||
- '"Horia Geantă" <horia.geanta@nxp.com>'
|
||||
- Pankaj Gupta <pankaj.gupta@nxp.com>
|
||||
- Gaurav Jain <gaurav.jain@nxp.com>
|
||||
|
||||
description: |
|
||||
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
|
||||
Accelerator and Assurance Module (CAAM).
|
||||
|
||||
SEC 4 h/w can process requests from 2 types of sources.
|
||||
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
|
||||
2. Job Rings (HW interface between cores & SEC 4 registers).
|
||||
|
||||
High Speed Data Path Configuration:
|
||||
|
||||
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
|
||||
such as the P4080. The number of simultaneous dequeues the QI can make is
|
||||
equal to the number of Descriptor Controller (DECO) engines in a particular
|
||||
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
|
||||
dequeue from 5 subportals simultaneously.
|
||||
|
||||
Job Ring Data Path Configuration:
|
||||
|
||||
Each JR is located on a separate 4k page, they may (or may not) be made visible
|
||||
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
|
||||
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v5.4
|
||||
- const: fsl,sec-v5.0
|
||||
- const: fsl,sec-v4.0
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6ul-caam
|
||||
- fsl,sec-v5.0
|
||||
- const: fsl,sec-v4.0
|
||||
- const: fsl,sec-v4.0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
enum: [1, 2]
|
||||
|
||||
'#size-cells':
|
||||
enum: [1, 2]
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [mem, aclk, ipg, emi_slow]
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
fsl,sec-era:
|
||||
description: Defines the 'ERA' of the SEC device.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
patternProperties:
|
||||
'^jr@[0-9a-f]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
|
||||
peripheral bus for purposes of processing cryptographic descriptors. The
|
||||
specified address range can be made visible to one (or more) cores. The
|
||||
interrupt defined for this node is controlled within the address range of
|
||||
this node.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v5.4-job-ring
|
||||
- const: fsl,sec-v5.0-job-ring
|
||||
- const: fsl,sec-v4.0-job-ring
|
||||
- items:
|
||||
- const: fsl,sec-v5.0-job-ring
|
||||
- const: fsl,sec-v4.0-job-ring
|
||||
- const: fsl,sec-v4.0-job-ring
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
fsl,liodn:
|
||||
description:
|
||||
Specifies the LIODN to be used in conjunction with the ppid-to-liodn
|
||||
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
|
||||
used. Value is a 12 bit value where value is a LIODN ID for this JR.
|
||||
This property is normally set by boot firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
|
||||
'^rtic@[0-9a-f]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
Run Time Integrity Check (RTIC) Node. Defines a register space that
|
||||
contains up to 5 sets of addresses and their lengths (sizes) that will be
|
||||
checked at run time. After an initial hash result is calculated, these
|
||||
addresses are checked by HW to monitor any change. If any memory is
|
||||
modified, a Security Violation is triggered (see SNVS definition).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v5.4-rtic
|
||||
- const: fsl,sec-v5.0-rtic
|
||||
- const: fsl,sec-v4.0-rtic
|
||||
- const: fsl,sec-v4.0-rtic
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
'^rtic-[a-z]@[0-9a-f]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
|
||||
memory regions that are used to perform run-time integrity check of
|
||||
memory areas that should not modified. The node defines a register
|
||||
that contains the memory address & length (combined) and a second
|
||||
register that contains the hash result in big endian format.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v5.4-rtic-memory
|
||||
- const: fsl,sec-v5.0-rtic-memory
|
||||
- const: fsl,sec-v4.0-rtic-memory
|
||||
- const: fsl,sec-v4.0-rtic-memory
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: RTIC memory address
|
||||
- description: RTIC hash result
|
||||
|
||||
fsl,liodn:
|
||||
description:
|
||||
Specifies the LIODN to be used in conjunction with the
|
||||
ppid-to-liodn table that specifies the PPID to LIODN mapping.
|
||||
Needed if the PAMU is used. Value is a 12 bit value where value
|
||||
is a LIODN ID for this JR. This property is normally set by boot
|
||||
firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
|
||||
fsl,rtic-region:
|
||||
description:
|
||||
Specifies the HW address (36 bit address) for this region
|
||||
followed by the length of the HW partition to be checked;
|
||||
the address is represented as a 64 bit quantity followed
|
||||
by a 32 bit length.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupts = <92 2>;
|
||||
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2>;
|
||||
};
|
||||
|
||||
jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2>;
|
||||
};
|
||||
|
||||
jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2>;
|
||||
};
|
||||
|
||||
jr@4000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20>, <0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20>, <0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20>, <0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20>, <0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
42
Bindings/crypto/qcom,inline-crypto-engine.yaml
Normal file
42
Bindings/crypto/qcom,inline-crypto-engine.yaml
Normal file
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sm8550-inline-crypto-engine
|
||||
- const: qcom,inline-crypto-engine
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
|
||||
|
||||
crypto@1d88000 {
|
||||
compatible = "qcom,sm8550-inline-crypto-engine",
|
||||
"qcom,inline-crypto-engine";
|
||||
reg = <0x01d88000 0x8000>;
|
||||
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
||||
};
|
||||
...
|
||||
123
Bindings/crypto/qcom-qce.yaml
Normal file
123
Bindings/crypto/qcom-qce.yaml
Normal file
@ -0,0 +1,123 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm crypto engine driver
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
|
||||
description:
|
||||
This document defines the binding for the QCE crypto
|
||||
controller found on Qualcomm parts.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,crypto-v5.1
|
||||
deprecated: true
|
||||
description: Kept only for ABI backward compatibility
|
||||
|
||||
- const: qcom,crypto-v5.4
|
||||
deprecated: true
|
||||
description: Kept only for ABI backward compatibility
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq6018-qce
|
||||
- qcom,ipq8074-qce
|
||||
- qcom,msm8996-qce
|
||||
- qcom,sdm845-qce
|
||||
- const: qcom,ipq4019-qce
|
||||
- const: qcom,qce
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8250-qce
|
||||
- qcom,sm8350-qce
|
||||
- qcom,sm8450-qce
|
||||
- qcom,sm8550-qce
|
||||
- const: qcom,sm8150-qce
|
||||
- const: qcom,qce
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: iface clocks register interface.
|
||||
- description: bus clocks data transfer interface.
|
||||
- description: core clocks rest of the crypto block.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
phandle to apps_smmu node with sid mask.
|
||||
|
||||
interconnects:
|
||||
maxItems: 1
|
||||
description:
|
||||
Interconnect path between qce crypto and main memory.
|
||||
|
||||
interconnect-names:
|
||||
const: memory
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: DMA specifiers for rx dma channel.
|
||||
- description: DMA specifiers for tx dma channel.
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,crypto-v5.1
|
||||
- qcom,crypto-v5.4
|
||||
- qcom,ipq4019-qce
|
||||
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
|
||||
crypto-engine@fd45a000 {
|
||||
compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
|
||||
reg = <0xfd45a000 0x6000>;
|
||||
clocks = <&gcc GCC_CE2_AHB_CLK>,
|
||||
<&gcc GCC_CE2_AXI_CLK>,
|
||||
<&gcc GCC_CE2_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
||||
dma-names = "rx", "tx";
|
||||
iommus = <&apps_smmu 0x584 0x0011>,
|
||||
<&apps_smmu 0x586 0x0011>,
|
||||
<&apps_smmu 0x594 0x0011>,
|
||||
<&apps_smmu 0x596 0x0011>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user