Always read/write the full 64-bit value of 64-bit BARs. Specifically,
when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
This commit is contained in:
John Baldwin
parent
d004885d3a
commit
c4e8c9df9e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=189401
@ -71,10 +71,10 @@ __FBSDID("$FreeBSD$");
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#define ACPI_PWR_FOR_SLEEP(x, y, z)
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#endif
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static uint32_t pci_mapbase(unsigned mapreg);
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static const char *pci_maptype(unsigned mapreg);
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static int pci_mapsize(unsigned testval);
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static int pci_maprange(unsigned mapreg);
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static pci_addr_t pci_mapbase(uint64_t mapreg);
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static const char *pci_maptype(uint64_t mapreg);
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static int pci_mapsize(uint64_t testval);
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static int pci_maprange(uint64_t mapreg);
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static void pci_fixancient(pcicfgregs *cfg);
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static int pci_porten(device_t pcib, int b, int s, int f);
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@ -316,8 +316,8 @@ pci_find_device(uint16_t vendor, uint16_t device)
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/* return base address of memory or port map */
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static uint32_t
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pci_mapbase(uint32_t mapreg)
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static pci_addr_t
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pci_mapbase(uint64_t mapreg)
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{
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if (PCI_BAR_MEM(mapreg))
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@ -329,7 +329,7 @@ pci_mapbase(uint32_t mapreg)
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/* return map type of memory or port map */
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static const char *
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pci_maptype(unsigned mapreg)
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pci_maptype(uint64_t mapreg)
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{
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if (PCI_BAR_IO(mapreg))
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@ -342,7 +342,7 @@ pci_maptype(unsigned mapreg)
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/* return log2 of map size decoded for memory or port map */
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static int
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pci_mapsize(uint32_t testval)
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pci_mapsize(uint64_t testval)
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{
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int ln2size;
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@ -361,7 +361,7 @@ pci_mapsize(uint32_t testval)
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/* return log2 of address range supported by map register */
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static int
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pci_maprange(unsigned mapreg)
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pci_maprange(uint64_t mapreg)
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{
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int ln2range = 0;
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@ -2279,8 +2279,7 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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int b, int s, int f, int reg, struct resource_list *rl, int force,
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int prefetch)
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{
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uint32_t map;
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pci_addr_t base;
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pci_addr_t base, map;
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pci_addr_t start, end, count;
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uint8_t ln2size;
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uint8_t ln2range;
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@ -2291,6 +2290,10 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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struct resource *res;
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map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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ln2range = pci_maprange(map);
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if (ln2range == 64)
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map |= (uint64_t)PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) <<
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32;
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/*
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* Disable decoding via the command register before
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@ -2308,9 +2311,16 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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*/
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
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testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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if (ln2range == 64) {
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg + 4, 0xffffffff, 4);
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testval |= (uint64_t)PCIB_READ_CONFIG(pcib, b, s, f, reg + 4,
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4) << 32;
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}
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/* Restore the BAR and command register. */
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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if (ln2range == 64)
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg + 4, map >> 32, 4);
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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if (PCI_BAR_MEM(map)) {
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@ -2320,7 +2330,6 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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} else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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base = pci_mapbase(map);
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barlen = ln2range == 64 ? 2 : 1;
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@ -2337,12 +2346,6 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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(type == SYS_RES_IOPORT && ln2size < 2))
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return (barlen);
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if (ln2range == 64)
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/*
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* Read the other half of a 64bit map register. We
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* assume that the size of the BAR is less than 2^32.
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*/
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base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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if (bootverbose) {
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printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
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reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
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@ -3421,7 +3424,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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struct resource *res;
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pci_addr_t map, testval;
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uint16_t cmd;
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int mapsize;
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int maprange, mapsize;
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/*
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* Weed out the bogons, and figure out how large the BAR/map
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@ -3432,6 +3435,9 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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*/
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res = NULL;
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map = pci_read_config(child, *rid, 4);
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maprange = pci_maprange(map);
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if (maprange == 64)
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map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
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/*
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* Disable decoding via the command register before
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@ -3445,8 +3451,11 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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/* Determine the BAR's length. */
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pci_write_config(child, *rid, 0xffffffff, 4);
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testval = pci_read_config(child, *rid, 4);
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if (pci_maprange(testval) == 64)
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map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
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if (maprange == 64) {
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pci_write_config(child, *rid + 4, 0xffffffff, 4);
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testval |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) <<
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32;
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}
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/*
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* Restore the original value of the BAR. We may have reprogrammed
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@ -3454,6 +3463,8 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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* we need the console device addressable.
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*/
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pci_write_config(child, *rid, map, 4);
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if (maprange == 64)
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pci_write_config(child, *rid + 4, map, 4);
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pci_write_config(child, PCIR_COMMAND, cmd, 2);
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/* Ignore a BAR with a base of 0. */
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@ -3520,7 +3531,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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count, *rid, type, rman_get_start(res));
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map = rman_get_start(res);
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pci_write_config(child, *rid, map, 4);
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if (pci_maprange(testval) == 64)
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if (maprange == 64)
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pci_write_config(child, *rid + 4, map >> 32, 4);
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out:;
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return (res);
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@ -132,7 +132,7 @@
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#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
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#define PCIM_BAR_MEM_64 4
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#define PCIM_BAR_MEM_PREFETCH 0x00000008
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#define PCIM_BAR_MEM_BASE 0xfffffff0
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#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL
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#define PCIM_BAR_IO_RESERVED 0x00000002
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#define PCIM_BAR_IO_BASE 0xfffffffc
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#define PCIR_CIS 0x28
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