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Replace generic ARM11 option with more specific

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support for ARM1136 and ARM1176

Submitted by:	Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from:	NetBSD
This commit is contained in:
Oleksandr Tymoshenko 2012-12-20 04:32:02 +00:00
parent b9a3b76662
commit c5f8f8946c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=244480
15 changed files with 456 additions and 60 deletions
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222
sys/arm/arm/cpufunc.c
View File

@ -974,18 +974,18 @@ struct cpu_functions fa526_cpufuncs = {
};
#endif /* CPU_FA526 || CPU_FA626TE */
#if defined(CPU_ARM11)
struct cpu_functions arm11_cpufuncs = {
#if defined(CPU_ARM1136)
struct cpu_functions arm1136_cpufuncs = {
/* CPU functions */
cpufunc_id, /* id */
arm11_drain_writebuf, /* cpwait */
cpufunc_nullop, /* cpwait */
/* MMU functions */
cpufunc_control, /* control */
cpufunc_domains, /* Domain */
arm11_setttb, /* Setttb */
arm11x6_setttb, /* Setttb */
cpufunc_faultstatus, /* Faultstatus */
cpufunc_faultaddress, /* Faultaddress */
@ -1000,30 +1000,30 @@ struct cpu_functions arm11_cpufuncs = {
/* Cache operations */
armv6_icache_sync_all, /* icache_sync_all */
armv6_icache_sync_range, /* icache_sync_range */
arm11x6_icache_sync_all, /* icache_sync_all */
arm11x6_icache_sync_range, /* icache_sync_range */
armv6_dcache_wbinv_all, /* dcache_wbinv_all */
arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
armv6_dcache_wbinv_range, /* dcache_wbinv_range */
armv6_dcache_inv_range, /* dcache_inv_range */
armv6_dcache_wb_range, /* dcache_wb_range */
armv6_idcache_wbinv_all, /* idcache_wbinv_all */
armv6_idcache_wbinv_range, /* idcache_wbinv_range */
arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */
arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */
(void*)cpufunc_nullop, /* l2cache_wbinv_all */
(void *)cpufunc_nullop, /* l2cache_wbinv_all */
(void *)cpufunc_nullop, /* l2cache_wbinv_range */
(void *)cpufunc_nullop, /* l2cache_inv_range */
(void *)cpufunc_nullop, /* l2cache_wb_range */
/* Other functions */
cpufunc_nullop, /* flush_prefetchbuf */
arm11x6_flush_prefetchbuf, /* flush_prefetchbuf */
arm11_drain_writebuf, /* drain_writebuf */
cpufunc_nullop, /* flush_brnchtgt_C */
(void *)cpufunc_nullop, /* flush_brnchtgt_E */
arm11_sleep, /* sleep */
arm11_sleep, /* sleep */
/* Soft functions */
@ -1032,9 +1032,70 @@ struct cpu_functions arm11_cpufuncs = {
arm11_context_switch, /* context_switch */
arm11_setup /* cpu setup */
arm11x6_setup /* cpu setup */
};
#endif /* CPU_ARM11 */
#endif /* CPU_ARM1136 */
#if defined(CPU_ARM1176)
struct cpu_functions arm1176_cpufuncs = {
/* CPU functions */
cpufunc_id, /* id */
cpufunc_nullop, /* cpwait */
/* MMU functions */
cpufunc_control, /* control */
cpufunc_domains, /* Domain */
arm11x6_setttb, /* Setttb */
cpufunc_faultstatus, /* Faultstatus */
cpufunc_faultaddress, /* Faultaddress */
/* TLB functions */
arm11_tlb_flushID, /* tlb_flushID */
arm11_tlb_flushID_SE, /* tlb_flushID_SE */
arm11_tlb_flushI, /* tlb_flushI */
arm11_tlb_flushI_SE, /* tlb_flushI_SE */
arm11_tlb_flushD, /* tlb_flushD */
arm11_tlb_flushD_SE, /* tlb_flushD_SE */
/* Cache operations */
arm11x6_icache_sync_all, /* icache_sync_all */
arm11x6_icache_sync_range, /* icache_sync_range */
arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
armv6_dcache_wbinv_range, /* dcache_wbinv_range */
armv6_dcache_inv_range, /* dcache_inv_range */
armv6_dcache_wb_range, /* dcache_wb_range */
arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */
arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */
(void *)cpufunc_nullop, /* l2cache_wbinv_all */
(void *)cpufunc_nullop, /* l2cache_wbinv_range */
(void *)cpufunc_nullop, /* l2cache_inv_range */
(void *)cpufunc_nullop, /* l2cache_wb_range */
/* Other functions */
arm11x6_flush_prefetchbuf, /* flush_prefetchbuf */
arm11_drain_writebuf, /* drain_writebuf */
cpufunc_nullop, /* flush_brnchtgt_C */
(void *)cpufunc_nullop, /* flush_brnchtgt_E */
arm11x6_sleep, /* sleep */
/* Soft functions */
cpufunc_null_fixup, /* dataabt_fixup */
cpufunc_null_fixup, /* prefetchabt_fixup */
arm11_context_switch, /* context_switch */
arm11x6_setup /* cpu setup */
};
#endif /*CPU_ARM1176 */
#if defined(CPU_CORTEXA)
struct cpu_functions cortexa_cpufuncs = {
@ -1111,8 +1172,8 @@ u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM11) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM1136) || \
defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
@ -1393,15 +1454,27 @@ set_cpufuncs()
goto out;
}
#endif /* CPU_ARM10 */
#ifdef CPU_ARM11
cpufuncs = arm11_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
pmap_pte_init_mmu_v6();
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
if (cputype == CPU_ID_ARM1136JS
|| cputype == CPU_ID_ARM1136JSR1
|| cputype == CPU_ID_ARM1176JZS) {
#ifdef CPU_ARM1136
if (cputype == CPU_ID_ARM1136JS
|| cputype == CPU_ID_ARM1136JSR1)
cpufuncs = arm1136_cpufuncs;
#endif
#ifdef CPU_ARM1176
if (cputype == CPU_ID_ARM1176JZS)
cpufuncs = arm1176_cpufuncs;
#endif
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
goto out;
#endif /* CPU_ARM11 */
pmap_pte_init_mmu_v6();
goto out;
}
#endif /* CPU_ARM1136 || CPU_ARM1176 */
#ifdef CPU_CORTEXA
if (cputype == CPU_ID_CORTEXA8R1 ||
cputype == CPU_ID_CORTEXA8R2 ||
@ -1962,7 +2035,7 @@ late_abort_fixup(arg)
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_ARM10) || defined(CPU_ARM1136) || defined(CPU_ARM1176) ||\
defined(CPU_FA526) || defined(CPU_FA626TE)
#define IGN 0
@ -2262,7 +2335,7 @@ arm10_setup(args)
}
#endif /* CPU_ARM9E || CPU_ARM10 */
#ifdef CPU_ARM11
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
struct cpu_option arm11_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@ -2273,41 +2346,100 @@ struct cpu_option arm11_options[] = {
};
void
arm11_setup(args)
char *args;
arm11x6_setup(char *args)
{
int cpuctrl;
int cpuctrl, cpuctrl_wax;
uint32_t auxctrl, auxctrl_wax;
uint32_t tmp, tmp2;
uint32_t sbz=0;
uint32_t cpuid;
cpuid = cpufunc_id();
cpuctrl =
CPU_CONTROL_MMU_ENABLE |
CPU_CONTROL_DC_ENABLE |
CPU_CONTROL_WBUF_ENABLE |
CPU_CONTROL_32BP_ENABLE |
CPU_CONTROL_32BD_ENABLE |
CPU_CONTROL_LABT_ENABLE |
CPU_CONTROL_SYST_ENABLE |
CPU_CONTROL_IC_ENABLE;
/*
* "write as existing" bits
* inverse of this is mask
*/
cpuctrl_wax =
(3 << 30) | /* SBZ */
(1 << 29) | /* FA */
(1 << 28) | /* TR */
(3 << 26) | /* SBZ */
(3 << 19) | /* SBZ */
(1 << 17); /* SBZ */
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
cpuctrl = CPU_CONTROL_MMU_ENABLE;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl |= CPU_CONTROL_DC_ENABLE;
cpuctrl |= (0xf << 3);
cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
cpuctrl |= CPU_CONTROL_SYST_ENABLE;
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
cpuctrl |= CPU_CONTROL_IC_ENABLE;
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
/* Make sure caches are clean. */
auxctrl = 0;
auxctrl_wax = ~0;
/*
* This options enables the workaround for the 364296 ARM1136
* r0pX errata (possible cache data corruption with
* hit-under-miss enabled). It sets the undocumented bit 31 in
* the auxiliary control register and the FI bit in the control
* register, thus disabling hit-under-miss without putting the
* processor into full low interrupt latency mode. ARM11MPCore
* is not affected.
*/
if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
cpuctrl |= CPU_CONTROL_FI_ENABLE;
auxctrl = ARM1136_AUXCTL_PFI;
auxctrl_wax = ~ARM1136_AUXCTL_PFI;
}
/*
* Enable an errata workaround
*/
if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1176JZS) { /* ARM1176JZSr0 */
auxctrl = ARM1176_AUXCTL_PHD;
auxctrl_wax = ~ARM1176_AUXCTL_PHD;
}
/* Clear out the cache */
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Now really make sure they are clean. */
__asm volatile ("mcr\tp15, 0, %0, c7, c7, 0" : : "r"(sbz));
/* Allow detection code to find the VFP if it's fitted. */
__asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
/* Set the control register */
ctrl = cpuctrl;
cpu_control(0xffffffff, cpuctrl);
cpu_control(~cpuctrl_wax, cpuctrl);
__asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t"
"and %1, %0, %2\n\t"
"orr %1, %1, %3\n\t"
"teq %0, %1\n\t"
"mcrne p15, 0, %1, c1, c0, 1\n\t"
: "=r"(tmp), "=r"(tmp2) :
"r"(auxctrl_wax), "r"(auxctrl));
/* And again. */
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
}
#endif /* CPU_ARM11 */
#endif /* CPU_ARM1136 || CPU_ARM1176 */
#ifdef CPU_MV_PJ4B
void

216
sys/arm/arm/cpufunc_asm_arm11x6.S Normal file
View File

@ -0,0 +1,216 @@
/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */
/*
* Copyright (c) 2007 Microsoft
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Microsoft
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Eben Upton
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
#else
/*
* Workaround for
*
* Erratum 411920 in ARM1136 (fixed in r1p4)
* Erratum 415045 in ARM1176 (fixed in r0p5?)
*
* - value of arg 'reg' Should Be Zero
*/
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
mov Rtmp1, #0; /* SBZ */ \
mrs Rtmp2, cpsr; \
cpsid ifa; \
mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
msr cpsr_cx, Rtmp2; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop; \
nop;
#endif
#if 1
#define Flush_D_cache(reg) \
mov reg, #0; /* SBZ */ \
mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
#else
#define Flush_D_cache(reg) \
1: mov reg, #0; /* SBZ */ \
mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
ands reg, reg, #01; /* Check if it is clean */ \
bne 1b; /* loop if not */ \
mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
#endif
ENTRY(arm11x6_setttb)
#ifdef PMAP_CACHE_VIVT
Flush_D_cache(r1)
Invalidate_I_cache(r1, r2)
#else
mov r1, #0
#endif
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
RET
ENTRY_NP(arm11x6_idcache_wbinv_all)
Flush_D_cache(r0)
Invalidate_I_cache(r0, r1)
RET
ENTRY_NP(arm11x6_dcache_wbinv_all)
Flush_D_cache(r0)
RET
ENTRY_NP(arm11x6_icache_sync_all)
Flush_D_cache(r0)
Invalidate_I_cache(r0, r1)
RET
ENTRY_NP(arm11x6_flush_prefetchbuf)
mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
RET
ENTRY_NP(arm11x6_icache_sync_range)
add r1, r1, r0
sub r1, r1, #1
/* Erratum ARM1136 371025, workaround #2 */
/* Erratum ARM1176 371367 */
mrs r2, cpsr /* save the CPSR */
cpsid ifa /* disable interrupts (irq,fiq,abort) */
mov r3, #0
mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
add r3, pc, #0x24
mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
msr cpsr_cx, r2 /* local_irq_restore */
nop
nop
nop
nop
nop
nop
nop
mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
ENTRY_NP(arm11x6_idcache_wbinv_range)
add r1, r1, r0
sub r1, r1, #1
/* Erratum ARM1136 371025, workaround #2 */
/* Erratum ARM1176 371367 */
mrs r2, cpsr /* save the CPSR */
cpsid ifa /* disable interrupts (irq,fiq,abort) */
mov r3, #0
mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
add r3, pc, #0x24
mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
msr cpsr_cx, r2 /* local_irq_restore */
nop
nop
nop
nop
nop
nop
nop
mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
/*
* Preload the cache before issuing the WFI by conditionally disabling the
* mcr intstructions the first time around the loop. Ensure the function is
* cacheline aligned.
*/
.arch armv6
.p2align 5
ENTRY_NP(arm11x6_sleep)
mov r0, #0
mov r1, #2
1:
subs r1, #1
nop
mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */
mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */
nop
nop
nop
bne 1b
RET

2
sys/arm/arm/elf_trampoline.c
View File

@ -63,7 +63,7 @@ void __startC(void);
#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
#elif defined(CPU_ARM10)
#define cpu_idcache_wbinv_all arm10_idcache_wbinv_all
#elif defined(CPU_ARM11)
#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \
defined(CPU_IXP12X0)

2
sys/arm/arm/identcpu.c
View File

@ -307,6 +307,8 @@ const struct cpuidtab cpuids[] = {
generic_steppings },
{ CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
generic_steppings },
{ CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S",
generic_steppings },
{ CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131",
generic_steppings },

8
sys/arm/arm/locore.S
View File

@ -168,7 +168,7 @@ Lunmapped:
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@ -178,7 +178,7 @@ Lunmapped:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
@ -363,7 +363,7 @@ Ltag:
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@ -375,7 +375,7 @@ Ltag:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)

1
sys/arm/broadcom/bcm2835/files.bcm2835
View File

@ -15,6 +15,7 @@ arm/broadcom/bcm2835/dwc_otg_brcm.c optional dwcotg
arm/arm/bus_space_generic.c standard
arm/arm/bus_space_asm_generic.S standard
arm/arm/cpufunc_asm_arm11.S standard
arm/arm/cpufunc_asm_arm11x6.S standard
arm/arm/cpufunc_asm_armv5.S standard
arm/arm/cpufunc_asm_armv6.S standard
arm/arm/irq_dispatch.S standard

2
sys/arm/conf/RPI-B
View File

@ -19,7 +19,7 @@
ident RPI-B
machine arm armv6
cpu CPU_ARM11
cpu CPU_ARM1176
files "../broadcom/bcm2835/files.bcm2835"
makeoptions MODULES_OVERRIDE=""

2
sys/arm/conf/VERSATILEPB
View File

@ -19,7 +19,7 @@
ident VERSATILEPB
machine arm armv6
cpu CPU_ARM11
cpu CPU_ARM1176
files "../versatile/files.versatile"
makeoptions MODULES_OVERRIDE=""

26
sys/arm/include/armreg.h
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@ -146,6 +146,7 @@
#define CPU_ID_ARM1026EJS 0x4106a260
#define CPU_ID_ARM1136JS 0x4107b360
#define CPU_ID_ARM1136JSR1 0x4117b360
#define CPU_ID_ARM1176JZS 0x410fb760
#define CPU_ID_CORTEXA8R1 0x411fc080
#define CPU_ID_CORTEXA8R2 0x412fc080
#define CPU_ID_CORTEXA8R3 0x413fc080
@ -284,11 +285,36 @@
#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
/* This is an undocumented flag
* used to work around a cache bug
* in r0 steppings. See errata
* 364296.
*/
/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */

7
sys/arm/include/cpuconf.h
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@ -54,7 +54,8 @@
defined(CPU_ARM8) + defined(CPU_ARM9) + \
defined(CPU_ARM9E) + \
defined(CPU_ARM10) + \
defined(CPU_ARM11) + \
defined(CPU_ARM1136) + \
defined(CPU_ARM1176) + \
defined(CPU_SA110) + defined(CPU_SA1100) + \
defined(CPU_SA1110) + \
defined(CPU_IXP12X0) + \
@ -89,7 +90,7 @@
#endif
#if !defined(ARM_ARCH_6)
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B)
#define ARM_ARCH_6 1
#else
#define ARM_ARCH_6 0
@ -149,7 +150,7 @@
#define ARM_MMU_GENERIC 0
#endif
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B)
#define ARM_MMU_V6 1
#else
#define ARM_MMU_V6 0

18
sys/arm/include/cpufunc.h
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@ -462,7 +462,8 @@ void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_wbinv_all (void);
#endif
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \
defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
void arm11_setttb (u_int);
void arm11_sleep (int);
@ -532,6 +533,21 @@ void armadaxp_idcache_wbinv_all (void);
void cortexa_setup (char *);
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void arm11x6_setttb (u_int);
void arm11x6_idcache_wbinv_all (void);
void arm11x6_dcache_wbinv_all (void);
void arm11x6_icache_sync_all (void);
void arm11x6_flush_prefetchbuf (void);
void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
void arm11x6_setup (char *string);
void arm11x6_sleep (int); /* no ref. for errata */
#endif
#if defined(CPU_ARM1136)
void arm1136_sleep_rev0 (int); /* for errata 336501 */
#endif
#if defined(CPU_ARM9E) || defined (CPU_ARM10)
void armv5_ec_setttb(u_int);

2
sys/arm/include/intr.h
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@ -52,7 +52,7 @@
#define NIRQ 64
#elif defined(CPU_CORTEXA)
#define NIRQ 128
#elif defined(CPU_ARM11)
#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
#define NIRQ 128
#elif defined(SOC_MV_ARMADAXP)
#define MAIN_IRQ_NUM 116

1
sys/arm/versatile/files.versatile
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@ -3,6 +3,7 @@
arm/arm/bus_space_asm_generic.S standard
arm/arm/bus_space_generic.c standard
arm/arm/cpufunc_asm_arm11.S standard
arm/arm/cpufunc_asm_arm11x6.S standard
arm/arm/cpufunc_asm_armv5.S standard
arm/arm/cpufunc_asm_armv6.S standard
arm/arm/irq_dispatch.S standard

4
sys/conf/files.arm
View File

@ -6,7 +6,7 @@ arm/arm/blockio.S standard
arm/arm/bootconfig.c standard
arm/arm/bus_space_asm_generic.S standard
arm/arm/busdma_machdep.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
arm/arm/busdma_machdep-v6.c optional cpu_arm11 | cpu_cortexa | cpu_mv_pj4b
arm/arm/busdma_machdep-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b
arm/arm/copystr.S standard
arm/arm/cpufunc.c standard
arm/arm/cpufunc_asm.S standard
@ -35,7 +35,7 @@ arm/arm/nexus.c standard
arm/arm/pl190.c optional pl190
arm/arm/pl310.c optional pl310
arm/arm/pmap.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
arm/arm/pmap-v6.c optional cpu_arm11 | cpu_cortexa | cpu_mv_pj4b
arm/arm/pmap-v6.c optional cpu_arm1136 | cpu_arm1176 | cpu_cortexa | cpu_mv_pj4b
arm/arm/sc_machdep.c optional sc
arm/arm/setcpsr.S standard
arm/arm/setstack.s standard

3
sys/conf/options.arm
View File

@ -11,7 +11,8 @@ ARM_WANT_TP_ADDRESS opt_global.h
COUNTS_PER_SEC opt_timer.h
CPU_ARM9 opt_global.h
CPU_ARM9E opt_global.h
CPU_ARM11 opt_global.h
CPU_ARM1136 opt_global.h
CPU_ARM1176 opt_global.h
CPU_CORTEXA opt_global.h
CPU_FA526 opt_global.h
CPU_FA626TE opt_global.h