Add 'sys/contrib/device-tree/' from commit '5ee353c36d3c9c7f63df7c7671875e73fba70958'
git-subtree-dir: sys/contrib/device-tree git-subtree-mainline:94611a8388git-subtree-split:5ee353c36d
This commit is contained in:
Emmanuel Vadot
commit
c66ec88fed
3
sys/contrib/device-tree/Bindings/.gitignore
vendored
Normal file
3
sys/contrib/device-tree/Bindings/.gitignore
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
*.example.dts
|
||||
processed-schema*.yaml
|
||||
42
sys/contrib/device-tree/Bindings/ABI.rst
Normal file
42
sys/contrib/device-tree/Bindings/ABI.rst
Normal file
@ -0,0 +1,42 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
===================
|
||||
Devicetree (DT) ABI
|
||||
===================
|
||||
|
||||
I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit
|
||||
summary document:
|
||||
|
||||
"That still leaves the question of, what does a stable binding look
|
||||
like? Certainly a stable binding means that a newer kernel will not
|
||||
break on an older device tree, but that doesn't mean the binding is
|
||||
frozen for all time. Grant said there are ways to change bindings that
|
||||
don't result in breakage. For instance, if a new property is added,
|
||||
then default to the previous behaviour if it is missing. If a binding
|
||||
truly needs an incompatible change, then change the compatible string
|
||||
at the same time. The driver can bind against both the old and the
|
||||
new. These guidelines aren't new, but they desperately need to be
|
||||
documented."
|
||||
|
||||
II. General binding rules
|
||||
|
||||
1) Maintainers, don't let perfect be the enemy of good. Don't hold up a
|
||||
binding because it isn't perfect.
|
||||
|
||||
2) Use specific compatible strings so that if we need to add a feature (DMA)
|
||||
in the future, we can create a new compatible string. See I.
|
||||
|
||||
3) Bindings can be augmented, but the driver shouldn't break when given
|
||||
the old binding. ie. add additional properties, but don't change the
|
||||
meaning of an existing property. For drivers, default to the original
|
||||
behaviour when a newly added property is missing.
|
||||
|
||||
4) Don't submit bindings for staging or unstable. That will be decided by
|
||||
the devicetree maintainers *after* discussion on the mailinglist.
|
||||
|
||||
III. Notes
|
||||
|
||||
1) This document is intended as a general familiarization with the process as
|
||||
decided at the 2013 Kernel Summit. When in doubt, the current word of the
|
||||
devicetree maintainers overrules this document. In that situation, a patch
|
||||
updating this document would be appreciated.
|
||||
73
sys/contrib/device-tree/Bindings/Makefile
Normal file
73
sys/contrib/device-tree/Bindings/Makefile
Normal file
@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
DT_DOC_CHECKER ?= dt-doc-validate
|
||||
DT_EXTRACT_EX ?= dt-extract-example
|
||||
DT_MK_SCHEMA ?= dt-mk-schema
|
||||
|
||||
DT_SCHEMA_MIN_VERSION = 2020.5
|
||||
|
||||
PHONY += check_dtschema_version
|
||||
check_dtschema_version:
|
||||
@{ echo $(DT_SCHEMA_MIN_VERSION); \
|
||||
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
|
||||
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
|
||||
|
||||
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
|
||||
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
|
||||
$(DT_EXTRACT_EX) $< > $@
|
||||
|
||||
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
|
||||
$(call if_changed,chk_binding)
|
||||
|
||||
# Use full schemas when checking %.example.dts
|
||||
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.yaml
|
||||
|
||||
find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
|
||||
-name 'processed-schema*' ! \
|
||||
-name '*.example.dt.yaml' \)
|
||||
|
||||
quiet_cmd_mk_schema = SCHEMA $@
|
||||
cmd_mk_schema = rm -f $@ ; \
|
||||
$(if $(DT_MK_SCHEMA_FLAGS), \
|
||||
echo $(real-prereqs), \
|
||||
$(find_cmd)) | \
|
||||
xargs $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) >> $@
|
||||
|
||||
DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
|
||||
|
||||
override DTC_FLAGS := \
|
||||
-Wno-avoid_unnecessary_addr_size \
|
||||
-Wno-graph_child_address \
|
||||
-Wno-interrupt_provider
|
||||
|
||||
$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE
|
||||
$(call if_changed,mk_schema)
|
||||
|
||||
ifeq ($(DT_SCHEMA_FILES),)
|
||||
|
||||
# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
|
||||
# Just copy processed-schema-examples.yaml
|
||||
|
||||
$(obj)/processed-schema.yaml: $(obj)/processed-schema-examples.yaml FORCE
|
||||
$(call if_changed,copy)
|
||||
|
||||
DT_SCHEMA_FILES = $(DT_DOCS)
|
||||
|
||||
else
|
||||
|
||||
# If DT_SCHEMA_FILES is specified, use it for processed-schema.yaml
|
||||
|
||||
$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u
|
||||
$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
|
||||
$(call if_changed,mk_schema)
|
||||
|
||||
endif
|
||||
|
||||
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
|
||||
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
|
||||
extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
|
||||
extra-$(CHECK_DTBS) += processed-schema.yaml
|
||||
|
||||
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
|
||||
# build artifacts here before they are processed by scripts/Makefile.clean
|
||||
clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
|
||||
-name '*.example.dt.yaml' \) -delete 2>/dev/null)
|
||||
17
sys/contrib/device-tree/Bindings/arc/archs-pct.txt
Normal file
17
sys/contrib/device-tree/Bindings/arc/archs-pct.txt
Normal file
@ -0,0 +1,17 @@
|
||||
* ARC HS Performance Counters
|
||||
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters.
|
||||
It also supports overflow interrupts.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain
|
||||
"snps,archs-pct"
|
||||
|
||||
Example:
|
||||
|
||||
pmu {
|
||||
compatible = "snps,archs-pct";
|
||||
};
|
||||
7
sys/contrib/device-tree/Bindings/arc/axs101.txt
Normal file
7
sys/contrib/device-tree/Bindings/arc/axs101.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "snps,axs101", "snps,arc-sdp";
|
||||
8
sys/contrib/device-tree/Bindings/arc/axs103.txt
Normal file
8
sys/contrib/device-tree/Bindings/arc/axs103.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
|
||||
HS38x cores.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "snps,axs103", "snps,arc-sdp";
|
||||
7
sys/contrib/device-tree/Bindings/arc/eznps.txt
Normal file
7
sys/contrib/device-tree/Bindings/arc/eznps.txt
Normal file
@ -0,0 +1,7 @@
|
||||
EZchip NPS Network Processor Platforms Device Tree Bindings
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
Appliance main board with NPS400 ASIC.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "ezchip,arc-nps";
|
||||
7
sys/contrib/device-tree/Bindings/arc/hsdk.txt
Normal file
7
sys/contrib/device-tree/Bindings/arc/hsdk.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
ARC HSDK Board with quad-core ARC HS38x4 in silicon.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "snps,hsdk";
|
||||
20
sys/contrib/device-tree/Bindings/arc/pct.txt
Normal file
20
sys/contrib/device-tree/Bindings/arc/pct.txt
Normal file
@ -0,0 +1,20 @@
|
||||
* ARC Performance Counters
|
||||
|
||||
The ARC700 can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters
|
||||
|
||||
Note that:
|
||||
* The ARC 700 PCT does not support interrupts; although HW events may be
|
||||
counted, the HW events themselves cannot serve as a trigger for a sample.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain
|
||||
"snps,arc700-pct"
|
||||
|
||||
Example:
|
||||
|
||||
pmu {
|
||||
compatible = "snps,arc700-pct";
|
||||
};
|
||||
38
sys/contrib/device-tree/Bindings/arm/actions.yaml
Normal file
38
sys/contrib/device-tree/Bindings/arm/actions.yaml
Normal file
@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/actions.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Actions Semi platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Andreas Färber <afaerber@suse.de>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
# The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
|
||||
- items:
|
||||
- enum:
|
||||
- allo,sparky # Allo.com Sparky
|
||||
- cubietech,cubieboard6 # Cubietech CubieBoard6
|
||||
- const: actions,s500
|
||||
- items:
|
||||
- enum:
|
||||
- lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B
|
||||
- const: lemaker,guitar
|
||||
- const: actions,s500
|
||||
|
||||
# The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
|
||||
- items:
|
||||
- enum:
|
||||
- cubietech,cubieboard7 # Cubietech CubieBoard7
|
||||
- const: actions,s700
|
||||
|
||||
# The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
|
||||
- items:
|
||||
- enum:
|
||||
- ucrobotics,bubblegum-96 # uCRobotics Bubblegum-96
|
||||
- const: actions,s900
|
||||
21
sys/contrib/device-tree/Bindings/arm/al,alpine.yaml
Normal file
21
sys/contrib/device-tree/Bindings/arm/al,alpine.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/al,alpine.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Annapurna Labs Alpine Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Tsahee Zidenberg <tsahee@annapurnalabs.com>
|
||||
- Antoine Tenart <antoine.tenart@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: al,alpine
|
||||
model:
|
||||
items:
|
||||
- const: "Annapurna Labs Alpine Dev Board"
|
||||
|
||||
...
|
||||
20
sys/contrib/device-tree/Bindings/arm/altera.yaml
Normal file
20
sys/contrib/device-tree/Bindings/arm/altera.yaml
Normal file
@ -0,0 +1,20 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/altera.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Altera's SoCFPGA platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-cyclone5
|
||||
- altr,socfpga-arria5
|
||||
- altr,socfpga-arria10
|
||||
- const: altr,socfpga
|
||||
...
|
||||
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Altera SOCFPGA Clock Manager
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
description: test
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: altr,clk-mgr
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clkmgr@ffd04000 {
|
||||
compatible = "altr,clk-mgr";
|
||||
reg = <0xffd04000 0x1000>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,12 @@
|
||||
Altera SOCFPGA SDRAM Controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should contain "altr,sdr-ctl" and "syscon".
|
||||
syscon is required by the Altera SOCFPGA SDRAM EDAC.
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
|
||||
Example:
|
||||
sdr: sdr@ffc25000 {
|
||||
compatible = "altr,sdr-ctl", "syscon";
|
||||
reg = <0xffc25000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,15 @@
|
||||
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
|
||||
The EDAC accesses a range of registers in the SDRAM controller.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
|
||||
- altr,sdr-syscon : phandle of the sdr module
|
||||
- interrupts : Should contain the SDRAM ECC IRQ in the
|
||||
appropriate format for the IRQ controller.
|
||||
|
||||
Example:
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac";
|
||||
altr,sdr-syscon = <&sdr>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
@ -0,0 +1,25 @@
|
||||
Altera SOCFPGA System Manager
|
||||
|
||||
Required properties:
|
||||
- compatible : "altr,sys-mgr"
|
||||
- reg : Should contain 1 register ranges(address and length)
|
||||
- cpu1-start-addr : CPU1 start address in hex.
|
||||
|
||||
Example:
|
||||
sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr";
|
||||
reg = <0xffd08000 0x1000>;
|
||||
cpu1-start-addr = <0xffd080c4>;
|
||||
};
|
||||
|
||||
ARM64 - Stratix10
|
||||
Required properties:
|
||||
- compatible : "altr,sys-mgr-s10"
|
||||
- reg : Should contain 1 register range(address and length)
|
||||
for system manager register.
|
||||
|
||||
Example:
|
||||
sysmgr@ffd12000 {
|
||||
compatible = "altr,sys-mgr-s10";
|
||||
reg = <0xffd12000 0x228>;
|
||||
};
|
||||
33
sys/contrib/device-tree/Bindings/arm/amazon,al.yaml
Normal file
33
sys/contrib/device-tree/Bindings/arm/amazon,al.yaml
Normal file
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/amazon,al.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Hanna Hawa <hhhawa@amazon.com>
|
||||
- Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
|
||||
- Ronen Krupnik <ronenk@amazon.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Boards with Alpine V1 SoC
|
||||
items:
|
||||
- const: al,alpine
|
||||
|
||||
- description: Boards with Alpine V2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- al,alpine-v2-evp
|
||||
- const: al,alpine-v2
|
||||
|
||||
- description: Boards with Alpine V3 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amazon,al-alpine-v3-evp
|
||||
- const: amazon,al-alpine-v3
|
||||
|
||||
...
|
||||
27
sys/contrib/device-tree/Bindings/arm/amlogic,scpi.txt
Normal file
27
sys/contrib/device-tree/Bindings/arm/amlogic,scpi.txt
Normal file
@ -0,0 +1,27 @@
|
||||
System Control and Power Interface (SCPI) Message Protocol
|
||||
(in addition to the standard binding in [0])
|
||||
----------------------------------------------------------
|
||||
Required properties
|
||||
|
||||
- compatible : should be "amlogic,meson-gxbb-scpi"
|
||||
|
||||
AMLOGIC SRAM and Shared Memory for SCPI
|
||||
------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "amlogic,meson-gxbb-sram"
|
||||
|
||||
Each sub-node represents the reserved area for SCPI.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
|
||||
memory on Amlogic GXBB SoC.
|
||||
|
||||
Sensor bindings for the sensors based on SCPI Message Protocol
|
||||
--------------------------------------------------------------
|
||||
SCPI provides an API to access the various sensors on the SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "amlogic,meson-gxbb-scpi-sensors".
|
||||
|
||||
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
|
||||
174
sys/contrib/device-tree/Bindings/arm/amlogic.yaml
Normal file
174
sys/contrib/device-tree/Bindings/arm/amlogic.yaml
Normal file
@ -0,0 +1,174 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/amlogic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic MesonX device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Kevin Hilman <khilman@baylibre.com>
|
||||
|
||||
description: |+
|
||||
Work in progress statement:
|
||||
|
||||
Device tree files and bindings applying to Amlogic SoCs and boards are
|
||||
considered "unstable". Any Amlogic device tree binding may change at
|
||||
any time. Be sure to use a device tree binary and a kernel image
|
||||
generated from the same source tree.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
|
||||
stable binding/ABI.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Boards with the Amlogic Meson6 SoC
|
||||
items:
|
||||
- enum:
|
||||
- geniatech,atv1200
|
||||
- const: amlogic,meson6
|
||||
|
||||
- description: Boards with the Amlogic Meson8 SoC
|
||||
items:
|
||||
- enum:
|
||||
- minix,neo-x8
|
||||
- const: amlogic,meson8
|
||||
|
||||
- description: Boards with the Amlogic Meson8m2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- tronsmart,mxiii-plus
|
||||
- const: amlogic,meson8m2
|
||||
|
||||
- description: Boards with the Amlogic Meson8b SoC
|
||||
items:
|
||||
- enum:
|
||||
- endless,ec100
|
||||
- hardkernel,odroid-c1
|
||||
- tronfy,mxq
|
||||
- const: amlogic,meson8b
|
||||
|
||||
- description: Boards with the Amlogic Meson GXBaby SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p200
|
||||
- amlogic,p201
|
||||
- friendlyarm,nanopi-k2
|
||||
- hardkernel,odroid-c2
|
||||
- nexbox,a95x
|
||||
- videostrong,kii-pro
|
||||
- wetek,hub
|
||||
- wetek,play2
|
||||
- const: amlogic,meson-gxbb
|
||||
|
||||
- description: Tronsmart Vega S95 devices
|
||||
items:
|
||||
- enum:
|
||||
- tronsmart,vega-s95-pro
|
||||
- tronsmart,vega-s95-meta
|
||||
- tronsmart,vega-s95-telos
|
||||
- const: tronsmart,vega-s95
|
||||
- const: amlogic,meson-gxbb
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S805X SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p241
|
||||
- libretech,aml-s805x-ac
|
||||
- const: amlogic,s805x
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S905W SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p281
|
||||
- oranth,tx3-mini
|
||||
- const: amlogic,s905w
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S905X SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p212
|
||||
- hwacom,amazetv
|
||||
- khadas,vim
|
||||
- libretech,aml-s905x-cc
|
||||
- nexbox,a95x
|
||||
- const: amlogic,s905x
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S905D SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,p230
|
||||
- amlogic,p231
|
||||
- libretech,aml-s905d-pc
|
||||
- phicomm,n1
|
||||
- smartlabs,sml5442tw
|
||||
- const: amlogic,s905d
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXM S912 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,q200
|
||||
- amlogic,q201
|
||||
- khadas,vim2
|
||||
- kingnovel,r-box-pro
|
||||
- libretech,aml-s912-pc
|
||||
- nexbox,a1
|
||||
- tronsmart,vega-s96
|
||||
- wetek,core2
|
||||
- const: amlogic,s912
|
||||
- const: amlogic,meson-gxm
|
||||
|
||||
- description: Boards with the Amlogic Meson AXG A113D SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,s400
|
||||
- const: amlogic,a113d
|
||||
- const: amlogic,meson-axg
|
||||
|
||||
- description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amediatech,x96-max
|
||||
- amlogic,u200
|
||||
- seirobotics,sei510
|
||||
- const: amlogic,g12a
|
||||
|
||||
- description: Boards with the Amlogic Meson G12B A311D SoC
|
||||
items:
|
||||
- enum:
|
||||
- khadas,vim3
|
||||
- const: amlogic,a311d
|
||||
- const: amlogic,g12b
|
||||
|
||||
- description: Boards with the Amlogic Meson G12B S922X SoC
|
||||
items:
|
||||
- enum:
|
||||
- azw,gtking
|
||||
- azw,gtking-pro
|
||||
- hardkernel,odroid-n2
|
||||
- khadas,vim3
|
||||
- ugoos,am6
|
||||
- const: amlogic,s922x
|
||||
- const: amlogic,g12b
|
||||
|
||||
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
|
||||
items:
|
||||
- enum:
|
||||
- seirobotics,sei610
|
||||
- khadas,vim3l
|
||||
- hardkernel,odroid-c4
|
||||
- const: amlogic,sm1
|
||||
|
||||
- description: Boards with the Amlogic Meson A1 A113L SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,ad401
|
||||
- const: amlogic,a1
|
||||
...
|
||||
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Amlogic Meson Firmware registers Interface
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
description: |
|
||||
The Meson SoCs have a register bank with status and data shared with the
|
||||
secure firmware.
|
||||
|
||||
# We need a select here so we don't match all nodes with 'syscon'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: amlogic,meson-gx-ao-secure
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: amlogic,meson-gx-ao-secure
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
amlogic,has-chip-id:
|
||||
description: |
|
||||
A firmware register encodes the SoC type, package and revision
|
||||
information on the Meson GX SoCs. If present, the interface gives
|
||||
the current SoC version.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ao-secure@140 {
|
||||
compatible = "amlogic,meson-gx-ao-secure", "syscon";
|
||||
reg = <0x140 0x140>;
|
||||
amlogic,has-chip-id;
|
||||
};
|
||||
20
sys/contrib/device-tree/Bindings/arm/amlogic/analog-top.txt
Normal file
20
sys/contrib/device-tree/Bindings/arm/amlogic/analog-top.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Amlogic Meson8 and Meson8b "analog top" registers:
|
||||
--------------------------------------------------
|
||||
|
||||
The analog top registers contain information about the so-called
|
||||
"metal revision" (which encodes the "minor version") of the SoC.
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the analog top registers
|
||||
- compatible: depending on the SoC this should be one of:
|
||||
- "amlogic,meson8-analog-top"
|
||||
- "amlogic,meson8b-analog-top"
|
||||
along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
analog_top: analog-top@81a8 {
|
||||
compatible = "amlogic,meson8-analog-top", "syscon";
|
||||
reg = <0x81a8 0x14>;
|
||||
};
|
||||
17
sys/contrib/device-tree/Bindings/arm/amlogic/assist.txt
Normal file
17
sys/contrib/device-tree/Bindings/arm/amlogic/assist.txt
Normal file
@ -0,0 +1,17 @@
|
||||
Amlogic Meson6/Meson8/Meson8b assist registers:
|
||||
-----------------------------------------------
|
||||
|
||||
The assist registers contain basic information about the SoC,
|
||||
for example the encoded SoC part number.
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the assist registers
|
||||
- compatible: should be "amlogic,meson-mx-assist" along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
assist: assist@7c00 {
|
||||
compatible = "amlogic,meson-mx-assist", "syscon";
|
||||
reg = <0x7c00 0x200>;
|
||||
};
|
||||
17
sys/contrib/device-tree/Bindings/arm/amlogic/bootrom.txt
Normal file
17
sys/contrib/device-tree/Bindings/arm/amlogic/bootrom.txt
Normal file
@ -0,0 +1,17 @@
|
||||
Amlogic Meson6/Meson8/Meson8b bootrom:
|
||||
--------------------------------------
|
||||
|
||||
The bootrom register area can be used to access SoC specific
|
||||
information, such as the "misc version".
|
||||
|
||||
Required properties:
|
||||
- reg: the register range of the bootrom registers
|
||||
- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bootrom: bootrom@d9040000 {
|
||||
compatible = "amlogic,meson-mx-bootrom", "syscon";
|
||||
reg = <0xd9040000 0x10000>;
|
||||
};
|
||||
18
sys/contrib/device-tree/Bindings/arm/amlogic/pmu.txt
Normal file
18
sys/contrib/device-tree/Bindings/arm/amlogic/pmu.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Amlogic Meson8 and Meson8b power-management-unit:
|
||||
-------------------------------------------------
|
||||
|
||||
The pmu is used to turn off and on different power domains of the SoCs
|
||||
This includes the power to the CPU cores.
|
||||
|
||||
Required node properties:
|
||||
- compatible value : depending on the SoC this should be one of:
|
||||
"amlogic,meson8-pmu"
|
||||
"amlogic,meson8b-pmu"
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Example:
|
||||
|
||||
pmu@c81000e4 {
|
||||
compatible = "amlogic,meson8b-pmu", "syscon";
|
||||
reg = <0xc81000e0 0x18>;
|
||||
};
|
||||
17
sys/contrib/device-tree/Bindings/arm/apm/scu.txt
Normal file
17
sys/contrib/device-tree/Bindings/arm/apm/scu.txt
Normal file
@ -0,0 +1,17 @@
|
||||
APM X-GENE SoC series SCU Registers
|
||||
|
||||
This system clock unit contain various register that control block resets,
|
||||
clock enable/disables, clock divisors and other deepsleep registers.
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be:
|
||||
- "apm,xgene-scu"
|
||||
second value must be always "syscon".
|
||||
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
Example :
|
||||
scu: system-clk-controller@17000000 {
|
||||
compatible = "apm,xgene-scu","syscon";
|
||||
reg = <0x0 0x17000000 0x0 0x400>;
|
||||
};
|
||||
86
sys/contrib/device-tree/Bindings/arm/arm,integrator.yaml
Normal file
86
sys/contrib/device-tree/Bindings/arm/arm,integrator.yaml
Normal file
@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Integrator Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
These were the first ARM platforms officially supported by ARM Ltd.
|
||||
They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
|
||||
so the system is modular and can host a variety of CPU tiles called
|
||||
"core tiles" and referred to in the device tree as "core modules".
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: ARM Integrator Application Platform, this board has a PCI
|
||||
host and several PCI slots, as well as a number of slots for logical
|
||||
expansion modules, it is referred to as an "ASIC Development
|
||||
Motherboard" and is extended with custom FPGA and is intended for
|
||||
rapid prototyping. See ARM DUI 0098B. This board can physically come
|
||||
pre-packaged in a PC Tower form factor called Integrator/PP1 or a
|
||||
special metal fixture called Integrator/PP2, see ARM DUI 0169A.
|
||||
items:
|
||||
- const: arm,integrator-ap
|
||||
- description: ARM Integrator Compact Platform (HBI-0086), this board has
|
||||
a compact form factor and mainly consists of the bare minimum
|
||||
peripherals to make use of the core module. See ARM DUI 0159B.
|
||||
items:
|
||||
- const: arm,integrator-cp
|
||||
- description: ARM Integrator Standard Development Board (SDB) Platform,
|
||||
this board is a PCI-based board conforming to the Microsoft SDB
|
||||
(HARP) specification. See ARM DUI 0099A.
|
||||
items:
|
||||
- const: arm,integrator-sp
|
||||
|
||||
core-module@10000000:
|
||||
type: object
|
||||
description: the root node in the Integrator platforms must contain
|
||||
a core module child node. They are always at physical address
|
||||
0x10000000 in all the Integrator variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,core-module-integrator
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^syscon@[0-9a-f]+$":
|
||||
description: All Integrator boards must provide a system controller as a
|
||||
node in the root of the device tree.
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,integrator-ap-syscon
|
||||
- arm,integrator-cp-syscon
|
||||
- arm,integrator-sp-syscon
|
||||
- const: syscon
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- core-module@10000000
|
||||
|
||||
...
|
||||
123
sys/contrib/device-tree/Bindings/arm/arm,realview.yaml
Normal file
123
sys/contrib/device-tree/Bindings/arm/arm,realview.yaml
Normal file
@ -0,0 +1,123 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM RealView Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
The ARM RealView series of reference designs were built to explore the ARM
|
||||
11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
|
||||
the earlier CPUs such as TrustZone and multicore (MPCore).
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: ARM RealView Emulation Baseboard (HBI-0140) was created
|
||||
as a generic platform to test different FPGA designs, and has
|
||||
pluggable CPU modules, see ARM DUI 0303E.
|
||||
items:
|
||||
- const: arm,realview-eb
|
||||
- description: ARM RealView Platform Baseboard for ARM1176JZF-S
|
||||
(HBI-0147) was created as a development board to test ARM TrustZone,
|
||||
CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
|
||||
items:
|
||||
- const: arm,realview-pb1176
|
||||
- description: ARM RealView Platform Baseboard for ARM 11 MPCore
|
||||
(HBI-0159, HBI-0175 and HBI-0176) was created to showcase
|
||||
multiprocessing with ARM11 using MPCore using symmetric
|
||||
multiprocessing (SMP). See ARM DUI 0351E.
|
||||
items:
|
||||
- const: arm,realview-pb11mp
|
||||
- description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
|
||||
HBI-0176 and HBI-0175) was the first reference platform for the
|
||||
Cortex CPU family, including a Cortex-A8 test chip.
|
||||
items:
|
||||
- const: arm,realview-pba8
|
||||
- description: ARM RealView Platform Baseboard Explore for Cortex-A9
|
||||
(HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
|
||||
CPU.
|
||||
items:
|
||||
- const: arm,realview-pbx
|
||||
|
||||
soc:
|
||||
description: All RealView boards must provide a soc node in the root of the
|
||||
device tree, representing the System-on-Chip since these test chips are
|
||||
rather complex.
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,realview-eb-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pb1176-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pb11mp-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pba8-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pbx-soc
|
||||
- const: simple-bus
|
||||
|
||||
patternProperties:
|
||||
"^.*syscon@[0-9a-f]+$":
|
||||
type: object
|
||||
description: All RealView boards must provide a syscon system controller
|
||||
node inside the soc node.
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,realview-eb11mp-revb-syscon
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-eb11mp-revc-syscon
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pb1176-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pb11mp-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pba8-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pbx-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- soc
|
||||
|
||||
...
|
||||
197
sys/contrib/device-tree/Bindings/arm/arm,scmi.txt
Normal file
197
sys/contrib/device-tree/Bindings/arm/arm,scmi.txt
Normal file
@ -0,0 +1,197 @@
|
||||
System Control and Management Interface (SCMI) Message Protocol
|
||||
----------------------------------------------------------
|
||||
|
||||
The SCMI is intended to allow agents such as OSPM to manage various functions
|
||||
that are provided by the hardware platform it is running on, including power
|
||||
and performance functions.
|
||||
|
||||
This binding is intended to define the interface the firmware implementing
|
||||
the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
|
||||
and Management Interface Platform Design Document")[0] provide for OSPM in
|
||||
the device tree.
|
||||
|
||||
Required properties:
|
||||
|
||||
The scmi node with the following properties shall be under the /firmware/ node.
|
||||
|
||||
- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
|
||||
- mboxes: List of phandle and mailbox channel specifiers. It should contain
|
||||
exactly one or two mailboxes, one for transmitting messages("tx")
|
||||
and another optional for receiving the notifications("rx") if
|
||||
supported.
|
||||
- shmem : List of phandle pointing to the shared memory(SHM) area as per
|
||||
generic mailbox client binding.
|
||||
- #address-cells : should be '1' if the device has sub-nodes, maps to
|
||||
protocol identifier for a given sub-node.
|
||||
- #size-cells : should be '0' as 'reg' property doesn't have any size
|
||||
associated with it.
|
||||
- arm,smc-id : SMC id required when using smc or hvc transports
|
||||
|
||||
Optional properties:
|
||||
|
||||
- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
|
||||
|
||||
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
|
||||
about the generic mailbox controller and client driver bindings.
|
||||
|
||||
The mailbox is the only permitted method of calling the SCMI firmware.
|
||||
Mailbox doorbell is used as a mechanism to alert the presence of a
|
||||
messages and/or notification.
|
||||
|
||||
Each protocol supported shall have a sub-node with corresponding compatible
|
||||
as described in the following sections. If the platform supports dedicated
|
||||
communication channel for a particular protocol, the 3 properties namely:
|
||||
mboxes, mbox-names and shmem shall be present in the sub-node corresponding
|
||||
to that protocol.
|
||||
|
||||
Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
|
||||
|
||||
Power domain bindings for the power domains based on SCMI Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding for the SCMI power domain providers uses the generic power
|
||||
domain binding[2].
|
||||
|
||||
Required properties:
|
||||
- #power-domain-cells : Should be 1. Contains the device or the power
|
||||
domain ID value used by SCMI commands.
|
||||
|
||||
Sensor bindings for the sensors based on SCMI Message Protocol
|
||||
--------------------------------------------------------------
|
||||
SCMI provides an API to access the various sensors on the SoC.
|
||||
|
||||
Required properties:
|
||||
- #thermal-sensor-cells: should be set to 1. This property follows the
|
||||
thermal device tree bindings[3].
|
||||
|
||||
Valid cell values are raw identifiers (Sensor ID)
|
||||
as used by the firmware. Refer to platform details
|
||||
for your implementation for the IDs to use.
|
||||
|
||||
Reset signal bindings for the reset domains based on SCMI Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding for the SCMI reset domain providers uses the generic reset
|
||||
signal binding[5].
|
||||
|
||||
Required properties:
|
||||
- #reset-cells : Should be 1. Contains the reset domain ID value used
|
||||
by SCMI commands.
|
||||
|
||||
SRAM and Shared Memory for SCMI
|
||||
-------------------------------
|
||||
|
||||
A small area of SRAM is reserved for SCMI communication between application
|
||||
processors and SCP.
|
||||
|
||||
The properties should follow the generic mmio-sram description found in [4]
|
||||
|
||||
Each sub-node represents the reserved area for SCMI.
|
||||
|
||||
Required sub-node properties:
|
||||
- reg : The base offset and size of the reserved area with the SRAM
|
||||
- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
|
||||
shared memory
|
||||
|
||||
[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
[3] Documentation/devicetree/bindings/thermal/thermal*.yaml
|
||||
[4] Documentation/devicetree/bindings/sram/sram.yaml
|
||||
[5] Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Example:
|
||||
|
||||
sram@50000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x50000000 0x0 0x10000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x10000>;
|
||||
|
||||
cpu_scp_lpri: scp-shmem@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-shmem@200 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
mailbox@40000000 {
|
||||
....
|
||||
#mbox-cells = <1>;
|
||||
reg = <0x0 0x40000000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
||||
...
|
||||
|
||||
scmi {
|
||||
compatible = "arm,scmi";
|
||||
mboxes = <&mailbox 0 &mailbox 1>;
|
||||
mbox-names = "tx", "rx";
|
||||
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_devpd: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_dvfs: protocol@13 {
|
||||
reg = <0x13>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_sensors0: protocol@15 {
|
||||
reg = <0x15>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_reset: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
...
|
||||
reg = <0 0>;
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
};
|
||||
|
||||
hdlcd@7ff60000 {
|
||||
...
|
||||
reg = <0 0x7ff60000 0 0x1000>;
|
||||
clocks = <&scmi_clk 4>;
|
||||
power-domains = <&scmi_devpd 1>;
|
||||
resets = <&scmi_reset 10>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <1000>;
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&scmi_sensors0 3>;
|
||||
...
|
||||
};
|
||||
};
|
||||
219
sys/contrib/device-tree/Bindings/arm/arm,scpi.txt
Normal file
219
sys/contrib/device-tree/Bindings/arm/arm,scpi.txt
Normal file
@ -0,0 +1,219 @@
|
||||
System Control and Power Interface (SCPI) Message Protocol
|
||||
----------------------------------------------------------
|
||||
|
||||
Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
|
||||
("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
|
||||
by Linux to initiate various system control and power operations.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be
|
||||
* "arm,scpi" : For implementations complying to SCPI v1.0 or above
|
||||
* "arm,scpi-pre-1.0" : For implementations complying to all
|
||||
unversioned releases prior to SCPI v1.0
|
||||
- mboxes: List of phandle and mailbox channel specifiers
|
||||
All the channels reserved by remote SCP firmware for use by
|
||||
SCPI message protocol should be specified in any order
|
||||
- shmem : List of phandle pointing to the shared memory(SHM) area between the
|
||||
processors using these mailboxes for IPC, one for each mailbox
|
||||
SHM can be any memory reserved for the purpose of this communication
|
||||
between the processors.
|
||||
|
||||
See Documentation/devicetree/bindings/mailbox/mailbox.txt
|
||||
for more details about the generic mailbox controller and
|
||||
client driver bindings.
|
||||
|
||||
Clock bindings for the clocks based on SCPI Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
Container Node
|
||||
==============
|
||||
Required properties:
|
||||
- compatible : should be "arm,scpi-clocks"
|
||||
All the clocks provided by SCP firmware via SCPI message
|
||||
protocol much be listed as sub-nodes under this node.
|
||||
|
||||
Sub-nodes
|
||||
=========
|
||||
Required properties:
|
||||
- compatible : shall include one of the following
|
||||
"arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
|
||||
These clocks don't provide an entire range of values between the
|
||||
limits but only discrete points within the range. The firmware
|
||||
provides the mapping for each such operating frequency and the
|
||||
index associated with it. The firmware also manages the
|
||||
voltage scaling appropriately with the clock scaling.
|
||||
"arm,scpi-variable-clocks" - all the clocks that are variable and provide full
|
||||
range within the specified range. The firmware provides the
|
||||
range of values within a specified range.
|
||||
|
||||
Other required properties for all clocks(all from common clock binding):
|
||||
- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
|
||||
- clock-output-names : shall be the corresponding names of the outputs.
|
||||
- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
|
||||
node. It can be non linear and hence provide the mapping of identifiers
|
||||
into the clock-output-names array.
|
||||
|
||||
SRAM and Shared Memory for SCPI
|
||||
-------------------------------
|
||||
|
||||
A small area of SRAM is reserved for SCPI communication between application
|
||||
processors and SCP.
|
||||
|
||||
The properties should follow the generic mmio-sram description found in [3]
|
||||
|
||||
Each sub-node represents the reserved area for SCPI.
|
||||
|
||||
Required sub-node properties:
|
||||
- reg : The base offset and size of the reserved area with the SRAM
|
||||
- compatible : should be "arm,scp-shmem" for Non-secure SRAM based
|
||||
shared memory
|
||||
|
||||
Sensor bindings for the sensors based on SCPI Message Protocol
|
||||
--------------------------------------------------------------
|
||||
SCPI provides an API to access the various sensors on the SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "arm,scpi-sensors".
|
||||
- #thermal-sensor-cells: should be set to 1. This property follows the
|
||||
thermal device tree bindings[2].
|
||||
|
||||
Valid cell values are raw identifiers (Sensor ID)
|
||||
as used by the firmware. Refer to platform details
|
||||
for your implementation for the IDs to use.
|
||||
|
||||
Power domain bindings for the power domains based on SCPI Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding uses the generic power domain binding[4].
|
||||
|
||||
PM domain providers
|
||||
===================
|
||||
|
||||
Required properties:
|
||||
- #power-domain-cells : Should be 1. Contains the device or the power
|
||||
domain ID value used by SCPI commands.
|
||||
- num-domains: Total number of power domains provided by SCPI. This is
|
||||
needed as the SCPI message protocol lacks a mechanism to
|
||||
query this information at runtime.
|
||||
|
||||
PM domain consumers
|
||||
===================
|
||||
|
||||
Required properties:
|
||||
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle.
|
||||
|
||||
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/thermal/thermal*.yaml
|
||||
[3] Documentation/devicetree/bindings/sram/sram.yaml
|
||||
[4] Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
|
||||
Example:
|
||||
|
||||
sram: sram@50000000 {
|
||||
compatible = "arm,juno-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0x50000000 0x0 0x10000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x10000>;
|
||||
|
||||
cpu_scp_lpri: scp-shmem@0 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-shmem@200 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
mailbox: mailbox0@40000000 {
|
||||
....
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
scpi_protocol: scpi@2e000000 {
|
||||
compatible = "arm,scpi";
|
||||
mboxes = <&mailbox 0 &mailbox 1>;
|
||||
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
||||
|
||||
clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: scpi_clocks@0 {
|
||||
compatible = "arm,scpi-dvfs-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <0>, <1>, <2>;
|
||||
clock-output-names = "atlclk", "aplclk","gpuclk";
|
||||
};
|
||||
scpi_clk: scpi_clocks@3 {
|
||||
compatible = "arm,scpi-variable-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <3>, <4>;
|
||||
clock-output-names = "pxlclk0", "pxlclk1";
|
||||
};
|
||||
};
|
||||
|
||||
scpi_sensors0: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
scpi_devpd: scpi-power-domains {
|
||||
compatible = "arm,scpi-power-domains";
|
||||
num-domains = <2>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
...
|
||||
reg = <0 0>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
hdlcd@7ff60000 {
|
||||
...
|
||||
reg = <0 0x7ff60000 0 0x1000>;
|
||||
clocks = <&scpi_clk 4>;
|
||||
power-domains = <&scpi_devpd 1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&scpi_sensors0 3>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
In the above example, the #clock-cells is set to 1 as required.
|
||||
scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
|
||||
1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
|
||||
and pxlclk1 with 3 and 4 as clock-indices.
|
||||
|
||||
The first consumer in the example is cpu@0 and it has '0' as the clock
|
||||
specifier which points to the first entry in the output clocks of
|
||||
scpi_dvfs i.e. "atlclk".
|
||||
|
||||
Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
|
||||
clock. '4' in the clock specifier here points to the second entry
|
||||
in the output clocks of scpi_clocks i.e. "pxlclk1"
|
||||
|
||||
The thermal-sensors property in the soc_thermal node uses the
|
||||
temperature sensor provided by SCP firmware to setup a thermal
|
||||
zone. The ID "3" is the sensor identifier for the temperature sensor
|
||||
as used by the firmware.
|
||||
|
||||
The num-domains property in scpi-power-domains domain specifies that
|
||||
SCPI provides 2 power domains. The hdlcd node uses the power domain with
|
||||
domain ID 1.
|
||||
71
sys/contrib/device-tree/Bindings/arm/arm,versatile.yaml
Normal file
71
sys/contrib/device-tree/Bindings/arm/arm,versatile.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
|
||||
with various pluggable interface boards, in essence the Versatile PB version
|
||||
is a superset of the Versatile AB version.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The ARM Versatile Application Baseboard (HBI-0118) is an
|
||||
evaluation board specifically for the ARM926EJ-S. It can be connected
|
||||
to an IB1 interface board for a touchscreen-type use case or an IB2
|
||||
for a candybar phone-type use case. See ARM DUI 0225D.
|
||||
items:
|
||||
- const: arm,versatile-ab
|
||||
- description: The ARM Versatile Platform Baseboard (HBI-0117) is an
|
||||
extension of the Versatile Application Baseboard that includes a
|
||||
PCI host controller. Like the sibling board, it is done specifically
|
||||
for ARM926EJ-S. See ARM DUI 0224B.
|
||||
items:
|
||||
- const: arm,versatile-pb
|
||||
|
||||
core-module@10000000:
|
||||
type: object
|
||||
description: the root node in the Versatile platforms must contain
|
||||
a core module child node. They are always at physical address
|
||||
0x10000000 in all the Versatile variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,core-module-versatile
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^syscon@[0-9a-f]+$":
|
||||
type: object
|
||||
description: When fitted with the IB2 Interface Board, the Versatile
|
||||
AB will present an optional system controller node which controls the
|
||||
extra peripherals on the interface board.
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,versatile-ib2-syscon
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- core-module@10000000
|
||||
|
||||
...
|
||||
219
sys/contrib/device-tree/Bindings/arm/arm,vexpress-juno.yaml
Normal file
219
sys/contrib/device-tree/Bindings/arm/arm,vexpress-juno.yaml
Normal file
@ -0,0 +1,219 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express and Juno Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Sudeep Holla <sudeep.holla@arm.com>
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
ARM's Versatile Express platform were built as reference designs for exploring
|
||||
multicore Cortex-A class systems. The Versatile Express family contains both
|
||||
32 bit (Aarch32) and 64 bit (Aarch64) systems.
|
||||
|
||||
The board consist of a motherboard and one or more daughterboards (tiles). The
|
||||
motherboard provides a set of peripherals. Processor and RAM "live" on the
|
||||
tiles.
|
||||
|
||||
The motherboard and each core tile should be described by a separate Device
|
||||
Tree source file, with the tile's description including the motherboard file
|
||||
using an include directive. As the motherboard can be initialized in one of
|
||||
two different configurations ("memory maps"), care must be taken to include
|
||||
the correct one.
|
||||
|
||||
When a new generation of boards were introduced under the name "Juno", these
|
||||
shared to many common characteristics with the Versatile Express that the
|
||||
"arm,vexpress" compatible was retained in the root node, and these are
|
||||
included in this binding schema as well.
|
||||
|
||||
The root node indicates the CPU SoC on the core tile, and this
|
||||
is a daughterboard to the main motherboard. The name used in the compatible
|
||||
string shall match the name given in the core tile's technical reference
|
||||
manual, followed by "arm,vexpress" as an additional compatible value. If
|
||||
further subvariants are released of the core tile, even more fine-granular
|
||||
compatible strings with up to three compatible strings are used.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
|
||||
in MPCore configuration in a test chip on the core tile. See ARM
|
||||
DUI 0448I. This was the first Versatile Express platform.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca9
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
|
||||
in a test chip on the core tile. It is intended to evaluate NEON, FPU
|
||||
and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca5s
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
|
||||
cores in a MPCore configuration in a test chip on the core tile. See
|
||||
ARM DUI 0604F.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
|
||||
A15 CPU cores in a test chip on the core tile. This is the first test
|
||||
chip called "TC1".
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15,tc1
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
|
||||
CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
|
||||
in a test chip on the core tile. See ARM DDI 0503I.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15_a7
|
||||
- const: arm,vexpress
|
||||
- description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
|
||||
cores in a test chip on the core tile. See ARM DDI 0498D.
|
||||
items:
|
||||
- const: arm,vexpress,v2f-1xv7,ca53x2
|
||||
- const: arm,vexpress,v2f-1xv7
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno "r0" (the first Juno board,
|
||||
V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
|
||||
AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
|
||||
cores in a big.LITTLE configuration. It also features the MALI T624
|
||||
GPU. See ARM document 100113_0000_07_en.
|
||||
items:
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r1 Development Platform
|
||||
(V2M-Juno r1) was introduced mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on
|
||||
the TLX connectors to join the coherency domain. Otherwise it is the
|
||||
same configuration as Juno r0. See ARM document 100122_0100_06_en.
|
||||
items:
|
||||
- const: arm,juno-r1
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r2 Development Platform
|
||||
(V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
|
||||
ARM document 100114_0200_04_en.
|
||||
items:
|
||||
- const: arm,juno-r2
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm AEMv8a Versatile Express Real-Time System Model
|
||||
(VE RTSM) is a programmers view of the Versatile Express with Arm
|
||||
v8A hardware. See ARM DUI 0575D.
|
||||
items:
|
||||
- const: arm,rtsm_ve,aemv8a
|
||||
- const: arm,vexpress
|
||||
- description: Arm FVP (Fixed Virtual Platform) base model revision C
|
||||
See ARM Document 100964_1190_00_en.
|
||||
items:
|
||||
- const: arm,fvp-base-revc
|
||||
- const: arm,vexpress
|
||||
- description: Arm Foundation model for Aarch64
|
||||
items:
|
||||
- const: arm,foundation-aarch64
|
||||
- const: arm,vexpress
|
||||
|
||||
arm,hbi:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: This indicates the ARM HBI (Hardware Board ID), this is
|
||||
ARM's unique board model ID, visible on the PCB's silkscreen.
|
||||
|
||||
arm,vexpress,site:
|
||||
description: As Versatile Express can be configured in number of physically
|
||||
different setups, the device tree should describe platform topology.
|
||||
For this reason the root node and main motherboard node must define this
|
||||
property, describing the physical location of the children nodes.
|
||||
0 means motherboard site, while 1 and 2 are daughterboard sites, and
|
||||
0xf means "sisterboard" which is the site containing the main CPU tile.
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
arm,vexpress,position:
|
||||
description: When daughterboards are stacked on one site, their position
|
||||
in the stack be be described this attribute.
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
arm,vexpress,dcc:
|
||||
description: When describing tiles consisting of more than one DCC, its
|
||||
number can be specified with this attribute.
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
patternProperties:
|
||||
"^bus@[0-9a-f]+$":
|
||||
description: Static Memory Bus (SMB) node, if this exists it describes
|
||||
the connection between the motherboard and any tiles. Sometimes the
|
||||
compatible is placed directly under this node, sometimes it is placed
|
||||
in a subnode named "motherboard". Sometimes the compatible includes
|
||||
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
|
||||
"simple-bus". If the compatible is placed in the "motherboard" node,
|
||||
it is stricter and always has two compatibles.
|
||||
type: object
|
||||
$ref: '/schemas/simple-bus.yaml'
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
- const: simple-bus
|
||||
motherboard:
|
||||
type: object
|
||||
description: The motherboard description provides a single "motherboard"
|
||||
node using 2 address cells corresponding to the Static Memory Bus
|
||||
used between the motherboard and the tile. The first cell defines the
|
||||
Chip Select (CS) line number, the second cell address offset within
|
||||
the CS. All interrupt lines between the motherboard and the tile
|
||||
are active high and are described using single cell.
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 2
|
||||
"#size-cells":
|
||||
const: 1
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
arm,v2m-memory-map:
|
||||
description: This describes the memory map type.
|
||||
$ref: '/schemas/types.yaml#/definitions/string'
|
||||
enum:
|
||||
- rs1
|
||||
- rs2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,vexpress,v2p-ca9
|
||||
- arm,vexpress,v2p-ca5s
|
||||
- arm,vexpress,v2p-ca15
|
||||
- arm,vexpress,v2p-ca15_a7
|
||||
- arm,vexpress,v2f-1xv7,ca53x2
|
||||
then:
|
||||
required:
|
||||
- arm,hbi
|
||||
|
||||
...
|
||||
27
sys/contrib/device-tree/Bindings/arm/arm-dsu-pmu.txt
Normal file
27
sys/contrib/device-tree/Bindings/arm/arm-dsu-pmu.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
|
||||
|
||||
ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
|
||||
with a shared L3 memory system, control logic and external interfaces to
|
||||
form a multicore cluster. The PMU enables to gather various statistics on
|
||||
the operations of the DSU. The PMU provides independent 32bit counters that
|
||||
can count any of the supported events, along with a 64bit cycle counter.
|
||||
The PMU is accessed via CPU system registers and has no MMIO component.
|
||||
|
||||
** DSU PMU required properties:
|
||||
|
||||
- compatible : should be one of :
|
||||
|
||||
"arm,dsu-pmu"
|
||||
|
||||
- interrupts : Exactly 1 SPI must be listed.
|
||||
|
||||
- cpus : List of phandles for the CPUs connected to this DSU instance.
|
||||
|
||||
|
||||
** Example:
|
||||
|
||||
dsu-pmu-0 {
|
||||
compatible = "arm,dsu-pmu";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cpus = <&cpu_0>, <&cpu_1>;
|
||||
};
|
||||
186
sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
Normal file
186
sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
Normal file
@ -0,0 +1,186 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel-at91.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel AT91 device tree bindings.
|
||||
|
||||
maintainers:
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Ludovic Desroches <ludovic.desroches@microchip.com>
|
||||
|
||||
description: |
|
||||
Boards with a SoC of the Atmel AT91 or SMART family shall have the following
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: atmel,at91rm9200
|
||||
- items:
|
||||
- enum:
|
||||
- olimex,sam9-l9260
|
||||
- enum:
|
||||
- atmel,at91sam9260
|
||||
- atmel,at91sam9261
|
||||
- atmel,at91sam9263
|
||||
- atmel,at91sam9g20
|
||||
- atmel,at91sam9g45
|
||||
- atmel,at91sam9n12
|
||||
- atmel,at91sam9rl
|
||||
- atmel,at91sam9xe
|
||||
- atmel,at91sam9x60
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
|
||||
- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
|
||||
- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
|
||||
- overkiz,smartkiz # Overkiz SmartKiz Board
|
||||
- const: atmel,at91sam9g25
|
||||
- const: atmel,at91sam9x5
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91sam9g15
|
||||
- atmel,at91sam9g25
|
||||
- atmel,at91sam9g35
|
||||
- atmel,at91sam9x25
|
||||
- atmel,at91sam9x35
|
||||
- const: atmel,at91sam9x5
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Overkiz kizbox3 board
|
||||
items:
|
||||
- const: overkiz,kizbox3-hs
|
||||
- const: atmel,sama5d27
|
||||
- const: atmel,sama5d2
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: Microchip SAMA5D27 WLSOM1
|
||||
items:
|
||||
- const: microchip,sama5d27-wlsom1
|
||||
- const: atmel,sama5d27
|
||||
- const: atmel,sama5d2
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
|
||||
items:
|
||||
- const: microchip,sama5d27-wlsom1-ek
|
||||
- const: microchip,sama5d27-wlsom1
|
||||
- const: atmel,sama5d27
|
||||
- const: atmel,sama5d2
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- const: atmel,sama5d27
|
||||
- const: atmel,sama5d2
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: Microchip SAMA5D2 Industrial Connectivity Platform
|
||||
items:
|
||||
- const: microchip,sama5d2-icp
|
||||
- const: atmel,sama5d27
|
||||
- const: atmel,sama5d2
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: SAM9X60-EK board
|
||||
items:
|
||||
- const: microchip,sam9x60ek
|
||||
- const: microchip,sam9x60
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Nattis v2 board with Natte v2 power board
|
||||
items:
|
||||
- const: axentia,nattis-2
|
||||
- const: axentia,natte-2
|
||||
- const: axentia,linea
|
||||
- const: atmel,sama5d31
|
||||
- const: atmel,sama5d3
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: TSE-850 v3 board
|
||||
items:
|
||||
- const: axentia,tse850v3
|
||||
- const: axentia,linea
|
||||
- const: atmel,sama5d31
|
||||
- const: atmel,sama5d3
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- const: axentia,linea
|
||||
- const: atmel,sama5d31
|
||||
- const: atmel,sama5d3
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: Overkiz kizbox2 board with two heads
|
||||
items:
|
||||
- const: overkiz,kizbox2-2
|
||||
- const: atmel,sama5d31
|
||||
- const: atmel,sama5d3
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,sama5d31
|
||||
- atmel,sama5d33
|
||||
- atmel,sama5d34
|
||||
- atmel,sama5d35
|
||||
- atmel,sama5d36
|
||||
- const: atmel,sama5d3
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,sama5d41
|
||||
- atmel,sama5d42
|
||||
- atmel,sama5d43
|
||||
- atmel,sama5d44
|
||||
- const: atmel,sama5d4
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,sams70j19
|
||||
- atmel,sams70j20
|
||||
- atmel,sams70j21
|
||||
- atmel,sams70n19
|
||||
- atmel,sams70n20
|
||||
- atmel,sams70n21
|
||||
- atmel,sams70q19
|
||||
- atmel,sams70q20
|
||||
- atmel,sams70q21
|
||||
- const: atmel,sams70
|
||||
- const: atmel,samv7
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,samv70j19
|
||||
- atmel,samv70j20
|
||||
- atmel,samv70n19
|
||||
- atmel,samv70n20
|
||||
- atmel,samv70q19
|
||||
- atmel,samv70q20
|
||||
- const: atmel,samv70
|
||||
- const: atmel,samv7
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,samv71j19
|
||||
- atmel,samv71j20
|
||||
- atmel,samv71j21
|
||||
- atmel,samv71n19
|
||||
- atmel,samv71n20
|
||||
- atmel,samv71n21
|
||||
- atmel,samv71q19
|
||||
- atmel,samv71q20
|
||||
- atmel,samv71q21
|
||||
- const: atmel,samv71
|
||||
- const: atmel,samv7
|
||||
|
||||
...
|
||||
193
sys/contrib/device-tree/Bindings/arm/atmel-sysregs.txt
Normal file
193
sys/contrib/device-tree/Bindings/arm/atmel-sysregs.txt
Normal file
@ -0,0 +1,193 @@
|
||||
Atmel system registers
|
||||
|
||||
Chipid required properties:
|
||||
- compatible: Should be "atmel,sama5d2-chipid"
|
||||
- reg : Should contain registers location and length
|
||||
|
||||
PIT Timer required properties:
|
||||
- compatible: Should be "atmel,at91sam9260-pit"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for the PIT which is the IRQ line
|
||||
shared across all System Controller members.
|
||||
|
||||
PIT64B Timer required properties:
|
||||
- compatible: Should be "microchip,sam9x60-pit64b"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for PIT64B timer
|
||||
- clocks: Should contain the available clock sources for PIT64B timer.
|
||||
|
||||
System Timer (ST) required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for the ST which is the IRQ line
|
||||
shared across all System Controller members.
|
||||
- clocks: phandle to input clock.
|
||||
Its subnodes can be:
|
||||
- watchdog: compatible should be "atmel,at91rm9200-wdt"
|
||||
|
||||
RSTC Reset Controller required properties:
|
||||
- compatible: Should be "atmel,<chip>-rstc".
|
||||
<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
|
||||
it also can be "microchip,sam9x60-rstc"
|
||||
- reg: Should contain registers location and length
|
||||
- clocks: phandle to input clock.
|
||||
|
||||
Example:
|
||||
|
||||
rstc@fffffd00 {
|
||||
compatible = "atmel,at91sam9260-rstc";
|
||||
reg = <0xfffffd00 0x10>;
|
||||
clocks = <&clk32k>;
|
||||
};
|
||||
|
||||
RAMC SDRAM/DDR Controller required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
|
||||
"atmel,at91sam9260-sdramc",
|
||||
"atmel,at91sam9g45-ddramc",
|
||||
"atmel,sama5d3-ddramc",
|
||||
"microchip,sam9x60-ddramc"
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Examples:
|
||||
|
||||
ramc0: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
SHDWC Shutdown Controller
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-shdwc".
|
||||
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
|
||||
- reg: Should contain registers location and length
|
||||
- clocks: phandle to input clock.
|
||||
|
||||
optional properties:
|
||||
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
|
||||
Supported values are: "none", "high", "low", "any".
|
||||
- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
|
||||
|
||||
optional at91sam9260 properties:
|
||||
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
||||
|
||||
optional at91sam9rl properties:
|
||||
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
|
||||
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
||||
|
||||
optional at91sam9x5 properties:
|
||||
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
|
||||
|
||||
Example:
|
||||
|
||||
shdwc@fffffd10 {
|
||||
compatible = "atmel,at91sam9260-shdwc";
|
||||
reg = <0xfffffd10 0x10>;
|
||||
clocks = <&clk32k>;
|
||||
};
|
||||
|
||||
SHDWC SAMA5D2-Compatible Shutdown Controller
|
||||
|
||||
1) shdwc node
|
||||
|
||||
required properties:
|
||||
- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
|
||||
- reg: should contain registers location and length
|
||||
- clocks: phandle to input clock.
|
||||
- #address-cells: should be one. The cell is the wake-up input index.
|
||||
- #size-cells: should be zero.
|
||||
|
||||
optional properties:
|
||||
|
||||
- debounce-delay-us: minimum wake-up inputs debouncer period in
|
||||
microseconds. It's usually a board-related property.
|
||||
- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
|
||||
|
||||
optional microchip,sam9x60-shdwc properties:
|
||||
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
||||
|
||||
The node contains child nodes for each wake-up input that the platform uses.
|
||||
|
||||
2) input nodes
|
||||
|
||||
Wake-up input nodes are usually described in the "board" part of the Device
|
||||
Tree. Note also that input 0 is linked to the wake-up pin and is frequently
|
||||
used.
|
||||
|
||||
Required properties:
|
||||
- reg: should contain the wake-up input index [0 - 15].
|
||||
|
||||
Optional properties:
|
||||
- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
|
||||
by the child, forces the wake-up of the core power supply on a high level.
|
||||
The default is to be active low.
|
||||
|
||||
Example:
|
||||
|
||||
On the SoC side:
|
||||
shdwc@f8048010 {
|
||||
compatible = "atmel,sama5d2-shdwc";
|
||||
reg = <0xf8048010 0x10>;
|
||||
clocks = <&clk32k>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
atmel,wakeup-rtc-timer;
|
||||
};
|
||||
|
||||
On the board side:
|
||||
shdwc@f8048010 {
|
||||
debounce-delay-us = <976>;
|
||||
|
||||
input@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
input@1 {
|
||||
reg = <1>;
|
||||
atmel,wakeup-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
Special Function Registers (SFR)
|
||||
|
||||
Special Function Registers (SFR) manage specific aspects of the integrated
|
||||
memory, bridge implementations, processor and other functionality not controlled
|
||||
elsewhere.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
|
||||
"atmel,<chip>-sfrbu", "syscon"
|
||||
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
|
||||
It also can be "microchip,sam9x60-sfr", "syscon".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
sfr@f0038000 {
|
||||
compatible = "atmel,sama5d3-sfr", "syscon";
|
||||
reg = <0xf0038000 0x60>;
|
||||
};
|
||||
|
||||
Security Module (SECUMOD)
|
||||
|
||||
The Security Module macrocell provides all necessary secure functions to avoid
|
||||
voltage, temperature, frequency and mechanical attacks on the chip. It also
|
||||
embeds secure memories that can be scrambled.
|
||||
|
||||
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
|
||||
Note that they maintain their voltage during Backup/Self-refresh.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-secumod", "syscon".
|
||||
<chip> can be "sama5d2".
|
||||
- reg: Should contain registers location and length
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
- #gpio-cells: There are 2. The pin number is the
|
||||
first, the second represents additional
|
||||
parameters such as GPIO_ACTIVE_HIGH/LOW.
|
||||
|
||||
|
||||
secumod@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
29
sys/contrib/device-tree/Bindings/arm/axis.txt
Normal file
29
sys/contrib/device-tree/Bindings/arm/axis.txt
Normal file
@ -0,0 +1,29 @@
|
||||
Axis Communications AB
|
||||
ARTPEC series SoC Device Tree Bindings
|
||||
|
||||
ARTPEC-6 ARM SoC
|
||||
================
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "axis,artpec6";
|
||||
|
||||
ARTPEC-6 System Controller
|
||||
--------------------------
|
||||
|
||||
The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
|
||||
and resets.
|
||||
|
||||
Required properties:
|
||||
- compatible: "axis,artpec6-syscon", "syscon"
|
||||
- reg: Address and length of the register bank.
|
||||
|
||||
Example:
|
||||
syscon {
|
||||
compatible = "axis,artpec6-syscon", "syscon";
|
||||
reg = <0xf8000000 0x48>;
|
||||
};
|
||||
|
||||
ARTPEC-6 Development board:
|
||||
---------------------------
|
||||
Required root node properties:
|
||||
- compatible = "axis,artpec6-dev-board", "axis,artpec6";
|
||||
19
sys/contrib/device-tree/Bindings/arm/axxia.yaml
Normal file
19
sys/contrib/device-tree/Bindings/arm/axxia.yaml
Normal file
@ -0,0 +1,19 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/axxia.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axxia AXM55xx device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Anders Berg <anders.berg@lsi.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: LSI AXM5516 Validation board (Amarillo)
|
||||
items:
|
||||
- const: lsi,axm5516-amarillo
|
||||
- const: lsi,axm5516
|
||||
|
||||
...
|
||||
54
sys/contrib/device-tree/Bindings/arm/bcm/bcm2835.yaml
Normal file
54
sys/contrib/device-tree/Bindings/arm/bcm/bcm2835.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM2711 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,4-model-b
|
||||
- const: brcm,bcm2711
|
||||
|
||||
- description: BCM2835 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,model-a
|
||||
- raspberrypi,model-a-plus
|
||||
- raspberrypi,model-b
|
||||
- raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5)
|
||||
- raspberrypi,model-b-rev2
|
||||
- raspberrypi,model-b-plus
|
||||
- raspberrypi,compute-module
|
||||
- raspberrypi,model-zero
|
||||
- raspberrypi,model-zero-w
|
||||
- const: brcm,bcm2835
|
||||
|
||||
- description: BCM2836 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,2-model-b
|
||||
- const: brcm,bcm2836
|
||||
|
||||
- description: BCM2837 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,3-model-a-plus
|
||||
- raspberrypi,3-model-b
|
||||
- raspberrypi,3-model-b-plus
|
||||
- raspberrypi,3-compute-module
|
||||
- raspberrypi,3-compute-module-lite
|
||||
- const: brcm,bcm2837
|
||||
|
||||
...
|
||||
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm11351.yaml
Normal file
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm11351.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM11351 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm28155-ap
|
||||
- const: brcm,bcm11351
|
||||
|
||||
...
|
||||
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm21664.yaml
Normal file
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm21664.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM21664 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm21664-garnet
|
||||
- const: brcm,bcm21664
|
||||
|
||||
...
|
||||
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm23550.yaml
Normal file
21
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm23550.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM23550 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm23550-sparrow
|
||||
- const: brcm,bcm23550
|
||||
|
||||
...
|
||||
88
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4708.yaml
Normal file
88
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4708.yaml
Normal file
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM4708 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
|
||||
on the iProc architecture (Northstar).
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
- Rafal Milecki <zajec5@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM4708 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac56u
|
||||
- asus,rt-ac68u
|
||||
- buffalo,wzr-1750dhp
|
||||
- linksys,ea6300-v1
|
||||
- linksys,ea6500-v2
|
||||
- luxul,xap-1510v1
|
||||
- luxul,xwc-1000
|
||||
- netgear,r6250v1
|
||||
- netgear,r6300v2
|
||||
- smartrg,sr400ac
|
||||
- brcm,bcm94708
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47081 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-n18u
|
||||
- buffalo,wzr-600dhp2
|
||||
- buffalo,wzr-900dhp
|
||||
- luxul,xap-1410v1
|
||||
- luxul,xwr-1200v1
|
||||
- tplink,archer-c5-v2
|
||||
- const: brcm,bcm47081
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM4709 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac87u
|
||||
- buffalo,wxr-1900dhp
|
||||
- linksys,ea9200
|
||||
- netgear,r7000
|
||||
- netgear,r8000
|
||||
- tplink,archer-c9-v1
|
||||
- brcm,bcm94709
|
||||
- const: brcm,bcm4709
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47094 based boards
|
||||
items:
|
||||
- enum:
|
||||
- dlink,dir-885l
|
||||
- linksys,panamera
|
||||
- luxul,abr-4500-v1
|
||||
- luxul,xap-1610-v1
|
||||
- luxul,xbr-4500-v1
|
||||
- luxul,xwc-2000-v1
|
||||
- luxul,xwr-3100v1
|
||||
- luxul,xwr-3150-v1
|
||||
- netgear,r8500
|
||||
- phicomm,k3
|
||||
- const: brcm,bcm47094
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM53012 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm953012er
|
||||
- brcm,bcm953012hr
|
||||
- brcm,bcm953012k
|
||||
- const: brcm,brcm53012
|
||||
- const: brcm,bcm4708
|
||||
...
|
||||
85
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm63138.txt
Normal file
85
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm63138.txt
Normal file
@ -0,0 +1,85 @@
|
||||
Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
|
||||
-----------------------------------------------------------
|
||||
|
||||
Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
|
||||
following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: should be "brcm,bcm63138"
|
||||
|
||||
An optional Boot lookup table Device Tree node is required for secondary CPU
|
||||
initialization as well as a 'resets' phandle to the correct PMB controller as
|
||||
defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
|
||||
'enable-method' property.
|
||||
|
||||
Required properties for the Boot lookup table node:
|
||||
- compatible: should be "brcm,bcm63138-bootlut"
|
||||
- reg: register base address and length for the Boot Lookup table
|
||||
|
||||
Optional properties for the primary CPU node:
|
||||
- enable-method: should be "brcm,bcm63138"
|
||||
|
||||
Optional properties for the secondary CPU node:
|
||||
- enable-method: should be "brcm,bcm63138"
|
||||
- resets: phandle to the relevant PMB controller, one integer indicating the internal
|
||||
bus number, and a second integer indicating the address of the CPU in the PMB
|
||||
internal bus number.
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cotex-a9";
|
||||
reg = <0>;
|
||||
...
|
||||
enable-method = "brcm,bcm63138";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
...
|
||||
enable-method = "brcm,bcm63138";
|
||||
resets = <&pmb0 4 1>;
|
||||
};
|
||||
};
|
||||
|
||||
bootlut: bootlut@8000 {
|
||||
compatible = "brcm,bcm63138-bootlut";
|
||||
reg = <0x8000 0x50>;
|
||||
};
|
||||
|
||||
=======
|
||||
reboot
|
||||
------
|
||||
Two nodes are required for software reboot: a timer node and a syscon-reboot node.
|
||||
|
||||
Timer node:
|
||||
|
||||
- compatible: Must be "brcm,bcm6328-timer", "syscon"
|
||||
- reg: Register base address and length
|
||||
|
||||
Syscon reboot node:
|
||||
|
||||
See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
|
||||
detailed list of properties, the two values defined below are specific to the
|
||||
BCM6328-style timer:
|
||||
|
||||
- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
|
||||
from the beginning of the TIMER block
|
||||
- mask: Should be 1 for the SoftRst bit.
|
||||
|
||||
Example:
|
||||
|
||||
timer: timer@80 {
|
||||
compatible = "brcm,bcm6328-timer", "syscon";
|
||||
reg = <0x80 0x3c>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&timer>;
|
||||
offset = <0x34>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
265
sys/contrib/device-tree/Bindings/arm/bcm/brcm,brcmstb.txt
Normal file
265
sys/contrib/device-tree/Bindings/arm/bcm/brcm,brcmstb.txt
Normal file
@ -0,0 +1,265 @@
|
||||
ARM Broadcom STB platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
|
||||
SoC shall have the following DT organization:
|
||||
|
||||
Required root node properties:
|
||||
- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
|
||||
|
||||
example:
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "Broadcom STB (bcm7445)";
|
||||
compatible = "brcm,bcm7445", "brcm,brcmstb";
|
||||
|
||||
Further, syscon nodes that map platform-specific registers used for general
|
||||
system control is required:
|
||||
|
||||
- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
|
||||
- compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
|
||||
"brcm,brcmstb-cpu-biu-ctrl",
|
||||
"syscon"
|
||||
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
|
||||
|
||||
cpu-biu-ctrl node
|
||||
-------------------
|
||||
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
|
||||
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
|
||||
complex to the different Memory Controller Ports (MCP), one per memory
|
||||
controller (MEMC). This BIU block offers a feature called Write Pairing which
|
||||
consists in collapsing two adjacent cache lines into a single (bursted) write
|
||||
transaction towards the memory controller (MEMC) to maximize write bandwidth.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,write-pairing:
|
||||
Boolean property, which when present indicates that the chip
|
||||
supports write-pairing.
|
||||
|
||||
example:
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x00 0xf0000000 0x1000000>;
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
};
|
||||
|
||||
hif_cpubiuctrl: syscon@3e2400 {
|
||||
compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
|
||||
reg = <0x3e2400 0x5b4>;
|
||||
brcm,write-pairing;
|
||||
};
|
||||
|
||||
hif_continuation: syscon@452000 {
|
||||
compatible = "brcm,bcm7445-hif-continuation", "syscon";
|
||||
reg = <0x452000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
Nodes that allow for support of SMP initialization and reboot are required:
|
||||
|
||||
smpboot
|
||||
-------
|
||||
Required properties:
|
||||
|
||||
- compatible
|
||||
The string "brcm,brcmstb-smpboot".
|
||||
|
||||
- syscon-cpu
|
||||
A phandle / integer array property which lets the BSP know the location
|
||||
of certain CPU power-on registers.
|
||||
|
||||
The layout of the property is as follows:
|
||||
o a phandle to the "hif_cpubiuctrl" syscon node
|
||||
o offset to the base CPU power zone register
|
||||
o offset to the base CPU reset register
|
||||
|
||||
- syscon-cont
|
||||
A phandle pointing to the syscon node which describes the CPU boot
|
||||
continuation registers.
|
||||
o a phandle to the "hif_continuation" syscon node
|
||||
|
||||
example:
|
||||
smpboot {
|
||||
compatible = "brcm,brcmstb-smpboot";
|
||||
syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
|
||||
syscon-cont = <&hif_continuation>;
|
||||
};
|
||||
|
||||
reboot
|
||||
-------
|
||||
Required properties
|
||||
|
||||
- compatible
|
||||
The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
|
||||
the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
|
||||
chips with the old SUN_TOP_CTRL interface.
|
||||
|
||||
- syscon
|
||||
A phandle / integer array that points to the syscon node which describes
|
||||
the general system reset registers.
|
||||
o a phandle to "sun_top_ctrl"
|
||||
o offset to the "reset source enable" register
|
||||
o offset to the "software master reset" register
|
||||
|
||||
example:
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
|
||||
|
||||
Power management
|
||||
----------------
|
||||
|
||||
For power management (particularly, S2/S3/S5 system suspend), the following SoC
|
||||
components are needed:
|
||||
|
||||
= Always-On control block (AON CTRL)
|
||||
|
||||
This hardware provides control registers for the "always-on" (even in low-power
|
||||
modes) hardware, such as the Power Management State Machine (PMSM).
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "brcm,brcmstb-aon-ctrl"
|
||||
- reg : the register start and length for the AON CTRL block
|
||||
|
||||
Example:
|
||||
|
||||
aon-ctrl@410000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x410000 0x400>;
|
||||
};
|
||||
|
||||
= Memory controllers
|
||||
|
||||
A Broadcom STB SoC typically has a number of independent memory controllers,
|
||||
each of which may have several associated hardware blocks, which are versioned
|
||||
independently (control registers, DDR PHYs, etc.). One might consider
|
||||
describing these controllers as a parent "memory controllers" block, which
|
||||
contains N sub-nodes (one for each controller in the system), each of which is
|
||||
associated with a number of hardware register resources (e.g., its PHY). See
|
||||
the example device tree snippet below.
|
||||
|
||||
== MEMC (MEMory Controller)
|
||||
|
||||
Represents a single memory controller instance.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
|
||||
|
||||
Should contain subnodes for any of the following relevant hardware resources:
|
||||
|
||||
== DDR PHY control
|
||||
|
||||
Control registers for this memory controller's DDR PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of these
|
||||
"brcm,brcmstb-ddr-phy-v71.1"
|
||||
"brcm,brcmstb-ddr-phy-v72.0"
|
||||
"brcm,brcmstb-ddr-phy-v225.1"
|
||||
"brcm,brcmstb-ddr-phy-v240.1"
|
||||
"brcm,brcmstb-ddr-phy-v240.2"
|
||||
|
||||
- reg : the DDR PHY register range
|
||||
|
||||
== DDR SHIMPHY
|
||||
|
||||
Control registers for this memory controller's DDR SHIMPHY.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
|
||||
- reg : the DDR SHIMPHY register range
|
||||
|
||||
== MEMC DDR control
|
||||
|
||||
Sequencer DRAM parameters and control registers. Used for Self-Refresh
|
||||
Power-Down (SRPD), among other things.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of these
|
||||
"brcm,brcmstb-memc-ddr-rev-b.2.1"
|
||||
"brcm,brcmstb-memc-ddr-rev-b.2.2"
|
||||
"brcm,brcmstb-memc-ddr-rev-b.2.3"
|
||||
"brcm,brcmstb-memc-ddr-rev-b.3.0"
|
||||
"brcm,brcmstb-memc-ddr-rev-b.3.1"
|
||||
"brcm,brcmstb-memc-ddr"
|
||||
- reg : the MEMC DDR register range
|
||||
|
||||
Example:
|
||||
|
||||
memory_controllers {
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
memc@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges;
|
||||
|
||||
ddr-phy@f1106000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy-v240.1";
|
||||
reg = <0xf1106000 0x21c>;
|
||||
};
|
||||
|
||||
shimphy@f1108000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
|
||||
reg = <0xf1108000 0xe4>;
|
||||
};
|
||||
|
||||
memc-ddr@f1102000 {
|
||||
reg = <0xf1102000 0x800>;
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
};
|
||||
};
|
||||
|
||||
memc@1 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges;
|
||||
|
||||
ddr-phy@f1186000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy-v240.1";
|
||||
reg = <0xf1186000 0x21c>;
|
||||
};
|
||||
|
||||
shimphy@f1188000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
|
||||
reg = <0xf1188000 0xe4>;
|
||||
};
|
||||
|
||||
memc-ddr@f1182000 {
|
||||
reg = <0xf1182000 0x800>;
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
};
|
||||
};
|
||||
|
||||
memc@2 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges;
|
||||
|
||||
ddr-phy@f1206000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy-v240.1";
|
||||
reg = <0xf1206000 0x21c>;
|
||||
};
|
||||
|
||||
shimphy@f1208000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
|
||||
reg = <0xf1208000 0xe4>;
|
||||
};
|
||||
|
||||
memc-ddr@f1202000 {
|
||||
reg = <0xf1202000 0x800>;
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
};
|
||||
};
|
||||
};
|
||||
29
sys/contrib/device-tree/Bindings/arm/bcm/brcm,cygnus.yaml
Normal file
29
sys/contrib/device-tree/Bindings/arm/bcm/brcm,cygnus.yaml
Normal file
@ -0,0 +1,29 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Cygnus device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm11300
|
||||
- brcm,bcm11320
|
||||
- brcm,bcm11350
|
||||
- brcm,bcm11360
|
||||
- brcm,bcm58300
|
||||
- brcm,bcm58302
|
||||
- brcm,bcm58303
|
||||
- brcm,bcm58305
|
||||
- const: brcm,cygnus
|
||||
|
||||
...
|
||||
28
sys/contrib/device-tree/Bindings/arm/bcm/brcm,hr2.yaml
Normal file
28
sys/contrib/device-tree/Bindings/arm/bcm/brcm,hr2.yaml
Normal file
@ -0,0 +1,28 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Hurricane 2 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
|
||||
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
|
||||
flash and a PCIe attached integrated switching engine.
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ubnt,unifi-switch8
|
||||
- const: brcm,bcm53342
|
||||
- const: brcm,hr2
|
||||
|
||||
...
|
||||
23
sys/contrib/device-tree/Bindings/arm/bcm/brcm,ns2.yaml
Normal file
23
sys/contrib/device-tree/Bindings/arm/bcm/brcm,ns2.yaml
Normal file
@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom North Star 2 (NS2) device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,ns2-svk
|
||||
- brcm,ns2-xmc
|
||||
- const: brcm,ns2
|
||||
|
||||
...
|
||||
36
sys/contrib/device-tree/Bindings/arm/bcm/brcm,nsp.yaml
Normal file
36
sys/contrib/device-tree/Bindings/arm/bcm/brcm,nsp.yaml
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Northstar Plus device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm58522
|
||||
- brcm,bcm58525
|
||||
- brcm,bcm58535
|
||||
- brcm,bcm58622
|
||||
- brcm,bcm58623
|
||||
- brcm,bcm58625
|
||||
- brcm,bcm88312
|
||||
- const: brcm,nsp
|
||||
|
||||
...
|
||||
24
sys/contrib/device-tree/Bindings/arm/bcm/brcm,stingray.yaml
Normal file
24
sys/contrib/device-tree/Bindings/arm/bcm/brcm,stingray.yaml
Normal file
@ -0,0 +1,24 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm958742k
|
||||
- brcm,bcm958742t
|
||||
- brcm,bcm958802a802x
|
||||
- const: brcm,stingray
|
||||
|
||||
...
|
||||
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Vulcan device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rrichter@marvell.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,vulcan-eval
|
||||
- cavium,thunderx2-cn9900
|
||||
- const: brcm,vulcan-soc
|
||||
|
||||
...
|
||||
@ -0,0 +1,14 @@
|
||||
Raspberry Pi VideoCore firmware driver
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "raspberrypi,bcm2835-firmware"
|
||||
- mboxes: Phandle to the firmware device's Mailbox.
|
||||
(See: ../mailbox/mailbox.txt for more information)
|
||||
|
||||
Example:
|
||||
|
||||
firmware {
|
||||
compatible = "raspberrypi,bcm2835-firmware";
|
||||
mboxes = <&mailbox>;
|
||||
};
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Raspberry Pi VideoCore firmware driver
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: raspberrypi,bcm2835-firmware
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: raspberrypi,bcm2835-firmware
|
||||
- const: simple-mfd
|
||||
|
||||
mboxes:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Phandle to the firmware device's Mailbox.
|
||||
(See: ../mailbox/mailbox.txt for more information)
|
||||
|
||||
clocks:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: raspberrypi,firmware-clocks
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The argument is the ID of the clocks contained by the
|
||||
firmware messages.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware {
|
||||
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
|
||||
mboxes = <&mailbox>;
|
||||
|
||||
firmware_clocks: clocks {
|
||||
compatible = "raspberrypi,firmware-clocks";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
18
sys/contrib/device-tree/Bindings/arm/bitmain.yaml
Normal file
18
sys/contrib/device-tree/Bindings/arm/bitmain.yaml
Normal file
@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Bitmain platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- bitmain,sophon-edge
|
||||
- const: bitmain,bm1880
|
||||
...
|
||||
22
sys/contrib/device-tree/Bindings/arm/calxeda.yaml
Normal file
22
sys/contrib/device-tree/Bindings/arm/calxeda.yaml
Normal file
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/calxeda.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Calxeda Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
description: |+
|
||||
Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
|
||||
or Cortex-A15 based ECX-2000 SOCs
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- calxeda,highbank
|
||||
- calxeda,ecx-2000
|
||||
49
sys/contrib/device-tree/Bindings/arm/calxeda/hb-sregs.yaml
Normal file
49
sys/contrib/device-tree/Bindings/arm/calxeda/hb-sregs.yaml
Normal file
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Calxeda Highbank system registers
|
||||
|
||||
description: |
|
||||
The Calxeda Highbank system has a block of MMIO registers controlling
|
||||
several generic system aspects. Those can be used to control some power
|
||||
management, they also contain some gate and PLL clocks.
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: calxeda,hb-sregs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sregs@fff3c000 {
|
||||
compatible = "calxeda,hb-sregs";
|
||||
reg = <0xfff3c000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
42
sys/contrib/device-tree/Bindings/arm/calxeda/l2ecc.yaml
Normal file
42
sys/contrib/device-tree/Bindings/arm/calxeda/l2ecc.yaml
Normal file
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Calxeda Highbank L2 cache ECC
|
||||
|
||||
description: |
|
||||
Binding for the Calxeda Highbank L2 cache controller ECC device.
|
||||
This does not cover the actual L2 cache controller control registers,
|
||||
but just the error reporting functionality.
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: "calxeda,hb-sregs-l2-ecc"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: single bit error interrupt
|
||||
- description: double bit error interrupt
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sregs@fff3c200 {
|
||||
compatible = "calxeda,hb-sregs-l2-ecc";
|
||||
reg = <0xfff3c200 0x100>;
|
||||
interrupts = <0 71 4>, <0 72 4>;
|
||||
};
|
||||
10
sys/contrib/device-tree/Bindings/arm/cavium-thunder.txt
Normal file
10
sys/contrib/device-tree/Bindings/arm/cavium-thunder.txt
Normal file
@ -0,0 +1,10 @@
|
||||
Cavium Thunder platform device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Boards with Cavium's Thunder SoC shall have following properties.
|
||||
|
||||
Root Node
|
||||
---------
|
||||
Required root node properties:
|
||||
|
||||
- compatible = "cavium,thunder-88xx";
|
||||
8
sys/contrib/device-tree/Bindings/arm/cavium-thunder2.txt
Normal file
8
sys/contrib/device-tree/Bindings/arm/cavium-thunder2.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Cavium ThunderX2 CN99XX platform tree bindings
|
||||
----------------------------------------------
|
||||
|
||||
Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
|
||||
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
|
||||
|
||||
These SoC uses the "cavium,thunder2" core which will be compatible
|
||||
with "brcm,vulcan".
|
||||
224
sys/contrib/device-tree/Bindings/arm/cci.txt
Normal file
224
sys/contrib/device-tree/Bindings/arm/cci.txt
Normal file
@ -0,0 +1,224 @@
|
||||
=======================================================
|
||||
ARM CCI cache coherent interconnect binding description
|
||||
=======================================================
|
||||
|
||||
ARM multi-cluster systems maintain intra-cluster coherency through a
|
||||
cache coherent interconnect (CCI) that is capable of monitoring bus
|
||||
transactions and manage coherency, TLB invalidations and memory barriers.
|
||||
|
||||
It allows snooping and distributed virtual memory message broadcast across
|
||||
clusters, through memory mapped interface, with a global control register
|
||||
space and multiple sets of interface control registers, one per slave
|
||||
interface.
|
||||
|
||||
* CCI interconnect node
|
||||
|
||||
Description: Describes a CCI cache coherent Interconnect component
|
||||
|
||||
Node name must be "cci".
|
||||
Node's parent must be the root node /, and the address space visible
|
||||
through the CCI interconnect is the same as the one seen from the
|
||||
root node (ie from CPUs perspective as per DT standard).
|
||||
Every CCI node has to define the following properties:
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must contain one of the following:
|
||||
"arm,cci-400"
|
||||
"arm,cci-500"
|
||||
"arm,cci-550"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: Integer cells. A register entry, expressed as a pair
|
||||
of cells, containing base and size.
|
||||
Definition: A standard property. Specifies base physical
|
||||
address of CCI control registers common to all
|
||||
interfaces.
|
||||
|
||||
- ranges:
|
||||
Usage: required
|
||||
Value type: Integer cells. An array of range entries, expressed
|
||||
as a tuple of cells, containing child address,
|
||||
parent address and the size of the region in the
|
||||
child address space.
|
||||
Definition: A standard property. Follow rules in the Devicetree
|
||||
Specification for hierarchical bus addressing. CCI
|
||||
interfaces addresses refer to the parent node
|
||||
addressing scheme to declare their register bases.
|
||||
|
||||
CCI interconnect node can define the following child nodes:
|
||||
|
||||
- CCI control interface nodes
|
||||
|
||||
Node name must be "slave-if".
|
||||
Parent node must be CCI interconnect node.
|
||||
|
||||
A CCI control interface node must contain the following
|
||||
properties:
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be set to
|
||||
"arm,cci-400-ctrl-if"
|
||||
|
||||
- interface-type:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be set to one of {"ace", "ace-lite"}
|
||||
depending on the interface type the node
|
||||
represents.
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: Integer cells. A register entry, expressed
|
||||
as a pair of cells, containing base and
|
||||
size.
|
||||
Definition: the base address and size of the
|
||||
corresponding interface programming
|
||||
registers.
|
||||
|
||||
- CCI PMU node
|
||||
|
||||
Parent node must be CCI interconnect node.
|
||||
|
||||
A CCI pmu node must contain the following properties:
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must contain one of:
|
||||
"arm,cci-400-pmu,r0"
|
||||
"arm,cci-400-pmu,r1"
|
||||
"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
|
||||
secure access to CCI registers
|
||||
"arm,cci-500-pmu,r0"
|
||||
"arm,cci-550-pmu,r0"
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: Integer cells. A register entry, expressed
|
||||
as a pair of cells, containing base and
|
||||
size.
|
||||
Definition: the base address and size of the
|
||||
corresponding interface programming
|
||||
registers.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: Integer cells. Array of interrupt specifier
|
||||
entries, as defined in
|
||||
../interrupt-controller/interrupts.txt.
|
||||
Definition: list of counter overflow interrupts, one per
|
||||
counter. The interrupts must be specified
|
||||
starting with the cycle counter overflow
|
||||
interrupt, followed by counter0 overflow
|
||||
interrupt, counter1 overflow interrupt,...
|
||||
,counterN overflow interrupt.
|
||||
|
||||
The CCI PMU has an interrupt signal for each
|
||||
counter. The number of interrupts must be
|
||||
equal to the number of counters.
|
||||
|
||||
* CCI interconnect bus masters
|
||||
|
||||
Description: masters in the device tree connected to a CCI port
|
||||
(inclusive of CPUs and their cpu nodes).
|
||||
|
||||
A CCI interconnect bus master node must contain the following
|
||||
properties:
|
||||
|
||||
- cci-control-port:
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: a phandle containing the CCI control interface node
|
||||
the master is connected to.
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
cci-control-port = <&cci_control1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
cci-control-port = <&cci_control1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
cci-control-port = <&cci_control2>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
cci-control-port = <&cci_control2>;
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
dma0: dma@3000000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
cci-control-port = <&cci_control0>;
|
||||
reg = <0x0 0x3000000 0x0 0x1000>;
|
||||
interrupts = <10>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
cci@2c090000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x2c090000 0 0x1000>;
|
||||
ranges = <0x0 0x0 0x2c090000 0x10000>;
|
||||
|
||||
cci_control0: slave-if@1000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace-lite";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control1: slave-if@4000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control2: slave-if@5000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
pmu@9000 {
|
||||
compatible = "arm,cci-400-pmu";
|
||||
reg = <0x9000 0x5000>;
|
||||
interrupts = <0 101 4>,
|
||||
<0 102 4>,
|
||||
<0 103 4>,
|
||||
<0 104 4>,
|
||||
<0 105 4>;
|
||||
};
|
||||
};
|
||||
|
||||
This CCI node corresponds to a CCI component whose control registers sits
|
||||
at address 0x000000002c090000.
|
||||
CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
|
||||
CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
|
||||
CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
|
||||
49
sys/contrib/device-tree/Bindings/arm/coresight-cpu-debug.txt
Normal file
49
sys/contrib/device-tree/Bindings/arm/coresight-cpu-debug.txt
Normal file
@ -0,0 +1,49 @@
|
||||
* CoreSight CPU Debug Component:
|
||||
|
||||
CoreSight CPU debug component are compliant with the ARMv8 architecture
|
||||
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
|
||||
external debug module is mainly used for two modes: self-hosted debug and
|
||||
external debug, and it can be accessed from mmio region from Coresight
|
||||
and eventually the debug module connects with CPU for debugging. And the
|
||||
debug module provides sample-based profiling extension, which can be used
|
||||
to sample CPU program counter, secure state and exception level, etc;
|
||||
usually every CPU has one dedicated debug module to be connected.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "arm,coresight-cpu-debug"; supplemented with
|
||||
"arm,primecell" since this driver is using the AMBA bus
|
||||
interface.
|
||||
|
||||
- reg : physical base address and length of the register set.
|
||||
|
||||
- clocks : the clock associated to this component.
|
||||
|
||||
- clock-names : the name of the clock referenced by the code. Since we are
|
||||
using the AMBA framework, the name of the clock providing
|
||||
the interconnect should be "apb_pclk" and the clock is
|
||||
mandatory. The interface between the debug logic and the
|
||||
processor core is clocked by the internal CPU clock, so it
|
||||
is enabled with CPU clock by default.
|
||||
|
||||
- cpu : the CPU phandle the debug module is affined to. Do not assume it
|
||||
to default to CPU0 if omitted.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- power-domains: a phandle to the debug power domain. We use "power-domains"
|
||||
binding to turn on the debug logic if it has own dedicated
|
||||
power domain and if necessary to use "cpuidle.off=1" or
|
||||
"nohlt" in the kernel command line or sysfs node to
|
||||
constrain idle states to ensure registers in the CPU power
|
||||
domain are accessible.
|
||||
|
||||
Example:
|
||||
|
||||
debug@f6590000 {
|
||||
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
||||
reg = <0 0xf6590000 0 0x1000>;
|
||||
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
330
sys/contrib/device-tree/Bindings/arm/coresight-cti.yaml
Normal file
330
sys/contrib/device-tree/Bindings/arm/coresight-cti.yaml
Normal file
@ -0,0 +1,330 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# Copyright 2019 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Coresight Cross Trigger Interface (CTI) device.
|
||||
|
||||
description: |
|
||||
The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
|
||||
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
|
||||
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
|
||||
The ECT components are not part of the trace generation data path and are thus
|
||||
not part of the CoreSight graph described in the general CoreSight bindings
|
||||
file coresight.txt.
|
||||
|
||||
The CTI component properties define the connections between the individual
|
||||
CTI and the components it is directly connected to, consisting of input and
|
||||
output hardware trigger signals. CTIs can have a maximum number of input and
|
||||
output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
|
||||
number is defined at design time, the maximum of each defined in the DEVID
|
||||
register.
|
||||
|
||||
CTIs are interconnected in a star topology via the CTM, using a number of
|
||||
programmable channels, usually 4, but again implementation defined and
|
||||
described in the DEVID register. The star topology is not required to be
|
||||
described in the bindings as the actual connections are software
|
||||
programmable.
|
||||
|
||||
In general the connections between CTI and components via the trigger signals
|
||||
are implementation defined, except when the CTI is connected to an ARM v8
|
||||
architecture core and optional ETM.
|
||||
|
||||
In this case the ARM v8 architecture defines the required signal connections
|
||||
between CTI and the CPU core and ETM if present. In the case of a v8
|
||||
architecturally connected CTI an additional compatible string is used to
|
||||
indicate this feature (arm,coresight-cti-v8-arch).
|
||||
|
||||
When CTI trigger connection information is unavailable then a minimal driver
|
||||
binding can be declared with no explicit trigger signals. This will result
|
||||
the driver detecting the maximum available triggers and channels from the
|
||||
DEVID register and make them all available for use as a single default
|
||||
connection. Any user / client application will require additional information
|
||||
on the connections between the CTI and other components for correct operation.
|
||||
This information might be found by enabling the Integration Test registers in
|
||||
the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
|
||||
configuration). These registers may be used to explore the trigger connections
|
||||
between CTI and other CoreSight components.
|
||||
|
||||
Certain triggers between CoreSight devices and the CTI have specific types
|
||||
and usages. These can be defined along with the signal indexes with the
|
||||
constants defined in <dt-bindings/arm/coresight-cti-dt.h>
|
||||
|
||||
For example a CTI connected to a core will usually have a DBGREQ signal. This
|
||||
is defined in the binding as type PE_EDBGREQ. These types will appear in an
|
||||
optional array alongside the signal indexes. Omitting types will default all
|
||||
signals to GEN_IO.
|
||||
|
||||
Note that some hardware trigger signals can be connected to non-CoreSight
|
||||
components (e.g. UART etc) depending on hardware implementation.
|
||||
|
||||
maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/primecell.yaml#
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,coresight-cti
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^cti(@[0-9a-f]+)$"
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,coresight-cti
|
||||
- const: arm,primecell
|
||||
- items:
|
||||
- const: arm,coresight-cti-v8-arch
|
||||
- const: arm,coresight-cti
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
cpu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Handle to cpu this device is associated with. This must appear in the
|
||||
base cti node if compatible string arm,coresight-cti-v8-arch is used,
|
||||
or may appear in a trig-conns child node when appropriate.
|
||||
|
||||
arm,cti-ctm-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Defines the CTM this CTI is connected to, in large systems with multiple
|
||||
separate CTI/CTM nets. Typically multi-socket systems where the CTM is
|
||||
propagated between sockets.
|
||||
|
||||
arm,cs-dev-assoc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
defines a phandle reference to an associated CoreSight trace device.
|
||||
When the associated trace device is enabled, then the respective CTI
|
||||
will be enabled. Use in a trig-conns node, or in CTI base node when
|
||||
compatible string arm,coresight-cti-v8-arch used. If the associated
|
||||
device has not been registered then the node name will be stored as
|
||||
the connection name for later resolution. If the associated device is
|
||||
not a CoreSight device or not registered then the node name will remain
|
||||
the connection name and automatic enabling will not occur.
|
||||
|
||||
# size cells and address cells required if trig-conns node present.
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
'^trig-conns@([0-9]+)$':
|
||||
type: object
|
||||
description:
|
||||
A trigger connections child node which describes the trigger signals
|
||||
between this CTI and another hardware device. This device may be a CPU,
|
||||
CoreSight device, any other hardware device or simple external IO lines.
|
||||
The connection may have both input and output triggers, or only one or the
|
||||
other.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,trig-in-sigs:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger in signal numbers in use by a trig-conns node.
|
||||
|
||||
arm,trig-in-types:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of constants representing the types for the CTI trigger in
|
||||
signals. Types in this array match to the corresponding signal in the
|
||||
arm,trig-in-sigs array. If the -types array is smaller, or omitted
|
||||
completely, then the types will default to GEN_IO.
|
||||
|
||||
arm,trig-out-sigs:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger out signal numbers in use by a trig-conns node.
|
||||
|
||||
arm,trig-out-types:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of constants representing the types for the CTI trigger out
|
||||
signals. Types in this array match to the corresponding signal
|
||||
in the arm,trig-out-sigs array. If the "-types" array is smaller,
|
||||
or omitted completely, then the types will default to GEN_IO.
|
||||
|
||||
arm,trig-filters:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger out signals that will be blocked from becoming
|
||||
active, unless filtering is disabled on the driver.
|
||||
|
||||
arm,trig-conn-name:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
Defines a connection name that will be displayed, if the cpu or
|
||||
arm,cs-dev-assoc properties are not being used in this connection.
|
||||
Principle use for CTI that are connected to non-CoreSight devices, or
|
||||
external IO.
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- arm,trig-in-sigs
|
||||
- required:
|
||||
- arm,trig-out-sigs
|
||||
oneOf:
|
||||
- required:
|
||||
- arm,trig-conn-name
|
||||
- required:
|
||||
- cpu
|
||||
- required:
|
||||
- arm,cs-dev-assoc
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,coresight-cti-v8-arch
|
||||
|
||||
then:
|
||||
required:
|
||||
- cpu
|
||||
|
||||
examples:
|
||||
# minimum CTI definition. DEVID register used to set number of triggers.
|
||||
- |
|
||||
cti@20020000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x20020000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
# v8 architecturally defined CTI - CPU + ETM connections generated by the
|
||||
# driver according to the v8 architecture specification.
|
||||
- |
|
||||
cti@859000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0x859000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&CPU1>;
|
||||
arm,cs-dev-assoc = <&etm1>;
|
||||
};
|
||||
# Implementation defined CTI - CPU + ETM connections explicitly defined..
|
||||
# Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
|
||||
# #size-cells and #address-cells are required if trig-conns@ nodes present.
|
||||
- |
|
||||
#include <dt-bindings/arm/coresight-cti-dt.h>
|
||||
|
||||
cti@858000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x858000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
arm,cti-ctm-id = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs = <4 5 6 7>;
|
||||
arm,trig-in-types = <ETM_EXTOUT
|
||||
ETM_EXTOUT
|
||||
ETM_EXTOUT
|
||||
ETM_EXTOUT>;
|
||||
arm,trig-out-sigs = <4 5 6 7>;
|
||||
arm,trig-out-types = <ETM_EXTIN
|
||||
ETM_EXTIN
|
||||
ETM_EXTIN
|
||||
ETM_EXTIN>;
|
||||
arm,cs-dev-assoc = <&etm0>;
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
cpu = <&CPU0>;
|
||||
arm,trig-in-sigs = <0 1>;
|
||||
arm,trig-in-types = <PE_DBGTRIGGER
|
||||
PE_PMUIRQ>;
|
||||
arm,trig-out-sigs=<0 1 2 >;
|
||||
arm,trig-out-types = <PE_EDBGREQ
|
||||
PE_DBGRESTART
|
||||
PE_CTIIRQ>;
|
||||
|
||||
arm,trig-filters = <0>;
|
||||
};
|
||||
};
|
||||
# Implementation defined CTI - non CoreSight component connections.
|
||||
- |
|
||||
cti@20110000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x20110000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs=<0>;
|
||||
arm,trig-in-types=<GEN_INTREQ>;
|
||||
arm,trig-out-sigs=<0>;
|
||||
arm,trig-out-types=<GEN_HALTREQ>;
|
||||
arm,trig-conn-name = "sys_profiler";
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
arm,trig-out-sigs=<2 3>;
|
||||
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "watchdog";
|
||||
};
|
||||
|
||||
trig-conns@2 {
|
||||
reg = <2>;
|
||||
arm,trig-in-sigs=<1 6>;
|
||||
arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "g_counter";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
394
sys/contrib/device-tree/Bindings/arm/coresight.txt
Normal file
394
sys/contrib/device-tree/Bindings/arm/coresight.txt
Normal file
@ -0,0 +1,394 @@
|
||||
* CoreSight Components:
|
||||
|
||||
CoreSight components are compliant with the ARM CoreSight architecture
|
||||
specification and can be connected in various topologies to suit a particular
|
||||
SoCs tracing needs. These trace components can generally be classified as
|
||||
sinks, links and sources. Trace data produced by one or more sources flows
|
||||
through the intermediate links connecting the source to the currently selected
|
||||
sink. Each CoreSight component device should use these properties to describe
|
||||
its hardware characteristcs.
|
||||
|
||||
* Required properties for all components *except* non-configurable replicators
|
||||
and non-configurable funnels:
|
||||
|
||||
* compatible: These have to be supplemented with "arm,primecell" as
|
||||
drivers are using the AMBA bus interface. Possible values include:
|
||||
- Embedded Trace Buffer (version 1.0):
|
||||
"arm,coresight-etb10", "arm,primecell";
|
||||
|
||||
- Trace Port Interface Unit:
|
||||
"arm,coresight-tpiu", "arm,primecell";
|
||||
|
||||
- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
|
||||
Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
|
||||
configuration. The configuration mode (ETB, ETF, ETR) is
|
||||
discovered at boot time when the device is probed.
|
||||
"arm,coresight-tmc", "arm,primecell";
|
||||
|
||||
- Trace Programmable Funnel:
|
||||
"arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
|
||||
backward compatibility and will be removed)
|
||||
|
||||
- Embedded Trace Macrocell (version 3.x) and
|
||||
Program Flow Trace Macrocell:
|
||||
"arm,coresight-etm3x", "arm,primecell";
|
||||
|
||||
- Embedded Trace Macrocell (version 4.x):
|
||||
"arm,coresight-etm4x", "arm,primecell";
|
||||
|
||||
- Coresight programmable Replicator :
|
||||
"arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
|
||||
- System Trace Macrocell:
|
||||
"arm,coresight-stm", "arm,primecell"; [1]
|
||||
- Coresight Address Translation Unit (CATU)
|
||||
"arm,coresight-catu", "arm,primecell";
|
||||
|
||||
- Coresight Cross Trigger Interface (CTI):
|
||||
"arm,coresight-cti", "arm,primecell";
|
||||
See coresight-cti.yaml for full CTI definitions.
|
||||
|
||||
* reg: physical base address and length of the register
|
||||
set(s) of the component.
|
||||
|
||||
* clocks: the clocks associated to this component.
|
||||
|
||||
* clock-names: the name of the clocks referenced by the code.
|
||||
Since we are using the AMBA framework, the name of the clock
|
||||
providing the interconnect should be "apb_pclk", and some
|
||||
coresight blocks also have an additional clock "atclk", which
|
||||
clocks the core of that coresight component. The latter clock
|
||||
is optional.
|
||||
|
||||
* port or ports: see "Graph bindings for Coresight" below.
|
||||
|
||||
* Additional required property for Embedded Trace Macrocell (version 3.x and
|
||||
version 4.x):
|
||||
* cpu: the cpu phandle this ETM/PTM is affined to. Do not
|
||||
assume it to default to CPU0 if omitted.
|
||||
|
||||
* Additional required properties for System Trace Macrocells (STM):
|
||||
* reg: along with the physical base address and length of the register
|
||||
set as described above, another entry is required to describe the
|
||||
mapping of the extended stimulus port area.
|
||||
|
||||
* reg-names: the only acceptable values are "stm-base" and
|
||||
"stm-stimulus-base", each corresponding to the areas defined in "reg".
|
||||
|
||||
* Required properties for Coresight Cross Trigger Interface (CTI)
|
||||
See coresight-cti.yaml for full CTI definitions.
|
||||
|
||||
* Required properties for devices that don't show up on the AMBA bus, such as
|
||||
non-configurable replicators and non-configurable funnels:
|
||||
|
||||
* compatible: Currently supported value is (note the absence of the
|
||||
AMBA markee):
|
||||
- Coresight Non-configurable Replicator:
|
||||
"arm,coresight-static-replicator";
|
||||
"arm,coresight-replicator"; (OBSOLETE. For backward
|
||||
compatibility and will be removed)
|
||||
|
||||
- Coresight Non-configurable Funnel:
|
||||
"arm,coresight-static-funnel";
|
||||
|
||||
* port or ports: see "Graph bindings for Coresight" below.
|
||||
|
||||
* Optional properties for all components:
|
||||
|
||||
* arm,coresight-loses-context-with-cpu : boolean. Indicates that the
|
||||
hardware will lose register context on CPU power down (e.g. CPUIdle).
|
||||
An example of where this may be needed are systems which contain a
|
||||
coresight component and CPU in the same power domain. When the CPU
|
||||
powers down the coresight component also powers down and loses its
|
||||
context. This property is currently only used for the ETM 4.x driver.
|
||||
|
||||
* Optional properties for ETM/PTMs:
|
||||
|
||||
* arm,cp14: must be present if the system accesses ETM/PTM management
|
||||
registers via co-processor 14.
|
||||
|
||||
* qcom,skip-power-up: boolean. Indicates that an implementation can
|
||||
skip powering up the trace unit. TRCPDCR.PU does not have to be set
|
||||
on Qualcomm Technologies Inc. systems since ETMs are in the same power
|
||||
domain as their CPU cores. This property is required to identify such
|
||||
systems with hardware errata where the CPU watchdog counter is stopped
|
||||
when TRCPDCR.PU is set.
|
||||
|
||||
* Optional property for TMC:
|
||||
|
||||
* arm,buffer-size: size of contiguous buffer space for TMC ETR
|
||||
(embedded trace router). This property is obsolete. The buffer size
|
||||
can be configured dynamically via buffer_size property in sysfs.
|
||||
|
||||
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
|
||||
use the SG mode on this system.
|
||||
|
||||
* Optional property for CATU :
|
||||
* interrupts : Exactly one SPI may be listed for reporting the address
|
||||
error
|
||||
|
||||
* Optional property for configurable replicators:
|
||||
|
||||
* qcom,replicator-loses-context: boolean. Indicates that the replicator
|
||||
will lose register context when AMBA clock is removed which is observed
|
||||
in some replicator designs.
|
||||
|
||||
Graph bindings for Coresight
|
||||
-------------------------------
|
||||
|
||||
Coresight components are interconnected to create a data path for the flow of
|
||||
trace data generated from the "sources" to their collection points "sink".
|
||||
Each coresight component must describe the "input" and "output" connections.
|
||||
The connections must be described via generic DT graph bindings as described
|
||||
by the "bindings/graph.txt", where each "port" along with an "endpoint"
|
||||
component represents a hardware port and the connection.
|
||||
|
||||
* All output ports must be listed inside a child node named "out-ports"
|
||||
* All input ports must be listed inside a child node named "in-ports".
|
||||
* Port address must match the hardware port number.
|
||||
|
||||
Example:
|
||||
|
||||
1. Sinks
|
||||
etb@20010000 {
|
||||
compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
etb_in_port: endpoint@0 {
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in_port: endpoint@0 {
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@20070000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20070000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
etr_in_port: endpoint {
|
||||
remote-endpoint = <&replicator2_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etr_out_port: endpoint {
|
||||
remote-endpoint = <&catu_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
2. Links
|
||||
replicator {
|
||||
/* non-configurable replicators don't show up on the
|
||||
* AMBA bus. As such no need to add "arm,primecell".
|
||||
*/
|
||||
compatible = "arm,coresight-static-replicator";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&etb_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
remote-endpoint = <&funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel {
|
||||
/*
|
||||
* non-configurable funnel don't show up on the AMBA
|
||||
* bus. As such no need to add "arm,primecell".
|
||||
*/
|
||||
compatible = "arm,coresight-static-funnel";
|
||||
clocks = <&crg_ctrl HI3660_PCLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
combo_funnel_out: endpoint {
|
||||
remote-endpoint = <&top_funnel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
combo_funnel_in0: endpoint {
|
||||
remote-endpoint = <&cluster0_etf_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
combo_funnel_in1: endpoint {
|
||||
remote-endpoint = <&cluster1_etf_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@20040000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20040000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
funnel_out_port0: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&ptm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&ptm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel_in_port2: endpoint {
|
||||
remote-endpoint = <&etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
3. Sources
|
||||
ptm@2201c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201c000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu0>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@2201d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201d000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu1>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
4. STM
|
||||
stm@20100000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x20100000 0 0x1000>,
|
||||
<0 0x28000000 0 0x180000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
stm_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
5. CATU
|
||||
|
||||
catu@207e0000 {
|
||||
compatible = "arm,coresight-catu", "arm,primecell";
|
||||
reg = <0 0x207e0000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
in-ports {
|
||||
port {
|
||||
catu_in_port: endpoint {
|
||||
remote-endpoint = <&etr_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
[1]. There is currently two version of STM: STM32 and STM500. Both
|
||||
have the same HW interface and as such don't need an explicit binding name.
|
||||
238
sys/contrib/device-tree/Bindings/arm/cpu-capacity.txt
Normal file
238
sys/contrib/device-tree/Bindings/arm/cpu-capacity.txt
Normal file
@ -0,0 +1,238 @@
|
||||
==========================================
|
||||
ARM CPUs capacity bindings
|
||||
==========================================
|
||||
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
ARM systems may be configured to have cpus with different power/performance
|
||||
characteristics within the same chip. In this case, additional information has
|
||||
to be made available to the kernel for it to be aware of such differences and
|
||||
take decisions accordingly.
|
||||
|
||||
==========================================
|
||||
2 - CPU capacity definition
|
||||
==========================================
|
||||
|
||||
CPU capacity is a number that provides the scheduler information about CPUs
|
||||
heterogeneity. Such heterogeneity can come from micro-architectural differences
|
||||
(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
|
||||
(e.g., SMP systems with multiple frequency domains). Heterogeneity in this
|
||||
context is about differing performance characteristics; this binding tries to
|
||||
capture a first-order approximation of the relative performance of CPUs.
|
||||
|
||||
CPU capacities are obtained by running a suitable benchmark. This binding makes
|
||||
no guarantees on the validity or suitability of any particular benchmark, the
|
||||
final capacity should, however, be:
|
||||
|
||||
* A "single-threaded" or CPU affine benchmark
|
||||
* Divided by the running frequency of the CPU executing the benchmark
|
||||
* Not subject to dynamic frequency scaling of the CPU
|
||||
|
||||
For the time being we however advise usage of the Dhrystone benchmark. What
|
||||
above thus becomes:
|
||||
|
||||
CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
|
||||
max frequency (with caches enabled). The obtained DMIPS score is then divided
|
||||
by the frequency (in MHz) at which the benchmark has been run, so that
|
||||
DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
|
||||
score obtained in the system.
|
||||
|
||||
==========================================
|
||||
3 - capacity-dmips-mhz
|
||||
==========================================
|
||||
|
||||
capacity-dmips-mhz is an optional cpu node [1] property: u32 value
|
||||
representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
|
||||
maximum frequency available to the cpu is then used to calculate the capacity
|
||||
value internally used by the kernel.
|
||||
|
||||
capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
|
||||
node, it has to be specified for every other cpu nodes, or the system will
|
||||
fall back to the default capacity value for every CPU. If cpufreq is not
|
||||
available, final capacities are calculated by directly using capacity-dmips-
|
||||
mhz values (normalized w.r.t. the highest value found while parsing the DT).
|
||||
|
||||
===========================================
|
||||
4 - Examples
|
||||
===========================================
|
||||
|
||||
Example 1 (ARM 64-bit, 6-cpu system, two clusters):
|
||||
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
|
||||
are 1024 and 578 for cluster0 and cluster1. Further normalization
|
||||
is done by the operating system based on cluster0@max-freq=1100 and
|
||||
custer1@max-freq=850, final capacities are 1024 for cluster0 and
|
||||
446 for cluster1 (576*850/1100).
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <100>;
|
||||
exit-latency-us = <250>;
|
||||
min-residency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
Example 2 (ARM 32-bit, 4-cpu system, two clusters,
|
||||
cpus 0,1@1GHz, cpus 2,3@500MHz):
|
||||
capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
|
||||
cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
capacity-dmips-mhz = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x100>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x101>;
|
||||
capacity-dmips-mhz = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
===========================================
|
||||
5 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
@ -0,0 +1,80 @@
|
||||
========================================================
|
||||
Secondary CPU enable-method "al,alpine-smp" binding
|
||||
========================================================
|
||||
|
||||
This document describes the "al,alpine-smp" method for
|
||||
enabling secondary CPUs. To apply to all CPUs, a single
|
||||
"al,alpine-smp" enable method should be defined in the
|
||||
"cpus" node.
|
||||
|
||||
Enable method name: "al,alpine-smp"
|
||||
Compatible machines: "al,alpine"
|
||||
Compatible CPUs: "arm,cortex-a15"
|
||||
Related properties: (none)
|
||||
|
||||
Note:
|
||||
This enable method requires valid nodes compatible with
|
||||
"al,alpine-cpu-resume" and "al,alpine-nb-service".
|
||||
|
||||
|
||||
* Alpine CPU resume registers
|
||||
|
||||
The CPU resume register are used to define required resume address after
|
||||
reset.
|
||||
|
||||
Properties:
|
||||
- compatible : Should contain "al,alpine-cpu-resume".
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
|
||||
* Alpine System-Fabric Service Registers
|
||||
|
||||
The System-Fabric Service Registers allow various operation on CPU and
|
||||
system fabric, like powering CPUs off.
|
||||
|
||||
Properties:
|
||||
- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "al,alpine-smp";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_resume {
|
||||
compatible = "al,alpine-cpu-resume";
|
||||
reg = <0xfbff5ed0 0x30>;
|
||||
};
|
||||
|
||||
nb_service {
|
||||
compatible = "al,alpine-sysfabric-service", "syscon";
|
||||
reg = <0xfb070000 0x10000>;
|
||||
};
|
||||
@ -0,0 +1,41 @@
|
||||
========================================================
|
||||
Secondary CPU enable-method "marvell,berlin-smp" binding
|
||||
========================================================
|
||||
|
||||
This document describes the "marvell,berlin-smp" method for enabling secondary
|
||||
CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
|
||||
be defined in the "cpus" node.
|
||||
|
||||
Enable method name: "marvell,berlin-smp"
|
||||
Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
|
||||
Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
|
||||
Related properties: (none)
|
||||
|
||||
Note:
|
||||
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
|
||||
"marvell,berlin-cpu-ctrl"[1].
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,berlin-smp";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
[1] arm/marvell,berlin.txt
|
||||
@ -0,0 +1,42 @@
|
||||
=========================================================
|
||||
Secondary CPU enable-method "nuvoton,npcm750-smp" binding
|
||||
=========================================================
|
||||
|
||||
To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
|
||||
defined in the "cpus" node.
|
||||
|
||||
Enable method name: "nuvoton,npcm750-smp"
|
||||
Compatible machines: "nuvoton,npcm750"
|
||||
Compatible CPUs: "arm,cortex-a9"
|
||||
Related properties: (none)
|
||||
|
||||
Note:
|
||||
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
|
||||
"nuvoton,npcm750-gcr".
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "nuvoton,npcm750-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
clocks = <&clk NPCM7XX_CLK_CPU>;
|
||||
clock-names = "clk_cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
clocks = <&clk NPCM7XX_CLK_CPU>;
|
||||
clock-names = "clk_cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
535
sys/contrib/device-tree/Bindings/arm/cpus.yaml
Normal file
535
sys/contrib/device-tree/Bindings/arm/cpus.yaml
Normal file
@ -0,0 +1,535 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/cpus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM CPUs bindings
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
The device tree allows to describe the layout of CPUs in a system through
|
||||
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
|
||||
defining properties for every cpu.
|
||||
|
||||
Bindings for CPU nodes follow the Devicetree Specification, available from:
|
||||
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
with updates for 32-bit and 64-bit ARM systems provided in this document.
|
||||
|
||||
================================
|
||||
Convention used in this document
|
||||
================================
|
||||
|
||||
This document follows the conventions described in the Devicetree
|
||||
Specification, with the addition:
|
||||
|
||||
- square brackets define bitfields, eg reg[7:0] value of the bitfield in
|
||||
the reg property contained in bits 7 down to 0
|
||||
|
||||
=====================================
|
||||
cpus and cpu node bindings definition
|
||||
=====================================
|
||||
|
||||
The ARM architecture, in accordance with the Devicetree Specification,
|
||||
requires the cpus and cpu nodes to be present and contain the properties
|
||||
described below.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version and
|
||||
configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
this property is required and must be set to 0.
|
||||
|
||||
On ARM 11 MPcore based systems this property is
|
||||
required and matches the CPUID[11:0] register bits.
|
||||
|
||||
Bits [11:0] in the reg cell must be set to
|
||||
bits [11:0] in CPU ID register.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On 32-bit ARM v7 or later systems this property is
|
||||
required and matches the CPU MPIDR[23:0] register
|
||||
bits.
|
||||
|
||||
Bits [23:0] in the reg cell must be set to
|
||||
bits [23:0] in MPIDR.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On ARM v8 64-bit systems this property is required
|
||||
and matches the MPIDR_EL1 register affinity bits.
|
||||
|
||||
* If cpus node's #address-cells property is set to 2
|
||||
|
||||
The first reg cell bits [7:0] must be set to
|
||||
bits [39:32] of MPIDR_EL1.
|
||||
|
||||
The second reg cell bits [23:0] must be set to
|
||||
bits [23:0] of MPIDR_EL1.
|
||||
|
||||
* If cpus node's #address-cells property is set to 1
|
||||
|
||||
The reg cell bits [23:0] must be set to bits [23:0]
|
||||
of MPIDR_EL1.
|
||||
|
||||
All other bits in the reg cells must be set to 0.
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- arm,arm710t
|
||||
- arm,arm720t
|
||||
- arm,arm740t
|
||||
- arm,arm7ej-s
|
||||
- arm,arm7tdmi
|
||||
- arm,arm7tdmi-s
|
||||
- arm,arm9es
|
||||
- arm,arm9ej-s
|
||||
- arm,arm920t
|
||||
- arm,arm922t
|
||||
- arm,arm925
|
||||
- arm,arm926e-s
|
||||
- arm,arm926ej-s
|
||||
- arm,arm940t
|
||||
- arm,arm946e-s
|
||||
- arm,arm966e-s
|
||||
- arm,arm968e-s
|
||||
- arm,arm9tdmi
|
||||
- arm,arm1020e
|
||||
- arm,arm1020t
|
||||
- arm,arm1022e
|
||||
- arm,arm1026ej-s
|
||||
- arm,arm1136j-s
|
||||
- arm,arm1136jf-s
|
||||
- arm,arm1156t2-s
|
||||
- arm,arm1156t2f-s
|
||||
- arm,arm1176jzf
|
||||
- arm,arm1176jz-s
|
||||
- arm,arm1176jzf-s
|
||||
- arm,arm11mpcore
|
||||
- arm,armv8 # Only for s/w models
|
||||
- arm,cortex-a5
|
||||
- arm,cortex-a7
|
||||
- arm,cortex-a8
|
||||
- arm,cortex-a9
|
||||
- arm,cortex-a12
|
||||
- arm,cortex-a15
|
||||
- arm,cortex-a17
|
||||
- arm,cortex-a32
|
||||
- arm,cortex-a34
|
||||
- arm,cortex-a35
|
||||
- arm,cortex-a53
|
||||
- arm,cortex-a55
|
||||
- arm,cortex-a57
|
||||
- arm,cortex-a65
|
||||
- arm,cortex-a72
|
||||
- arm,cortex-a73
|
||||
- arm,cortex-a75
|
||||
- arm,cortex-a76
|
||||
- arm,cortex-a77
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
- arm,cortex-m1
|
||||
- arm,cortex-m3
|
||||
- arm,cortex-m4
|
||||
- arm,cortex-r4
|
||||
- arm,cortex-r5
|
||||
- arm,cortex-r7
|
||||
- arm,neoverse-e1
|
||||
- arm,neoverse-n1
|
||||
- brcm,brahma-b15
|
||||
- brcm,brahma-b53
|
||||
- brcm,vulcan
|
||||
- cavium,thunder
|
||||
- cavium,thunder2
|
||||
- faraday,fa526
|
||||
- intel,sa110
|
||||
- intel,sa1100
|
||||
- marvell,feroceon
|
||||
- marvell,mohawk
|
||||
- marvell,pj4a
|
||||
- marvell,pj4b
|
||||
- marvell,sheeva-v5
|
||||
- marvell,sheeva-v7
|
||||
- nvidia,tegra132-denver
|
||||
- nvidia,tegra186-denver
|
||||
- nvidia,tegra194-carmel
|
||||
- qcom,krait
|
||||
- qcom,kryo
|
||||
- qcom,kryo260
|
||||
- qcom,kryo280
|
||||
- qcom,kryo385
|
||||
- qcom,kryo468
|
||||
- qcom,kryo485
|
||||
- qcom,scorpion
|
||||
|
||||
enable-method:
|
||||
$ref: '/schemas/types.yaml#/definitions/string'
|
||||
oneOf:
|
||||
# On ARM v8 64-bit this property is required
|
||||
- enum:
|
||||
- psci
|
||||
- spin-table
|
||||
# On ARM 32-bit systems this property is optional
|
||||
- enum:
|
||||
- actions,s500-smp
|
||||
- allwinner,sun6i-a31
|
||||
- allwinner,sun8i-a23
|
||||
- allwinner,sun9i-a80-smp
|
||||
- allwinner,sun8i-a83t-smp
|
||||
- amlogic,meson8-smp
|
||||
- amlogic,meson8b-smp
|
||||
- arm,realview-smp
|
||||
- aspeed,ast2600-smp
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm2836-smp
|
||||
- brcm,bcm63138
|
||||
- brcm,bcm-nsp-smp
|
||||
- brcm,brahma-b15
|
||||
- marvell,armada-375-smp
|
||||
- marvell,armada-380-smp
|
||||
- marvell,armada-390-smp
|
||||
- marvell,armada-xp-smp
|
||||
- marvell,98dx3236-smp
|
||||
- marvell,mmp3-smp
|
||||
- mediatek,mt6589-smp
|
||||
- mediatek,mt81xx-tz-smp
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,kpss-acc-v1
|
||||
- qcom,kpss-acc-v2
|
||||
- renesas,apmu
|
||||
- renesas,r9a06g032-smp
|
||||
- rockchip,rk3036-smp
|
||||
- rockchip,rk3066-smp
|
||||
- socionext,milbeaut-m10v-smp
|
||||
- ste,dbx500-smp
|
||||
- ti,am3352
|
||||
- ti,am4372
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
|
||||
description:
|
||||
Required for systems that have an "enable-method"
|
||||
property value of "spin-table".
|
||||
On ARM v8 64-bit systems must be a two cell
|
||||
property identifying a 64-bit zero-initialised
|
||||
memory location.
|
||||
|
||||
cpu-idle-states:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
description: |
|
||||
List of phandles to idle state nodes supported
|
||||
by this cpu (see ./idle-states.yaml).
|
||||
|
||||
capacity-dmips-mhz:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
u32 value representing CPU capacity (see ./cpu-capacity.txt) in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
|
||||
dynamic-power-coefficient:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
A u32 value that represents the running time dynamic
|
||||
power coefficient in units of uW/MHz/V^2. The
|
||||
coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
The dynamic power consumption of the CPU is
|
||||
proportional to the square of the Voltage (V) and
|
||||
the clock frequency (f). The coefficient is used to
|
||||
calculate the dynamic power as below -
|
||||
|
||||
Pdyn = dynamic-power-coefficient * V^2 * f
|
||||
|
||||
where voltage is in V, frequency is in MHz.
|
||||
|
||||
power-domains:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
description:
|
||||
List of phandles and PM domain specifiers, as defined by bindings of the
|
||||
PM domain provider (see also ../power_domain.txt).
|
||||
|
||||
power-domain-names:
|
||||
$ref: '/schemas/types.yaml#/definitions/string-array'
|
||||
description:
|
||||
A list of power domain name strings sorted in the same order as the
|
||||
power-domains property.
|
||||
|
||||
For PSCI based platforms, the name corresponding to the index of the PSCI
|
||||
PM domain provider, must be "psci".
|
||||
|
||||
qcom,saw:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the SAW* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,saw2.txt
|
||||
|
||||
qcom,acc:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the ACC* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,kpss-acc.txt
|
||||
|
||||
rockchip,pmu:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the syscon node controlling the cpu core power domains.
|
||||
|
||||
Optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
|
||||
secondary-boot-reg:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: |
|
||||
Required for systems that have an "enable-method" property value of
|
||||
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
|
||||
|
||||
This includes the following SoCs: |
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
if:
|
||||
# If the enable-method property contains one of those values
|
||||
properties:
|
||||
enable-method:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm-nsp-smp
|
||||
# and if enable-method is present
|
||||
required:
|
||||
- enable-method
|
||||
|
||||
then:
|
||||
required:
|
||||
- secondary-boot-reg
|
||||
|
||||
required:
|
||||
- device_type
|
||||
- reg
|
||||
- compatible
|
||||
|
||||
dependencies:
|
||||
rockchip,pmu: [enable-method]
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (Cortex-A8 uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm926ej-s";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 4 (ARM Cortex-A57 64-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
16
sys/contrib/device-tree/Bindings/arm/digicolor.yaml
Normal file
16
sys/contrib/device-tree/Bindings/arm/digicolor.yaml
Normal file
@ -0,0 +1,16 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/digicolor.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Conexant Digicolor Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Baruch Siach <baruch@tkos.co.il>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cnxt,cx92755
|
||||
|
||||
...
|
||||
@ -0,0 +1,31 @@
|
||||
OP-TEE Device Tree Bindings
|
||||
|
||||
OP-TEE is a piece of software using hardware features to provide a Trusted
|
||||
Execution Environment. The security can be provided with ARM TrustZone, but
|
||||
also by virtualization or a separate chip.
|
||||
|
||||
We're using "linaro" as the first part of the compatible property for
|
||||
the reference implementation maintained by Linaro.
|
||||
|
||||
* OP-TEE based on ARM TrustZone required properties:
|
||||
|
||||
- compatible : should contain "linaro,optee-tz"
|
||||
|
||||
- method : The method of calling the OP-TEE Trusted OS. Permitted
|
||||
values are:
|
||||
|
||||
"smc" : SMC #0, with the register assignments specified
|
||||
in drivers/tee/optee/optee_smc.h
|
||||
|
||||
"hvc" : HVC #0, with the register assignments specified
|
||||
in drivers/tee/optee/optee_smc.h
|
||||
|
||||
|
||||
|
||||
Example:
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
42
sys/contrib/device-tree/Bindings/arm/firmware/sdei.txt
Normal file
42
sys/contrib/device-tree/Bindings/arm/firmware/sdei.txt
Normal file
@ -0,0 +1,42 @@
|
||||
* Software Delegated Exception Interface (SDEI)
|
||||
|
||||
Firmware implementing the SDEI functions described in ARM document number
|
||||
ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
|
||||
Linux to receive notification of events such as those generated by
|
||||
firmware-first error handling, or from an IRQ that has been promoted to
|
||||
a firmware-assisted NMI.
|
||||
|
||||
The interface provides a number of API functions for registering callbacks
|
||||
and enabling/disabling events. Functions are invoked by trapping to the
|
||||
privilege level of the SDEI firmware (specified as part of the binding
|
||||
below) and passing arguments in a manner specified by the "SMC Calling
|
||||
Convention (ARM DEN 0028B):
|
||||
|
||||
r0 => 32-bit Function ID / return value
|
||||
{r1 - r3} => Parameters
|
||||
|
||||
Note that the immediate field of the trapping instruction must be set
|
||||
to #0.
|
||||
|
||||
The SDEI_EVENT_REGISTER function registers a callback in the kernel
|
||||
text to handle the specified event number.
|
||||
|
||||
The sdei node should be a child node of '/firmware' and have required
|
||||
properties:
|
||||
|
||||
- compatible : should contain:
|
||||
* "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.
|
||||
|
||||
- method : The method of calling the SDEI firmware. Permitted
|
||||
values are:
|
||||
* "smc" : SMC #0, with the register assignments specified in this
|
||||
binding.
|
||||
* "hvc" : HVC #0, with the register assignments specified in this
|
||||
binding.
|
||||
Example:
|
||||
firmware {
|
||||
sdei {
|
||||
compatible = "arm,sdei-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,20 @@
|
||||
Trusted Foundations
|
||||
-------------------
|
||||
|
||||
Boards that use the Trusted Foundations secure monitor can signal its
|
||||
presence by declaring a node compatible with "tlm,trusted-foundations"
|
||||
under the /firmware/ node
|
||||
|
||||
Required properties:
|
||||
- compatible: "tlm,trusted-foundations"
|
||||
- tlm,version-major: major version number of Trusted Foundations firmware
|
||||
- tlm,version-minor: minor version number of Trusted Foundations firmware
|
||||
|
||||
Example:
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
tlm,version-major = <2>;
|
||||
tlm,version-minor = <8>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,23 @@
|
||||
Freescale i.MX7ULP Power Management Components
|
||||
----------------------------------------------
|
||||
|
||||
The Multi-System Mode Controller (MSMC) is responsible for sequencing
|
||||
the MCU into and out of all stop and run power modes. Specifically, it
|
||||
monitors events to trigger transitions between power modes while
|
||||
controlling the power, clocks, and memories of the MCU to achieve the
|
||||
power consumption and functionality of that mode.
|
||||
|
||||
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
|
||||
Standby modes for either Cortex family. Run, Wait, and Stop are the
|
||||
common terms used for the primary operating modes of Kinetis
|
||||
microcontrollers.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7ulp-smc1".
|
||||
- reg: Specifies base physical address and size of the register sets.
|
||||
|
||||
Example:
|
||||
smc1: smc1@40410000 {
|
||||
compatible = "fsl,imx7ulp-smc1";
|
||||
reg = <0x40410000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,16 @@
|
||||
Freescale i.MX7ULP System Integration Module
|
||||
----------------------------------------------
|
||||
The system integration module (SIM) provides system control and chip configuration
|
||||
registers. In this module, chip revision information is located in JTAG ID register,
|
||||
and a set of registers have been made available in DGO domain for SW use, with the
|
||||
objective to maintain its value between system resets.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7ulp-sim".
|
||||
- reg: Specifies base physical address and size of the register sets.
|
||||
|
||||
Example:
|
||||
sim: sim@410a3000 {
|
||||
compatible = "fsl,imx7ulp-sim", "syscon";
|
||||
reg = <0x410a3000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,19 @@
|
||||
Freescale DCFG
|
||||
|
||||
DCFG is the device configuration unit, that provides general purpose
|
||||
configuration and status for the device. Such as setting the secondary
|
||||
core start address and release the secondary core from holdoff and startup.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain a chip-specific compatible string,
|
||||
Chip-specific strings are of the form "fsl,<chip>-dcfg",
|
||||
The following <chip>s are known to be supported:
|
||||
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
|
||||
|
||||
- reg : should contain base address and length of DCFG memory-mapped registers
|
||||
|
||||
Example:
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1021a-dcfg";
|
||||
reg = <0x0 0x1ee0000 0x0 0x10000>;
|
||||
};
|
||||
@ -0,0 +1,19 @@
|
||||
Freescale SCFG
|
||||
|
||||
SCFG is the supplemental configuration unit, that provides SoC specific
|
||||
configuration and status registers for the chip. Such as getting PEX port
|
||||
status.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain a chip-specific compatible string,
|
||||
Chip-specific strings are of the form "fsl,<chip>-scfg",
|
||||
The following <chip>s are known to be supported:
|
||||
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
|
||||
|
||||
- reg: should contain base address and length of SCFG memory-mapped registers
|
||||
|
||||
Example:
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1021a-scfg";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
};
|
||||
270
sys/contrib/device-tree/Bindings/arm/freescale/fsl,scu.txt
Normal file
270
sys/contrib/device-tree/Bindings/arm/freescale/fsl,scu.txt
Normal file
@ -0,0 +1,270 @@
|
||||
NXP i.MX System Controller Firmware (SCFW)
|
||||
--------------------------------------------------------------------
|
||||
|
||||
The System Controller Firmware (SCFW) is a low-level system function
|
||||
which runs on a dedicated Cortex-M core to provide power, clock, and
|
||||
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
|
||||
(QM, QP), and i.MX8QX (QXP, DX).
|
||||
|
||||
The AP communicates with the SC using a multi-ported MU module found
|
||||
in the LSIO subsystem. The current definition of this MU module provides
|
||||
5 remote AP connections to the SC to support up to 5 execution environments
|
||||
(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
|
||||
with the LSIO DSC IP bus. The SC firmware will communicate with this MU
|
||||
using the MSI bus.
|
||||
|
||||
System Controller Device Node:
|
||||
============================================================
|
||||
|
||||
The scu node with the following properties shall be under the /firmware/ node.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- compatible: should be "fsl,imx-scu".
|
||||
- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
|
||||
"rx0", "rx1", "rx2", "rx3";
|
||||
include "gip3" if want to support general MU interrupt.
|
||||
- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
|
||||
rx, and 1 optional MU channel for general interrupt.
|
||||
All MU channels must be in the same MU instance.
|
||||
Cross instances are not allowed. The MU instance can only
|
||||
be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
|
||||
to make sure use the one which is not conflict with other
|
||||
execution environments. e.g. ATF.
|
||||
Note:
|
||||
Channel 0 must be "tx0" or "rx0".
|
||||
Channel 1 must be "tx1" or "rx1".
|
||||
Channel 2 must be "tx2" or "rx2".
|
||||
Channel 3 must be "tx3" or "rx3".
|
||||
General interrupt rx channel must be "gip3".
|
||||
e.g.
|
||||
mboxes = <&lsio_mu1 0 0
|
||||
&lsio_mu1 0 1
|
||||
&lsio_mu1 0 2
|
||||
&lsio_mu1 0 3
|
||||
&lsio_mu1 1 0
|
||||
&lsio_mu1 1 1
|
||||
&lsio_mu1 1 2
|
||||
&lsio_mu1 1 3
|
||||
&lsio_mu1 3 3>;
|
||||
See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
|
||||
for detailed mailbox binding.
|
||||
|
||||
Note: Each mu which supports general interrupt should have an alias correctly
|
||||
numbered in "aliases" node.
|
||||
e.g.
|
||||
aliases {
|
||||
mu1 = &lsio_mu1;
|
||||
};
|
||||
|
||||
i.MX SCU Client Device Node:
|
||||
============================================================
|
||||
|
||||
Client nodes are maintained as children of the relevant IMX-SCU device node.
|
||||
|
||||
Power domain bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding for the SCU power domain providers uses the generic power
|
||||
domain binding[2].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-scu-pd",
|
||||
"fsl,imx8qxp-scu-pd"
|
||||
followed by "fsl,scu-pd"
|
||||
|
||||
- #power-domain-cells: Must be 1. Contains the Resource ID used by
|
||||
SCU commands.
|
||||
See detailed Resource ID list from:
|
||||
include/dt-bindings/firmware/imx/rsrc.h
|
||||
|
||||
Clock bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-clock"
|
||||
"fsl,imx8qxp-clock"
|
||||
followed by "fsl,scu-clk"
|
||||
- #clock-cells: Should be 1. Contains the Clock ID value.
|
||||
- clocks: List of clock specifiers, must contain an entry for
|
||||
each required entry in clock-names
|
||||
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
|
||||
See the full list of clock IDs from:
|
||||
include/dt-bindings/clock/imx8qxp-clock.h
|
||||
|
||||
Pinctrl bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
This binding uses the i.MX common pinctrl binding[3].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-iomuxc",
|
||||
"fsl,imx8qxp-iomuxc",
|
||||
"fsl,imx8dxl-iomuxc".
|
||||
|
||||
Required properties for Pinctrl sub nodes:
|
||||
- fsl,pins: Each entry consists of 3 integers which represents
|
||||
the mux and config setting for one pin. The first 2
|
||||
integers <pin_id mux_mode> are specified using a
|
||||
PIN_FUNC_ID macro, which can be found in
|
||||
<dt-bindings/pinctrl/pads-imx8qm.h>,
|
||||
<dt-bindings/pinctrl/pads-imx8qxp.h>,
|
||||
<dt-bindings/pinctrl/pads-imx8dxl.h>.
|
||||
The last integer CONFIG is the pad setting value like
|
||||
pull-up on this pin.
|
||||
|
||||
Please refer to i.MX8QXP Reference Manual for detailed
|
||||
CONFIG settings.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
|
||||
|
||||
RTC bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx8qxp-sc-rtc";
|
||||
|
||||
OCOTP bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-scu-ocotp",
|
||||
"fsl,imx8qxp-scu-ocotp".
|
||||
- #address-cells: Must be 1. Contains byte index
|
||||
- #size-cells: Must be 1. Contains byte length
|
||||
|
||||
Optional Child nodes:
|
||||
|
||||
- Data cells of ocotp:
|
||||
Detailed bindings are described in bindings/nvmem/nvmem.txt
|
||||
|
||||
Watchdog bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be:
|
||||
"fsl,imx8qxp-sc-wdt"
|
||||
followed by "fsl,imx-sc-wdt";
|
||||
Optional properties:
|
||||
- timeout-sec: contains the watchdog timeout in seconds.
|
||||
|
||||
SCU key bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be:
|
||||
"fsl,imx8qxp-sc-key"
|
||||
followed by "fsl,imx-sc-key";
|
||||
- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
|
||||
|
||||
Thermal bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be :
|
||||
"fsl,imx8qxp-sc-thermal"
|
||||
followed by "fsl,imx-sc-thermal";
|
||||
|
||||
- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
|
||||
for a description.
|
||||
|
||||
Example (imx8qxp):
|
||||
-------------
|
||||
aliases {
|
||||
mu1 = &lsio_mu1;
|
||||
};
|
||||
|
||||
lsio_mu1: mailbox@5d1c0000 {
|
||||
...
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
scu {
|
||||
compatible = "fsl,imx-scu";
|
||||
mbox-names = "tx0", "tx1", "tx2", "tx3",
|
||||
"rx0", "rx1", "rx2", "rx3",
|
||||
"gip3";
|
||||
mboxes = <&lsio_mu1 0 0
|
||||
&lsio_mu1 0 1
|
||||
&lsio_mu1 0 2
|
||||
&lsio_mu1 0 3
|
||||
&lsio_mu1 1 0
|
||||
&lsio_mu1 1 1
|
||||
&lsio_mu1 1 2
|
||||
&lsio_mu1 1 3
|
||||
&lsio_mu1 3 3>;
|
||||
|
||||
clk: clk {
|
||||
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
iomuxc {
|
||||
compatible = "fsl,imx8qxp-iomuxc";
|
||||
|
||||
pinctrl_lpuart0: lpuart0grp {
|
||||
fsl,pins = <
|
||||
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
|
||||
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
|
||||
>;
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
ocotp: imx8qx-ocotp {
|
||||
compatible = "fsl,imx8qxp-scu-ocotp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
fec_mac0: mac@2c4 {
|
||||
reg = <0x2c4 8>;
|
||||
};
|
||||
};
|
||||
|
||||
pd: imx8qx-pd {
|
||||
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fsl,imx8qxp-sc-rtc";
|
||||
};
|
||||
|
||||
scu_key: scu-key {
|
||||
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
|
||||
linux,keycodes = <KEY_POWER>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@5a060000 {
|
||||
...
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
clocks = <&clk IMX8QXP_UART0_CLK>,
|
||||
<&clk IMX8QXP_UART0_IPG_CLK>;
|
||||
clock-names = "per", "ipg";
|
||||
power-domains = <&pd IMX_SC_R_UART_0>;
|
||||
};
|
||||
@ -0,0 +1,14 @@
|
||||
Freescale Vybrid Miscellaneous System Control - CPU Configuration
|
||||
|
||||
The MSCM IP contains multiple sub modules, this binding describes the first
|
||||
block of registers which contains CPU configuration information.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
|
||||
- reg: the register range of the MSCM CPU configuration registers
|
||||
|
||||
Example:
|
||||
mscm_cpucfg: cpucfg@40001000 {
|
||||
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
|
||||
reg = <0x40001000 0x800>;
|
||||
}
|
||||
@ -0,0 +1,30 @@
|
||||
Freescale Vybrid Miscellaneous System Control - Interrupt Router
|
||||
|
||||
The MSCM IP contains multiple sub modules, this binding describes the second
|
||||
block of registers which control the interrupt router. The interrupt router
|
||||
allows to configure the recipient of each peripheral interrupt. Furthermore
|
||||
it controls the directed processor interrupts. The module is available in all
|
||||
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
|
||||
which comes with a Cortex-A5/Cortex-M4 combination).
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,vf610-mscm-ir"
|
||||
- reg: the register range of the MSCM Interrupt Router
|
||||
- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
|
||||
to get the current CPU ID
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- #interrupt-cells: Two cells, interrupt number and cells.
|
||||
The hardware interrupt number according to interrupt
|
||||
assignment of the interrupt router is required.
|
||||
Flags get passed only when using GIC as parent. Flags
|
||||
encoding as documented by the GIC bindings.
|
||||
|
||||
Example:
|
||||
mscm_ir: interrupt-controller@40001800 {
|
||||
compatible = "fsl,vf610-mscm-ir";
|
||||
reg = <0x40001800 0x400>;
|
||||
fsl,cpucfg = <&mscm_cpucfg>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
}
|
||||
12
sys/contrib/device-tree/Bindings/arm/freescale/m4if.txt
Normal file
12
sys/contrib/device-tree/Bindings/arm/freescale/m4if.txt
Normal file
@ -0,0 +1,12 @@
|
||||
* Freescale Multi Master Multi Memory Interface (M4IF) module
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx51-m4if"
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
m4if: m4if@83fd8000 {
|
||||
compatible = "fsl,imx51-m4if";
|
||||
reg = <0x83fd8000 0x1000>;
|
||||
};
|
||||
12
sys/contrib/device-tree/Bindings/arm/freescale/tigerp.txt
Normal file
12
sys/contrib/device-tree/Bindings/arm/freescale/tigerp.txt
Normal file
@ -0,0 +1,12 @@
|
||||
* Freescale Tigerp platform module
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx51-tigerp"
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
tigerp: tigerp@83fa0000 {
|
||||
compatible = "fsl,imx51-tigerp";
|
||||
reg = <0x83fa0000 0x28>;
|
||||
};
|
||||
529
sys/contrib/device-tree/Bindings/arm/fsl.yaml
Normal file
529
sys/contrib/device-tree/Bindings/arm/fsl.yaml
Normal file
@ -0,0 +1,529 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/fsl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Li Yang <leoyang.li@nxp.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: i.MX1 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx1-apf9328
|
||||
- fsl,imx1ads
|
||||
- const: fsl,imx1
|
||||
|
||||
- description: i.MX23 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx23-evk
|
||||
- olimex,imx23-olinuxino
|
||||
- const: fsl,imx23
|
||||
|
||||
- description: i.MX25 Product Development Kit
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx25-pdk
|
||||
- const: fsl,imx25
|
||||
|
||||
- description: i.MX27 Product Development Kit
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx27-apf27 # APF27 SoM
|
||||
- armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
|
||||
- fsl,imx27-pdk
|
||||
- const: fsl,imx27
|
||||
|
||||
- description: i.MX28 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx28-apf28 # APF28 SoM
|
||||
- armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
|
||||
- fsl,imx28-evk
|
||||
- i2se,duckbill
|
||||
- i2se,duckbill-2
|
||||
- technologic,imx28-ts4600
|
||||
- const: fsl,imx28
|
||||
- description: i.MX28 Duckbill 2 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- i2se,duckbill-2-485
|
||||
- i2se,duckbill-2-enocean
|
||||
- i2se,duckbill-2-spi
|
||||
- const: i2se,duckbill-2
|
||||
- const: fsl,imx28
|
||||
|
||||
- description: i.MX31 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- buglabs,imx31-bug
|
||||
- logicpd,imx31-lite
|
||||
- const: fsl,imx31
|
||||
|
||||
- description: i.MX35 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx35-pdk
|
||||
- const: fsl,imx35
|
||||
|
||||
- description: i.MX35 Eukrea CPUIMX35 Board
|
||||
items:
|
||||
- const: eukrea,mbimxsd35-baseboard
|
||||
- const: eukrea,cpuimx35
|
||||
- const: fsl,imx35
|
||||
|
||||
- description: i.MX50 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx50-evk
|
||||
- kobo,aura
|
||||
- const: fsl,imx50
|
||||
|
||||
- description: i.MX51 Babbage Board
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx51-apf51 # APF51 SoM
|
||||
- armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
|
||||
- fsl,imx51-babbage
|
||||
- technologic,imx51-ts4800
|
||||
- const: fsl,imx51
|
||||
|
||||
- description: i.MX53 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- bhf,cx9020
|
||||
- fsl,imx53-ard
|
||||
- fsl,imx53-evk
|
||||
- fsl,imx53-qsb
|
||||
- fsl,imx53-smd
|
||||
- menlo,m53menlo
|
||||
- const: fsl,imx53
|
||||
|
||||
- description: i.MX6Q based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
|
||||
- armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
|
||||
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
|
||||
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
|
||||
- fsl,imx6q-arm2
|
||||
- fsl,imx6q-sabreauto
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
|
||||
- prt,prti6q # Protonic PRTI6Q board
|
||||
- prt,prtwd2 # Protonic WD2 board
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
|
||||
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
|
||||
- technologic,imx6q-ts4900
|
||||
- technologic,imx6q-ts7970
|
||||
- toradex,apalis_imx6q # Apalis iMX6 Module
|
||||
- toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board
|
||||
- toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora
|
||||
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1
|
||||
- variscite,dt6customboard
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6Q Gateworks Ventana Boards
|
||||
items:
|
||||
- enum:
|
||||
- gw,imx6q-gw51xx
|
||||
- gw,imx6q-gw52xx
|
||||
- gw,imx6q-gw53xx
|
||||
- gw,imx6q-gw5400-a
|
||||
- gw,imx6q-gw54xx
|
||||
- gw,imx6q-gw551x
|
||||
- gw,imx6q-gw552x
|
||||
- gw,imx6q-gw553x
|
||||
- gw,imx6q-gw560x
|
||||
- gw,imx6q-gw5903
|
||||
- gw,imx6q-gw5904
|
||||
- gw,imx6q-gw5907
|
||||
- gw,imx6q-gw5910
|
||||
- gw,imx6q-gw5912
|
||||
- gw,imx6q-gw5913
|
||||
- const: gw,ventana
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6QP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
|
||||
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: i.MX6DL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
|
||||
- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
|
||||
- eckelmann,imx6dl-ci4x10
|
||||
- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
|
||||
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
|
||||
- prt,prtrvt # Protonic RVT board
|
||||
- prt,prtvt7 # Protonic VT7 board
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
|
||||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- toradex,colibri_imx6dl # Colibri iMX6 Module
|
||||
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
|
||||
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3
|
||||
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
|
||||
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
|
||||
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL Gateworks Ventana Boards
|
||||
items:
|
||||
- enum:
|
||||
- gw,imx6dl-gw51xx
|
||||
- gw,imx6dl-gw52xx
|
||||
- gw,imx6dl-gw53xx
|
||||
- gw,imx6dl-gw54xx
|
||||
- gw,imx6dl-gw551x
|
||||
- gw,imx6dl-gw552x
|
||||
- gw,imx6dl-gw553x
|
||||
- gw,imx6dl-gw560x
|
||||
- gw,imx6dl-gw5903
|
||||
- gw,imx6dl-gw5904
|
||||
- gw,imx6dl-gw5907
|
||||
- gw,imx6dl-gw5910
|
||||
- gw,imx6dl-gw5912
|
||||
- gw,imx6dl-gw5913
|
||||
- const: gw,ventana
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6SL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
|
||||
- kobo,tolino-shine3
|
||||
- const: fsl,imx6sl
|
||||
|
||||
- description: i.MX6SLL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sll-evk
|
||||
- kobo,clarahd
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SX based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
|
||||
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
|
||||
- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
|
||||
- const: fsl,imx6sx
|
||||
|
||||
- description: i.MX6UL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
|
||||
- armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
|
||||
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
|
||||
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
|
||||
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
|
||||
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
|
||||
- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
|
||||
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S Board
|
||||
items:
|
||||
- const: kontron,imx6ul-n6310-s
|
||||
- const: kontron,imx6ul-n6310-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6311 S Board
|
||||
items:
|
||||
- const: kontron,imx6ul-n6311-s
|
||||
- const: kontron,imx6ul-n6311-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S 43 Board
|
||||
items:
|
||||
- const: kontron,imx6ul-n6310-s-43
|
||||
- const: kontron,imx6ul-n6310-s
|
||||
- const: kontron,imx6ul-n6310-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: i.MX6ULL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
|
||||
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Kontron N6411 S Board
|
||||
items:
|
||||
- const: kontron,imx6ull-n6411-s
|
||||
- const: kontron,imx6ull-n6411-som
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULZ based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
|
||||
- const: fsl,imx6ull # This seems odd. Should be last?
|
||||
- const: fsl,imx6ulz
|
||||
|
||||
- description: i.MX7S based Boards
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
|
||||
- toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
|
||||
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
|
||||
- const: fsl,imx7s
|
||||
|
||||
- description: i.MX7D based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx7d-sdb # i.MX7 SabreSD Board
|
||||
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
|
||||
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
|
||||
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
|
||||
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
|
||||
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
|
||||
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
|
||||
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
|
||||
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
|
||||
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on
|
||||
# Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on
|
||||
# Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
|
||||
# Colibri Evaluation Board V3
|
||||
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
||||
- zii,imx7d-rmu2 # ZII RMU2 Board
|
||||
- zii,imx7d-rpu2 # ZII RPU2 Board
|
||||
- const: fsl,imx7d
|
||||
|
||||
- description:
|
||||
Compulab SBC-iMX7 is a single board computer based on the
|
||||
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
|
||||
the CL-SOM-iMX7 System-on-Module providing most of the functions,
|
||||
and SB-SOM-iMX7 carrier board providing additional peripheral
|
||||
functions and connectors.
|
||||
items:
|
||||
- const: compulab,sbc-imx7
|
||||
- const: compulab,cl-som-imx7
|
||||
- const: fsl,imx7d
|
||||
|
||||
- description: i.MX7ULP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board
|
||||
- fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit
|
||||
- const: fsl,imx7ulp
|
||||
|
||||
- description: i.MX8MM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: i.MX8MN based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
|
||||
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
|
||||
- fsl,imx8mq-evk # i.MX8MQ EVK Board
|
||||
- google,imx8mq-phanbell # Google Coral Edge TPU
|
||||
- purism,librem5-devkit # Purism Librem5 devkit
|
||||
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
|
||||
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
|
||||
- const: fsl,imx8mq
|
||||
|
||||
- description: i.MX8QXP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
|
||||
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
|
||||
- toradex,colibri-imx8x # Colibri iMX8X Module
|
||||
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
For the Vybrid SoC familiy all variants with DDR controller are supported,
|
||||
which is the VF5xx and VF6xx series. Out of historical reasons, in most
|
||||
places the kernel uses vf610 to refer to the whole familiy.
|
||||
The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
|
||||
core support.
|
||||
items:
|
||||
- enum:
|
||||
- fsl,vf500
|
||||
- fsl,vf510
|
||||
- fsl,vf600
|
||||
- fsl,vf610
|
||||
- fsl,vf610m4
|
||||
- toradex,vf500-colibri_vf50 # Colibri VF50 Module
|
||||
- toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board
|
||||
- toradex,vf610-colibri_vf61 # Colibri VF61 Module
|
||||
- toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board
|
||||
|
||||
- description: ZII's VF610 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- zii,vf610cfu1 # ZII VF610 CFU1 Board
|
||||
- zii,vf610dev-c # ZII VF610 Development Board, Rev C
|
||||
- zii,vf610dev-b # ZII VF610 Development Board, Rev B
|
||||
- zii,vf610scu4-aib # ZII VF610 SCU4 AIB
|
||||
- zii,vf610dtu # ZII VF610 SSMB DTU Board
|
||||
- zii,vf610spu3 # ZII VF610 SSMB SPU3 Board
|
||||
- zii,vf610spb4 # ZII VF610 SPB4 Board
|
||||
- const: zii,vf610dev
|
||||
- const: fsl,vf610
|
||||
|
||||
- description: LS1012A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- ebs-systart,oxalis
|
||||
- fsl,ls1012a-rdb
|
||||
- fsl,ls1012a-frdm
|
||||
- fsl,ls1012a-qds
|
||||
- const: fsl,ls1012a
|
||||
|
||||
- description: LS1021A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1021a-moxa-uc-8410a
|
||||
- fsl,ls1021a-qds
|
||||
- fsl,ls1021a-twr
|
||||
- const: fsl,ls1021a
|
||||
|
||||
- description: LS1028A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1028a-qds
|
||||
- fsl,ls1028a-rdb
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: Kontron KBox A-230-LS
|
||||
items:
|
||||
- const: kontron,kbox-a-230-ls
|
||||
- const: kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2-ads2
|
||||
- kontron,sl28-var3-ads2
|
||||
- kontron,sl28-var4-ads2
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (on a generic/undefined carrier)
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (base). This is used in the base device
|
||||
tree which is compatible with the overlays provided by the
|
||||
vendor.
|
||||
items:
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: LS1043A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1043a-rdb
|
||||
- fsl,ls1043a-qds
|
||||
- const: fsl,ls1043a
|
||||
|
||||
- description: LS1046A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1046a-frwy
|
||||
- fsl,ls1046a-qds
|
||||
- fsl,ls1046a-rdb
|
||||
- const: fsl,ls1046a
|
||||
|
||||
- description: LS1088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1088a-qds
|
||||
- fsl,ls1088a-rdb
|
||||
- const: fsl,ls1088a
|
||||
|
||||
- description: LS2080A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2080a-simu
|
||||
- fsl,ls2080a-qds
|
||||
- fsl,ls2080a-rdb
|
||||
- const: fsl,ls2080a
|
||||
|
||||
- description: LS2088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2088a-qds
|
||||
- fsl,ls2088a-rdb
|
||||
- const: fsl,ls2088a
|
||||
|
||||
- description: LX2160A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,lx2160a-qds
|
||||
- fsl,lx2160a-rdb
|
||||
- const: fsl,lx2160a
|
||||
|
||||
- description: S32V234 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
|
||||
- const: fsl,s32v234
|
||||
|
||||
...
|
||||
38
sys/contrib/device-tree/Bindings/arm/fw-cfg.txt
Normal file
38
sys/contrib/device-tree/Bindings/arm/fw-cfg.txt
Normal file
@ -0,0 +1,38 @@
|
||||
* QEMU Firmware Configuration bindings for ARM
|
||||
|
||||
QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
|
||||
provide the following Firmware Configuration interface on the "virt" machine
|
||||
type:
|
||||
|
||||
- A write-only, 16-bit wide selector (or control) register,
|
||||
- a read-write, 64-bit wide data register.
|
||||
|
||||
QEMU exposes the control and data register to ARM guests as memory mapped
|
||||
registers; their location is communicated to the guest's UEFI firmware in the
|
||||
DTB that QEMU places at the bottom of the guest's DRAM.
|
||||
|
||||
The authoritative guest-side hardware interface documentation to the fw_cfg
|
||||
device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "qemu,fw-cfg-mmio".
|
||||
|
||||
- reg: the MMIO region used by the device.
|
||||
* Bytes 0x0 to 0x7 cover the data register.
|
||||
* Bytes 0x8 to 0x9 cover the selector register.
|
||||
* Further registers may be appended to the region in case of future interface
|
||||
revisions / feature bits.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
fw-cfg@9020000 {
|
||||
compatible = "qemu,fw-cfg-mmio";
|
||||
reg = <0x0 0x9020000 0x0 0xa>;
|
||||
};
|
||||
};
|
||||
108
sys/contrib/device-tree/Bindings/arm/gemini.txt
Normal file
108
sys/contrib/device-tree/Bindings/arm/gemini.txt
Normal file
@ -0,0 +1,108 @@
|
||||
Cortina systems Gemini platforms
|
||||
|
||||
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
|
||||
produced by Storlink Semiconductor around 2005. The company was renamed
|
||||
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
|
||||
It was derived from earlier products from Storm named SL3316 (Centroid) and
|
||||
SL3512 (Bulverde).
|
||||
|
||||
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
|
||||
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
|
||||
in turn acquired by Inphi, who seem to have discontinued this product family.
|
||||
|
||||
Many of the IP blocks used in the SoC comes from Faraday Technology.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "cortina,gemini";
|
||||
|
||||
Required nodes:
|
||||
|
||||
- soc: the SoC should be represented by a simple bus encompassing all the
|
||||
onchip devices, this is referred to as the soc bus node.
|
||||
|
||||
- syscon: the soc bus node must have a system controller node pointing to the
|
||||
global control registers, with the compatible string
|
||||
"cortina,gemini-syscon", "syscon";
|
||||
|
||||
Required properties on the syscon:
|
||||
- reg: syscon register location and size.
|
||||
- #clock-cells: should be set to <1> - the system controller is also a
|
||||
clock provider.
|
||||
- #reset-cells: should be set to <1> - the system controller is also a
|
||||
reset line provider.
|
||||
|
||||
The clock sources have shorthand defines in the include file:
|
||||
<dt-bindings/clock/cortina,gemini-clock.h>
|
||||
|
||||
The reset lines have shorthand defines in the include file:
|
||||
<dt-bindings/reset/cortina,gemini-reset.h>
|
||||
|
||||
- timer: the soc bus node must have a timer node pointing to the SoC timer
|
||||
block, with the compatible string "cortina,gemini-timer"
|
||||
See: clocksource/cortina,gemini-timer.txt
|
||||
|
||||
- interrupt-controller: the sob bus node must have an interrupt controller
|
||||
node pointing to the SoC interrupt controller block, with the compatible
|
||||
string "cortina,gemini-interrupt-controller"
|
||||
See interrupt-controller/cortina,gemini-interrupt-controller.txt
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
model = "Foo Gemini Machine";
|
||||
compatible = "cortina,gemini";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intcon>;
|
||||
|
||||
syscon: syscon@40000000 {
|
||||
compatible = "cortina,gemini-syscon", "syscon";
|
||||
reg = <0x40000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@42000000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x42000000 0x100>;
|
||||
resets = <&syscon GEMINI_RESET_UART>;
|
||||
clocks = <&syscon GEMINI_CLK_UART>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
timer@43000000 {
|
||||
compatible = "cortina,gemini-timer";
|
||||
reg = <0x43000000 0x1000>;
|
||||
interrupt-parent = <&intcon>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
|
||||
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
|
||||
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
|
||||
resets = <&syscon GEMINI_RESET_TIMER>;
|
||||
/* APB clock or RTC clock */
|
||||
clocks = <&syscon GEMINI_CLK_APB>,
|
||||
<&syscon GEMINI_CLK_RTC>;
|
||||
clock-names = "PCLK", "EXTCLK";
|
||||
syscon = <&syscon>;
|
||||
};
|
||||
|
||||
intcon: interrupt-controller@48000000 {
|
||||
compatible = "cortina,gemini-interrupt-controller";
|
||||
reg = <0x48000000 0x1000>;
|
||||
resets = <&syscon GEMINI_RESET_INTCON0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,14 @@
|
||||
* Hisilicon Hi3519 System Controller Block
|
||||
|
||||
This bindings use the following binding:
|
||||
Documentation/devicetree/bindings/mfd/syscon.yaml
|
||||
|
||||
Required properties:
|
||||
- compatible: "hisilicon,hi3519-sysctrl".
|
||||
- reg: the register region of this block
|
||||
|
||||
Examples:
|
||||
sysctrl: system-controller@12010000 {
|
||||
compatible = "hisilicon,hi3519-sysctrl", "syscon";
|
||||
reg = <0x12010000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,33 @@
|
||||
Hisilicon Hip06 Low Pin Count device
|
||||
Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
|
||||
provides I/O access to some legacy ISA devices.
|
||||
Hip06 is based on arm64 architecture where there is no I/O space. So, the
|
||||
I/O ports here are not CPU addresses, and there is no 'ranges' property in
|
||||
LPC device node.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be as follows:
|
||||
(a) "hisilicon,hip06-lpc"
|
||||
(b) "hisilicon,hip07-lpc"
|
||||
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
|
||||
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
|
||||
- reg: base memory range where the LPC register set is mapped.
|
||||
|
||||
Note:
|
||||
The node name before '@' must be "isa" to represent the binding stick to the
|
||||
ISA/EISA binding specification.
|
||||
|
||||
Example:
|
||||
|
||||
isa@a01b0000 {
|
||||
compatible = "hisilicon,hip06-lpc";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0xa01b0000 0x0 0x1000>;
|
||||
|
||||
ipmi0: bt@e4 {
|
||||
compatible = "ipmi-bt";
|
||||
device_type = "ipmi";
|
||||
reg = <0x01 0xe4 0x04>;
|
||||
};
|
||||
};
|
||||
319
sys/contrib/device-tree/Bindings/arm/hisilicon/hisilicon.txt
Normal file
319
sys/contrib/device-tree/Bindings/arm/hisilicon/hisilicon.txt
Normal file
@ -0,0 +1,319 @@
|
||||
Hisilicon Platforms Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
Hi3660 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3660";
|
||||
|
||||
HiKey960 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
|
||||
|
||||
Hi3670 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3670";
|
||||
|
||||
HiKey970 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
|
||||
|
||||
Hi3798cv200 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3798cv200";
|
||||
|
||||
Hi3798cv200 Poplar Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
|
||||
|
||||
Hi4511 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3620-hi4511";
|
||||
|
||||
Hi6220 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi6220";
|
||||
|
||||
HiKey Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
|
||||
|
||||
HiP01 ca9x2 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip01-ca9x2";
|
||||
|
||||
HiP04 D01 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip04-d01";
|
||||
|
||||
HiP05 D02 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip05-d02";
|
||||
|
||||
HiP06 D03 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip06-d03";
|
||||
|
||||
HiP07 D05 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip07-d05";
|
||||
|
||||
Hisilicon system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,sysctrl"
|
||||
- reg : Register address and size
|
||||
|
||||
Optional properties:
|
||||
- smp-offset : offset in sysctrl for notifying slave cpu booting
|
||||
cpu 1, reg;
|
||||
cpu 2, reg + 0x4;
|
||||
cpu 3, reg + 0x8;
|
||||
If reg value is not zero, cpun exit wfi and go
|
||||
- resume-offset : offset in sysctrl for notifying cpu0 when resume
|
||||
- reboot-offset : offset in sysctrl for system reboot
|
||||
|
||||
Example:
|
||||
|
||||
/* for Hi3620 */
|
||||
sysctrl: system-controller@fc802000 {
|
||||
compatible = "hisilicon,sysctrl";
|
||||
reg = <0xfc802000 0x1000>;
|
||||
smp-offset = <0x31c>;
|
||||
resume-offset = <0x308>;
|
||||
reboot-offset = <0x4>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon Hi3798CV200 Peripheral Controller
|
||||
|
||||
The Hi3798CV200 Peripheral Controller controls peripherals, queries
|
||||
their status, and configures some functions of peripherals.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
|
||||
and "simple-mfd".
|
||||
- reg: Register address and size of Peripheral Controller.
|
||||
- #address-cells: Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
|
||||
Examples:
|
||||
|
||||
perictrl: peripheral-controller@8a20000 {
|
||||
compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0x8a20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon Hi6220 system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hi6220-sysctrl"
|
||||
- reg : Register address and size
|
||||
- #clock-cells: should be set to 1, many clock registers are defined
|
||||
under this controller and this property must be present.
|
||||
|
||||
Hisilicon designs this controller as one of the system controllers,
|
||||
its main functions are the same as Hisilicon system controller, but
|
||||
the register offset of some core modules are different.
|
||||
|
||||
Example:
|
||||
/*for Hi6220*/
|
||||
sys_ctrl: sys_ctrl@f7030000 {
|
||||
compatible = "hisilicon,hi6220-sysctrl", "syscon";
|
||||
reg = <0x0 0xf7030000 0x0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Hisilicon Hi6220 Power Always ON domain controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hi6220-aoctrl"
|
||||
- reg : Register address and size
|
||||
- #clock-cells: should be set to 1, many clock registers are defined
|
||||
under this controller and this property must be present.
|
||||
|
||||
Hisilicon designs this system controller to control the power always
|
||||
on domain for mobile platform.
|
||||
|
||||
Example:
|
||||
/*for Hi6220*/
|
||||
ao_ctrl: ao_ctrl@f7800000 {
|
||||
compatible = "hisilicon,hi6220-aoctrl", "syscon";
|
||||
reg = <0x0 0xf7800000 0x0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Hisilicon Hi6220 Media domain controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hi6220-mediactrl"
|
||||
- reg : Register address and size
|
||||
- #clock-cells: should be set to 1, many clock registers are defined
|
||||
under this controller and this property must be present.
|
||||
|
||||
Hisilicon designs this system controller to control the multimedia
|
||||
domain(e.g. codec, G3D ...) for mobile platform.
|
||||
|
||||
Example:
|
||||
/*for Hi6220*/
|
||||
media_ctrl: media_ctrl@f4410000 {
|
||||
compatible = "hisilicon,hi6220-mediactrl", "syscon";
|
||||
reg = <0x0 0xf4410000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Hisilicon Hi6220 Power Management domain controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hi6220-pmctrl"
|
||||
- reg : Register address and size
|
||||
- #clock-cells: should be set to 1, some clock registers are define
|
||||
under this controller and this property must be present.
|
||||
|
||||
Hisilicon designs this system controller to control the power management
|
||||
domain for mobile platform.
|
||||
|
||||
Example:
|
||||
/*for Hi6220*/
|
||||
pm_ctrl: pm_ctrl@f7032000 {
|
||||
compatible = "hisilicon,hi6220-pmctrl", "syscon";
|
||||
reg = <0x0 0xf7032000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Hisilicon Hi6220 SRAM controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hi6220-sramctrl", "syscon"
|
||||
- reg : Register address and size
|
||||
|
||||
Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
|
||||
SRAM banks for power management, modem, security, etc. Further, use "syscon"
|
||||
managing the common sram which can be shared by multiple modules.
|
||||
|
||||
Example:
|
||||
/*for Hi6220*/
|
||||
sram: sram@fff80000 {
|
||||
compatible = "hisilicon,hi6220-sramctrl", "syscon";
|
||||
reg = <0x0 0xfff80000 0x0 0x12000>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon HiP01 system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,hip01-sysctrl"
|
||||
- reg : Register address and size
|
||||
|
||||
The HiP01 system controller is mostly compatible with hisilicon
|
||||
system controller,but it has some specific control registers for
|
||||
HIP01 SoC family, such as slave core boot, and also some same
|
||||
registers located at different offset.
|
||||
|
||||
Example:
|
||||
|
||||
/* for hip01-ca9x2 */
|
||||
sysctrl: system-controller@10000000 {
|
||||
compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
|
||||
reg = <0x10000000 0x1000>;
|
||||
reboot-offset = <0x4>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations.
|
||||
|
||||
Example:
|
||||
/* for HiP05 PCIe-SAS sub system */
|
||||
pcie_sas: system_controller@b0000000 {
|
||||
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
|
||||
reg = <0xb0000000 0x10000>;
|
||||
};
|
||||
|
||||
Hisilicon HiP05/HiP06 PERI sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,peri-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The PERI sub system controller is shared by peripheral controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
|
||||
controllers include mdio, ddr, iic, uart, timer and so on.
|
||||
|
||||
Example:
|
||||
/* for HiP05 sub peri system */
|
||||
peri_c_subctrl: syscon@80000000 {
|
||||
compatible = "hisilicon,peri-subctrl", "syscon";
|
||||
reg = <0x0 0x80000000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
Hisilicon HiP05/HiP06 DSA sub system controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,dsa-subctrl", "syscon";
|
||||
- reg : Register address and size
|
||||
|
||||
The DSA sub system controller is shared by peripheral controllers in
|
||||
HiP05 or HiP06 Soc to implement some basic configurations.
|
||||
|
||||
Example:
|
||||
/* for HiP05 dsa sub system */
|
||||
pcie_sas: system_controller@a0000000 {
|
||||
compatible = "hisilicon,dsa-subctrl", "syscon";
|
||||
reg = <0xa0000000 0x10000>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon CPU controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,cpuctrl"
|
||||
- reg : Register address and size
|
||||
|
||||
The clock registers and power registers of secondary cores are defined
|
||||
in CPU controller, especially in HIX5HD2 SoC.
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
PCTRL: Peripheral misc control register
|
||||
|
||||
Required Properties:
|
||||
- compatible: "hisilicon,pctrl"
|
||||
- reg: Address and size of pctrl.
|
||||
|
||||
Example:
|
||||
|
||||
/* for Hi3620 */
|
||||
pctrl: pctrl@fca09000 {
|
||||
compatible = "hisilicon,pctrl";
|
||||
reg = <0xfca09000 0x1000>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Fabric:
|
||||
|
||||
Required Properties:
|
||||
- compatible: "hisilicon,hip04-fabric";
|
||||
- reg: Address and size of Fabric
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Bootwrapper boot method (software protocol on SMP):
|
||||
|
||||
Required Properties:
|
||||
- compatible: "hisilicon,hip04-bootwrapper";
|
||||
- boot-method: Address and size of boot method.
|
||||
[0]: bootwrapper physical address
|
||||
[1]: bootwrapper size
|
||||
[2]: relocation physical address
|
||||
[3]: relocation size
|
||||
661
sys/contrib/device-tree/Bindings/arm/idle-states.yaml
Normal file
661
sys/contrib/device-tree/Bindings/arm/idle-states.yaml
Normal file
@ -0,0 +1,661 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/idle-states.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM idle states binding description
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
ARM systems contain HW capable of managing power consumption dynamically,
|
||||
where cores can be put in different low-power states (ranging from simple wfi
|
||||
to power gating) according to OS PM policies. The CPU states representing the
|
||||
range of dynamic idle states that a processor can enter at run-time, can be
|
||||
specified through device tree bindings representing the parameters required to
|
||||
enter/exit specific idle states on a given processor.
|
||||
|
||||
According to the Server Base System Architecture document (SBSA, [3]), the
|
||||
power states an ARM CPU can be put into are identified by the following list:
|
||||
|
||||
- Running
|
||||
- Idle_standby
|
||||
- Idle_retention
|
||||
- Sleep
|
||||
- Off
|
||||
|
||||
The power states described in the SBSA document define the basic CPU states on
|
||||
top of which ARM platforms implement power management schemes that allow an OS
|
||||
PM implementation to put the processor in different idle states (which include
|
||||
states listed above; "off" state is not an idle state since it does not have
|
||||
wake-up capabilities, hence it is not considered in this document).
|
||||
|
||||
Idle state parameters (e.g. entry latency) are platform specific and need to
|
||||
be characterized with bindings that provide the required information to OS PM
|
||||
code so that it can build the required tables and use them at runtime.
|
||||
|
||||
The device tree binding definition for ARM idle states is the subject of this
|
||||
document.
|
||||
|
||||
===========================================
|
||||
2 - idle-states definitions
|
||||
===========================================
|
||||
|
||||
Idle states are characterized for a specific system through a set of
|
||||
timing and energy related properties, that underline the HW behaviour
|
||||
triggered upon idle states entry and exit.
|
||||
|
||||
The following diagram depicts the CPU execution phases and related timing
|
||||
properties required to enter and exit an idle state:
|
||||
|
||||
..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
|
||||
| | | | |
|
||||
|
||||
|<------ entry ------->|
|
||||
| latency |
|
||||
|<- exit ->|
|
||||
| latency |
|
||||
|<-------- min-residency -------->|
|
||||
|<------- wakeup-latency ------->|
|
||||
|
||||
Diagram 1: CPU idle state execution phases
|
||||
|
||||
EXEC: Normal CPU execution.
|
||||
|
||||
PREP: Preparation phase before committing the hardware to idle mode
|
||||
like cache flushing. This is abortable on pending wake-up
|
||||
event conditions. The abort latency is assumed to be negligible
|
||||
(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
|
||||
goes back to EXEC. This phase is optional. If not abortable,
|
||||
this should be included in the ENTRY phase instead.
|
||||
|
||||
ENTRY: The hardware is committed to idle mode. This period must run
|
||||
to completion up to IDLE before anything else can happen.
|
||||
|
||||
IDLE: This is the actual energy-saving idle period. This may last
|
||||
between 0 and infinite time, until a wake-up event occurs.
|
||||
|
||||
EXIT: Period during which the CPU is brought back to operational
|
||||
mode (EXEC).
|
||||
|
||||
entry-latency: Worst case latency required to enter the idle state. The
|
||||
exit-latency may be guaranteed only after entry-latency has passed.
|
||||
|
||||
min-residency: Minimum period, including preparation and entry, for a given
|
||||
idle state to be worthwhile energywise.
|
||||
|
||||
wakeup-latency: Maximum delay between the signaling of a wake-up event and the
|
||||
CPU being able to execute normal code again. If not specified, this is assumed
|
||||
to be entry-latency + exit-latency.
|
||||
|
||||
These timing parameters can be used by an OS in different circumstances.
|
||||
|
||||
An idle CPU requires the expected min-residency time to select the most
|
||||
appropriate idle state based on the expected expiry time of the next IRQ
|
||||
(i.e. wake-up) that causes the CPU to return to the EXEC phase.
|
||||
|
||||
An operating system scheduler may need to compute the shortest wake-up delay
|
||||
for CPUs in the system by detecting how long will it take to get a CPU out
|
||||
of an idle state, e.g.:
|
||||
|
||||
wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
|
||||
|
||||
In other words, the scheduler can make its scheduling decision by selecting
|
||||
(e.g. waking-up) the CPU with the shortest wake-up delay.
|
||||
The wake-up delay must take into account the entry latency if that period
|
||||
has not expired. The abortable nature of the PREP period can be ignored
|
||||
if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
|
||||
the worst case since it depends on the CPU operating conditions, i.e. caches
|
||||
state).
|
||||
|
||||
An OS has to reliably probe the wakeup-latency since some devices can enforce
|
||||
latency constraint guarantees to work properly, so the OS has to detect the
|
||||
worst case wake-up latency it can incur if a CPU is allowed to enter an
|
||||
idle state, and possibly to prevent that to guarantee reliable device
|
||||
functioning.
|
||||
|
||||
The min-residency time parameter deserves further explanation since it is
|
||||
expressed in time units but must factor in energy consumption coefficients.
|
||||
|
||||
The energy consumption of a cpu when it enters a power state can be roughly
|
||||
characterised by the following graph:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
e |
|
||||
n | /---
|
||||
e | /------
|
||||
r | /------
|
||||
g | /-----
|
||||
y | /------
|
||||
| ----
|
||||
| /|
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
|/ |
|
||||
-----|-------+----------------------------------
|
||||
0| 1 time(ms)
|
||||
|
||||
Graph 1: Energy vs time example
|
||||
|
||||
The graph is split in two parts delimited by time 1ms on the X-axis.
|
||||
The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
|
||||
and denotes the energy costs incurred while entering and leaving the idle
|
||||
state.
|
||||
The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
|
||||
shallower slope and essentially represents the energy consumption of the idle
|
||||
state.
|
||||
|
||||
min-residency is defined for a given idle state as the minimum expected
|
||||
residency time for a state (inclusive of preparation and entry) after
|
||||
which choosing that state become the most energy efficient option. A good
|
||||
way to visualise this, is by taking the same graph above and comparing some
|
||||
states energy consumptions plots.
|
||||
|
||||
For sake of simplicity, let's consider a system with two idle states IDLE1,
|
||||
and IDLE2:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
| /-- IDLE1
|
||||
e | /---
|
||||
n | /----
|
||||
e | /---
|
||||
r | /-----/--------- IDLE2
|
||||
g | /-------/---------
|
||||
y | ------------ /---|
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| --- |
|
||||
| / |
|
||||
| / |
|
||||
|/ | time
|
||||
---/----------------------------+------------------------
|
||||
|IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
|
||||
|
|
||||
IDLE2-min-residency
|
||||
|
||||
Graph 2: idle states min-residency example
|
||||
|
||||
In graph 2 above, that takes into account idle states entry/exit energy
|
||||
costs, it is clear that if the idle state residency time (i.e. time till next
|
||||
wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
|
||||
choice energywise.
|
||||
|
||||
This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
|
||||
than IDLE2.
|
||||
|
||||
However, the lower power consumption (i.e. shallower energy curve slope) of
|
||||
idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
|
||||
efficient.
|
||||
|
||||
The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
|
||||
shallower states in a system with multiple idle states) is defined
|
||||
IDLE2-min-residency and corresponds to the time when energy consumption of
|
||||
IDLE1 and IDLE2 states breaks even.
|
||||
|
||||
The definitions provided in this section underpin the idle states
|
||||
properties specification that is the subject of the following sections.
|
||||
|
||||
===========================================
|
||||
3 - idle-states node
|
||||
===========================================
|
||||
|
||||
ARM processor idle states are defined within the idle-states node, which is
|
||||
a direct child of the cpus node [1] and provides a container where the
|
||||
processor idle states, defined as device tree nodes, are listed.
|
||||
|
||||
On ARM systems, it is a container of processor idle states nodes. If the
|
||||
system does not provide CPU power management capabilities, or the processor
|
||||
just supports idle_standby, an idle-states node is not required.
|
||||
|
||||
===========================================
|
||||
4 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
[2] ARM Linux Kernel documentation - PSCI bindings
|
||||
Documentation/devicetree/bindings/arm/psci.yaml
|
||||
|
||||
[3] ARM Server Base System Architecture (SBSA)
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[4] ARM Architecture Reference Manuals
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
|
||||
Documentation/arm64/booting.rst
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: idle-states
|
||||
|
||||
entry-method:
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version.
|
||||
|
||||
On ARM v8 64-bit this property is required.
|
||||
On ARM 32-bit systems this property is optional
|
||||
|
||||
This assumes that the "enable-method" property is set to "psci" in the cpu
|
||||
node[6] that is responsible for setting up CPU idle management in the OS
|
||||
implementation.
|
||||
const: psci
|
||||
|
||||
patternProperties:
|
||||
"^(cpu|cluster)-":
|
||||
type: object
|
||||
description: |
|
||||
Each state node represents an idle state description and must be defined
|
||||
as follows.
|
||||
|
||||
The idle state entered by executing the wfi instruction (idle_standby
|
||||
SBSA,[3][4]) is considered standard on all ARM platforms and therefore
|
||||
must not be listed.
|
||||
|
||||
In addition to the properties listed above, a state node may require
|
||||
additional properties specific to the entry-method defined in the
|
||||
idle-states node. Please refer to the entry-method bindings
|
||||
documentation for properties definitions.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,idle-state
|
||||
|
||||
local-timer-stop:
|
||||
description:
|
||||
If present the CPU local timer control logic is
|
||||
lost on state entry, otherwise it is retained.
|
||||
type: boolean
|
||||
|
||||
entry-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to enter the idle state.
|
||||
|
||||
exit-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to exit the idle state.
|
||||
The exit-latency-us duration may be guaranteed only after
|
||||
entry-latency-us has passed.
|
||||
|
||||
min-residency-us:
|
||||
description:
|
||||
Minimum residency duration in microseconds, inclusive of preparation
|
||||
and entry, for this idle state to be considered worthwhile energy wise
|
||||
(refer to section 2 of this document for a complete description).
|
||||
|
||||
wakeup-latency-us:
|
||||
description: |
|
||||
Maximum delay between the signaling of a wake-up event and the CPU
|
||||
being able to execute normal code again. If omitted, this is assumed
|
||||
to be equal to:
|
||||
|
||||
entry-latency-us + exit-latency-us
|
||||
|
||||
It is important to supply this value on systems where the duration of
|
||||
PREP phase (see diagram 1, section 2) is non-neglibigle. In such
|
||||
systems entry-latency-us + exit-latency-us will exceed
|
||||
wakeup-latency-us by this duration.
|
||||
|
||||
idle-state-name:
|
||||
$ref: /schemas/types.yaml#definitions/string
|
||||
description:
|
||||
A string used as a descriptive name for the idle state.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- entry-latency-us
|
||||
- exit-latency-us
|
||||
- min-residency-us
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_RETENTION_0_0: cpu-retention-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_0: cluster-retention-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
|
||||
CPU_RETENTION_1_0: cpu-retention-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <90>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_1: cluster-retention-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <270>;
|
||||
wakeup-latency-us = <100>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <70>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <300>;
|
||||
wakeup-latency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <3500>;
|
||||
wakeup-latency-us = <1300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (ARM 32-bit, 8-cpu system, two clusters):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
cpu_sleep_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <200>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <400>;
|
||||
wakeup-latency-us = <250>;
|
||||
};
|
||||
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1500>;
|
||||
min-residency-us = <2500>;
|
||||
wakeup-latency-us = <1700>;
|
||||
};
|
||||
|
||||
cpu_sleep_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <900>;
|
||||
wakeup-latency-us = <600>;
|
||||
};
|
||||
|
||||
cluster_sleep_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <2000>;
|
||||
min-residency-us = <6500>;
|
||||
wakeup-latency-us = <2300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
19
sys/contrib/device-tree/Bindings/arm/intel,keembay.yaml
Normal file
19
sys/contrib/device-tree/Bindings/arm/intel,keembay.yaml
Normal file
@ -0,0 +1,19 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Keem Bay platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,keembay-evm
|
||||
- const: intel,keembay
|
||||
...
|
||||
22
sys/contrib/device-tree/Bindings/arm/intel-ixp4xx.yaml
Normal file
22
sys/contrib/device-tree/Bindings/arm/intel-ixp4xx.yaml
Normal file
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- linksys,nslu2
|
||||
- const: intel,ixp42x
|
||||
- items:
|
||||
- enum:
|
||||
- gateworks,gw2358
|
||||
- const: intel,ixp43x
|
||||
26
sys/contrib/device-tree/Bindings/arm/juno,scpi.txt
Normal file
26
sys/contrib/device-tree/Bindings/arm/juno,scpi.txt
Normal file
@ -0,0 +1,26 @@
|
||||
System Control and Power Interface (SCPI) Message Protocol
|
||||
(in addition to the standard binding in [0])
|
||||
|
||||
Juno SRAM and Shared Memory for SCPI
|
||||
------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
|
||||
|
||||
Each sub-node represents the reserved area for SCPI.
|
||||
|
||||
Required sub-node properties:
|
||||
- reg : The base offset and size of the reserved area with the SRAM
|
||||
- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
|
||||
shared memory on Juno platforms
|
||||
|
||||
Sensor bindings for the sensors based on SCPI Message Protocol
|
||||
--------------------------------------------------------------
|
||||
Required properties:
|
||||
- compatible : should be "arm,scpi-sensors".
|
||||
- #thermal-sensor-cells: should be set to 1.
|
||||
For Juno R0 and Juno R1 refer to [1] for the
|
||||
sensor identifiers
|
||||
|
||||
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
|
||||
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
|
||||
42
sys/contrib/device-tree/Bindings/arm/keystone/keystone.txt
Normal file
42
sys/contrib/device-tree/Bindings/arm/keystone/keystone.txt
Normal file
@ -0,0 +1,42 @@
|
||||
TI Keystone Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
|
||||
following properties.
|
||||
|
||||
Required properties:
|
||||
- compatible: All TI specific devices present in Keystone SOC should be in
|
||||
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
|
||||
type UART should use the specified compatible for those devices.
|
||||
|
||||
SoC families:
|
||||
|
||||
- Keystone 2 generic SoC:
|
||||
compatible = "ti,keystone"
|
||||
|
||||
SoCs:
|
||||
|
||||
- Keystone 2 Hawking/Kepler
|
||||
compatible = "ti,k2hk", "ti,keystone"
|
||||
- Keystone 2 Lamarr
|
||||
compatible = "ti,k2l", "ti,keystone"
|
||||
- Keystone 2 Edison
|
||||
compatible = "ti,k2e", "ti,keystone"
|
||||
- K2G
|
||||
compatible = "ti,k2g", "ti,keystone"
|
||||
|
||||
Boards:
|
||||
- Keystone 2 Hawking/Kepler EVM
|
||||
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
|
||||
|
||||
- Keystone 2 Lamarr EVM
|
||||
compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone"
|
||||
|
||||
- Keystone 2 Edison EVM
|
||||
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
|
||||
|
||||
- K2G EVM
|
||||
compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
|
||||
|
||||
- K2G Industrial Communication Engine EVM
|
||||
compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone"
|
||||
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common K3 TI-SCI bindings
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
||||
description: |
|
||||
The TI K3 family of SoCs usually have a central System Controller Processor
|
||||
that is responsible for managing various SoC-level resources like clocks,
|
||||
resets, interrupts etc. The communication with that processor is performed
|
||||
through the TI-SCI protocol.
|
||||
|
||||
Each specific device management node like a clock controller node, a reset
|
||||
controller node or an interrupt-controller node should define a common set
|
||||
of properties that enables them to implement the corresponding functionality
|
||||
over the TI-SCI protocol. The following are some of the common properties
|
||||
needed by such individual nodes. The required properties for each device
|
||||
management node is defined in the respective binding.
|
||||
|
||||
properties:
|
||||
ti,sci:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Should be a phandle to the TI-SCI System Controller node
|
||||
|
||||
ti,sci-dev-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Should contain the TI-SCI device id corresponding to the device. Please
|
||||
refer to the corresponding System Controller documentation for valid
|
||||
values for the desired device.
|
||||
|
||||
ti,sci-proc-ids:
|
||||
description: Should contain a single tuple of <proc_id host_id>.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: TI-SCI processor id for the remote processor device
|
||||
- description: TI-SCI host id to which processor control ownership
|
||||
should be transferred to
|
||||
86
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.txt
Normal file
86
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.txt
Normal file
@ -0,0 +1,86 @@
|
||||
Texas Instruments System Control Interface (TI-SCI) Message Protocol
|
||||
--------------------------------------------------------------------
|
||||
|
||||
Texas Instrument's processors including those belonging to Keystone generation
|
||||
of processors have separate hardware entity which is now responsible for the
|
||||
management of the System on Chip (SoC) system. These include various system
|
||||
level functions as well.
|
||||
|
||||
An example of such an SoC is K2G, which contains the system control hardware
|
||||
block called Power Management Micro Controller (PMMC). This hardware block is
|
||||
initialized early into boot process and provides services to Operating Systems
|
||||
on multiple processors including ones running Linux.
|
||||
|
||||
See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
|
||||
|
||||
TI-SCI controller Device Node:
|
||||
=============================
|
||||
|
||||
The TI-SCI node describes the Texas Instrument's System Controller entity node.
|
||||
This parent node may optionally have additional children nodes which describe
|
||||
specific functionality such as clocks, power domain, reset or additional
|
||||
functionality as may be required for the SoC. This hierarchy also describes the
|
||||
relationship between the TI-SCI parent node to the child node.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
|
||||
should be "ti,am654-sci" for for TI AM654 SoC
|
||||
- mbox-names:
|
||||
"rx" - Mailbox corresponding to receive path
|
||||
"tx" - Mailbox corresponding to transmit path
|
||||
|
||||
- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
|
||||
property should contain a phandle to the mailbox controller device
|
||||
node and an args specifier that will be the phandle to the intended
|
||||
sub-mailbox child node to be used for communication.
|
||||
|
||||
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
|
||||
about the generic mailbox controller and client driver bindings. Also see
|
||||
Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical
|
||||
controller that is used to communicate with this System controllers.
|
||||
|
||||
Optional Properties:
|
||||
-------------------
|
||||
- reg-names:
|
||||
debug_messages - Map the Debug message region
|
||||
- reg: register space corresponding to the debug_messages
|
||||
- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
|
||||
- ti,host-id: Integer value corresponding to the host ID assigned by Firmware
|
||||
for identification of host processing entities such as virtual
|
||||
machines
|
||||
|
||||
Example (K2G):
|
||||
-------------
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <2>;
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
|
||||
<&msgmgr &msgmgr_proxy_pmmc_tx>;
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x02921800 0x800>;
|
||||
};
|
||||
|
||||
|
||||
TI-SCI Client Device Node:
|
||||
=========================
|
||||
|
||||
Client nodes are maintained as children of the relevant TI-SCI device node.
|
||||
|
||||
Example (K2G):
|
||||
-------------
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
...
|
||||
|
||||
my_clk_node: clk_node {
|
||||
...
|
||||
...
|
||||
};
|
||||
|
||||
my_pd_node: pd_node {
|
||||
...
|
||||
...
|
||||
};
|
||||
};
|
||||
242
sys/contrib/device-tree/Bindings/arm/l2c2x0.yaml
Normal file
242
sys/contrib/device-tree/Bindings/arm/l2c2x0.yaml
Normal file
@ -0,0 +1,242 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM L2 Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description: |+
|
||||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
|
||||
PL220/PL310 and variants) based level 2 cache controller. All these various
|
||||
implementations of the L2 cache controller have compatible programming
|
||||
models (Note 1). Some of the properties that are just prefixed "cache-*" are
|
||||
taken from section 3.7.3 of the Devicetree Specification which can be found
|
||||
at:
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
||||
integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
|
||||
in the kernel at all.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
- items:
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- const: marvell,tauros3-cache
|
||||
- const: arm,pl310-cache
|
||||
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
cache-unified: true
|
||||
cache-size: true
|
||||
cache-sets: true
|
||||
cache-block-size: true
|
||||
cache-line-size: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,data-latency:
|
||||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,tag-latency:
|
||||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,dirty-latency:
|
||||
description: Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 8
|
||||
|
||||
arm,filter-ranges:
|
||||
description: <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
I/O coherent mode. Valid only when the arm,pl310-cache compatible
|
||||
string is used.
|
||||
type: boolean
|
||||
|
||||
interrupts:
|
||||
# Either a single combined interrupt or up to 9 individual interrupts
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
cache-id-part:
|
||||
description: cache id part number to be used if it is not present
|
||||
on hardware
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
wt-override:
|
||||
description: If present then L2 is forced to Write through mode
|
||||
type: boolean
|
||||
|
||||
arm,double-linefill:
|
||||
description: Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-incr:
|
||||
description: Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-wrap:
|
||||
description: Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-drop:
|
||||
description: Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-offset:
|
||||
description: Override prefetch offset value.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
|
||||
|
||||
arm,shared-override:
|
||||
description: The default behavior of the L220 or PL310 cache
|
||||
controllers with respect to the shareable attribute is to transform "normal
|
||||
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
||||
or "write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must
|
||||
be specified to indicate that such transforms are precluded.
|
||||
type: boolean
|
||||
|
||||
arm,parity-enable:
|
||||
description: enable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,parity-disable:
|
||||
description: disable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
marvell,ecc-enable:
|
||||
description: enable ECC protection on the L2 cache
|
||||
type: boolean
|
||||
|
||||
arm,outer-sync-disable:
|
||||
description: disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
|
||||
type: boolean
|
||||
|
||||
prefetch-data:
|
||||
description: |
|
||||
Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
prefetch-instr:
|
||||
description: |
|
||||
Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,dynamic-clock-gating:
|
||||
description: |
|
||||
L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,standby-mode:
|
||||
description: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,early-bresp-disable:
|
||||
description: Disable the CA9 optimization Early BRESP (PL310)
|
||||
type: boolean
|
||||
|
||||
arm,full-line-zero-disable:
|
||||
description: Disable the CA9 optimization Full line of zero
|
||||
write (PL310)
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cache-unified
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cache-controller@fff12000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x80000000 0x8000000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
interrupts = <45>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,16 @@
|
||||
Resume Control
|
||||
--------------
|
||||
Available on Marvell SOCs: 98DX3336 and 98DX4251
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be "marvell,98dx3336-resume-ctrl"
|
||||
|
||||
- reg: Should contain resume control registers location and length
|
||||
|
||||
Example:
|
||||
|
||||
resume@20980 {
|
||||
compatible = "marvell,98dx3336-resume-ctrl";
|
||||
reg = <0x20980 0x10>;
|
||||
};
|
||||
23
sys/contrib/device-tree/Bindings/arm/marvell/98dx3236.txt
Normal file
23
sys/contrib/device-tree/Bindings/arm/marvell/98dx3236.txt
Normal file
@ -0,0 +1,23 @@
|
||||
Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
|
||||
----------------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
|
||||
shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx3236"
|
||||
|
||||
In addition, boards using the Marvell 98DX3336 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx3336"
|
||||
|
||||
In addition, boards using the Marvell 98DX4251 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx4251"
|
||||
@ -0,0 +1,177 @@
|
||||
Marvell Armada AP80x System Controller
|
||||
======================================
|
||||
|
||||
The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
|
||||
7K/8K/931x SoCs. It contains system controllers, which provide several
|
||||
registers giving access to numerous features: clocks, pin-muxing and
|
||||
many other SoC configuration items. This DT binding allows to describe
|
||||
these system controllers.
|
||||
|
||||
For the top level node:
|
||||
- compatible: must be: "syscon", "simple-mfd";
|
||||
- reg: register area of the AP80x system controller
|
||||
|
||||
SYSTEM CONTROLLER 0
|
||||
===================
|
||||
|
||||
Clocks:
|
||||
-------
|
||||
|
||||
|
||||
The Device Tree node representing the AP806/AP807 system controller
|
||||
provides a number of clocks:
|
||||
|
||||
- 0: reference clock of CPU cluster 0
|
||||
- 1: reference clock of CPU cluster 1
|
||||
- 2: fixed PLL at 1200 Mhz
|
||||
- 3: MSS clock, derived from the fixed PLL
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be one of:
|
||||
* "marvell,ap806-clock"
|
||||
* "marvell,ap807-clock"
|
||||
- #clock-cells: must be set to 1
|
||||
|
||||
Pinctrl:
|
||||
--------
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible must be "marvell,ap806-pinctrl",
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, sdio(clk), spi0(clk)
|
||||
mpp1 1 gpio, sdio(cmd), spi0(miso)
|
||||
mpp2 2 gpio, sdio(d0), spi0(mosi)
|
||||
mpp3 3 gpio, sdio(d1), spi0(cs0n)
|
||||
mpp4 4 gpio, sdio(d2), i2c0(sda)
|
||||
mpp5 5 gpio, sdio(d3), i2c0(sdk)
|
||||
mpp6 6 gpio, sdio(ds)
|
||||
mpp7 7 gpio, sdio(d4), uart1(rxd)
|
||||
mpp8 8 gpio, sdio(d5), uart1(txd)
|
||||
mpp9 9 gpio, sdio(d6), spi0(cs1n)
|
||||
mpp10 10 gpio, sdio(d7)
|
||||
mpp11 11 gpio, uart0(txd)
|
||||
mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
|
||||
mpp13 13 gpio
|
||||
mpp14 14 gpio
|
||||
mpp15 15 gpio
|
||||
mpp16 16 gpio
|
||||
mpp17 17 gpio
|
||||
mpp18 18 gpio
|
||||
mpp19 19 gpio, uart0(rxd), sdio(pw_off)
|
||||
|
||||
GPIO:
|
||||
-----
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-8k-gpio"
|
||||
|
||||
- offset: offset address inside the syscon block
|
||||
|
||||
Example:
|
||||
ap_syscon: system-controller@6f4000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f4000 0x1000>;
|
||||
|
||||
ap_clk: clock {
|
||||
compatible = "marvell,ap806-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ap_pinctrl: pinctrl {
|
||||
compatible = "marvell,ap806-pinctrl";
|
||||
};
|
||||
|
||||
ap_gpio: gpio {
|
||||
compatible = "marvell,armada-8k-gpio";
|
||||
offset = <0x1040>;
|
||||
ngpios = <19>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&ap_pinctrl 0 0 19>;
|
||||
};
|
||||
};
|
||||
|
||||
SYSTEM CONTROLLER 1
|
||||
===================
|
||||
|
||||
Thermal:
|
||||
--------
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal*.yaml
|
||||
|
||||
The thermal IP can probe the temperature all around the processor. It
|
||||
may feature several channels, each of them wired to one sensor.
|
||||
|
||||
It is possible to setup an overheat interrupt by giving at least one
|
||||
critical point to any subnode of the thermal-zone node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
* marvell,armada-ap806-thermal
|
||||
- reg: register range associated with the thermal functions.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: overheat interrupt handle. Should point to line 18 of the
|
||||
SEI irqchip. See interrupt-controller/interrupts.txt
|
||||
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
|
||||
to this IP and represents the channel ID. There is one sensor per
|
||||
channel. O refers to the thermal IP internal channel, while positive
|
||||
IDs refer to each CPU.
|
||||
|
||||
Example:
|
||||
ap_syscon1: system-controller@6f8000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f8000 0x1000>;
|
||||
|
||||
ap_thermal: thermal-sensor@80 {
|
||||
compatible = "marvell,armada-ap806-thermal";
|
||||
reg = <0x80 0x10>;
|
||||
interrupt-parent = <&sei>;
|
||||
interrupts = <18>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Cluster clocks:
|
||||
---------------
|
||||
|
||||
Device Tree Clock bindings for cluster clock of Marvell
|
||||
AP806/AP807. Each cluster contain up to 2 CPUs running at the same
|
||||
frequency.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
* "marvell,ap806-cpu-clock"
|
||||
* "marvell,ap807-cpu-clock"
|
||||
- #clock-cells : should be set to 1.
|
||||
|
||||
- clocks : shall be the input parent clock(s) phandle for the clock
|
||||
(one per cluster)
|
||||
|
||||
- reg: register range associated with the cluster clocks
|
||||
|
||||
ap_syscon1: system-controller@6f8000 {
|
||||
compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
|
||||
reg = <0x6f8000 0x1000>;
|
||||
|
||||
cpu_clk: clock-cpu@278 {
|
||||
compatible = "marvell,ap806-cpu-clock";
|
||||
clocks = <&ap_clk 0>, <&ap_clk 1>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0x278 0xa30>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,21 @@
|
||||
Power Management Service Unit(PMSU)
|
||||
-----------------------------------
|
||||
Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of:
|
||||
- "marvell,armada-370-pmsu" for Armada 370 or Armada XP
|
||||
- "marvell,armada-380-pmsu" for Armada 38x
|
||||
- "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now
|
||||
deprecated and will be removed
|
||||
|
||||
- reg: Should contain PMSU registers location and length.
|
||||
|
||||
Example:
|
||||
|
||||
armada-370-xp-pmsu@22000 {
|
||||
compatible = "marvell,armada-370-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
@ -0,0 +1,24 @@
|
||||
Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Armada 370 and Armada XP families
|
||||
shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada-370-xp"
|
||||
|
||||
In addition, boards using the Marvell Armada 370 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada370"
|
||||
|
||||
In addition, boards using the Marvell Armada XP SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp"
|
||||
|
||||
@ -0,0 +1,9 @@
|
||||
Marvell Armada 375 Platforms Device Tree Bindings
|
||||
-------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Armada 375 family shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada375"
|
||||
58
sys/contrib/device-tree/Bindings/arm/marvell/armada-37xx.txt
Normal file
58
sys/contrib/device-tree/Bindings/arm/marvell/armada-37xx.txt
Normal file
@ -0,0 +1,58 @@
|
||||
Marvell Armada 37xx Platforms Device Tree Bindings
|
||||
--------------------------------------------------
|
||||
|
||||
Boards using a SoC of the Marvell Armada 37xx family must carry the
|
||||
following root node property:
|
||||
|
||||
- compatible: must contain "marvell,armada3710"
|
||||
|
||||
In addition, boards using the Marvell Armada 3720 SoC shall have the
|
||||
following property before the previous one:
|
||||
|
||||
- compatible: must contain "marvell,armada3720"
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
|
||||
|
||||
|
||||
Power management
|
||||
----------------
|
||||
|
||||
For power management (particularly DVFS and AVS), the North Bridge
|
||||
Power Management component is needed:
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "marvell,armada-3700-nb-pm", "syscon";
|
||||
- reg : the register start and length for the North Bridge
|
||||
Power Management
|
||||
|
||||
Example:
|
||||
|
||||
nb_pm: syscon@14000 {
|
||||
compatible = "marvell,armada-3700-nb-pm", "syscon";
|
||||
reg = <0x14000 0x60>;
|
||||
}
|
||||
|
||||
AVS
|
||||
---
|
||||
|
||||
For AVS an other component is needed:
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "marvell,armada-3700-avs", "syscon";
|
||||
- reg : the register start and length for the AVS
|
||||
|
||||
Example:
|
||||
avs: avs@11500 {
|
||||
compatible = "marvell,armada-3700-avs", "syscon";
|
||||
reg = <0x11500 0x40>;
|
||||
}
|
||||
|
||||
|
||||
CZ.NIC's Turris Mox SOHO router Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
Required root node property:
|
||||
|
||||
- compatible: must contain "cznic,turris-mox"
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user