Import the updated devicetree files from
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
This commit is contained in:
parent
235ad806ee
commit
c7716441be
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=303380 svn path=/vendor/device-tree/devicetree-965f3718/; revision=303381; tag=vendor/device-tree/devicetree-965f3718
@ -2,7 +2,7 @@
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||||
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The ARC HS can be configured with a pipeline performance monitor for counting
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CPU and cache events like cache misses and hits. Like conventional PCT there
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are 100+ hardware conditions dynamically mapped to upto 32 counters.
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are 100+ hardware conditions dynamically mapped to up to 32 counters.
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It also supports overflow interrupts.
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Required properties:
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|
7
Bindings/arc/eznps.txt
Normal file
7
Bindings/arc/eznps.txt
Normal file
@ -0,0 +1,7 @@
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EZchip NPS Network Processor Platforms Device Tree Bindings
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---------------------------------------------------------------------------
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Appliance main board with NPS400 ASIC.
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Required root node properties:
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- compatible = "ezchip,arc-nps";
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@ -2,7 +2,7 @@
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The ARC700 can be configured with a pipeline performance monitor for counting
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CPU and cache events like cache misses and hits. Like conventional PCT there
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are 100+ hardware conditions dynamically mapped to upto 32 counters
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are 100+ hardware conditions dynamically mapped to up to 32 counters
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Note that:
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* The ARC 700 PCT does not support interrupts; although HW events may be
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|
99
Bindings/arm/altera/socfpga-eccmgr.txt
Normal file
99
Bindings/arm/altera/socfpga-eccmgr.txt
Normal file
@ -0,0 +1,99 @@
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Altera SoCFPGA ECC Manager
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This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Cyclone5 and Arria5 ECC Manager
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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On Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-ocram-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- iram : phandle to On-Chip RAM definition.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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Example:
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eccmgr: eccmgr@ffd08140 {
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compatible = "altr,socfpga-ecc-manager";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l2-ecc@ffd08140 {
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compatible = "altr,socfpga-l2-ecc";
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reg = <0xffd08140 0x4>;
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interrupts = <0 36 1>, <0 37 1>;
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};
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ocram-ecc@ffd08144 {
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compatible = "altr,socfpga-ocram-ecc";
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reg = <0xffd08144 0x4>;
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iram = <&ocram>;
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interrupts = <0 178 1>, <0 179 1>;
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};
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};
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Arria10 SoCFPGA ECC Manager
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The Arria10 SoC ECC Manager handles the IRQs for each peripheral
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in a shared register instead of individual IRQs like the Cyclone5
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and Arria5. Therefore the device tree is different as well.
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ecc-manager"
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- altr,sysgr-syscon : phandle to Arria10 System Manager Block
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containing the ECC manager registers.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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Example:
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eccmgr: eccmgr@ffd06000 {
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compatible = "altr,socfpga-a10-ecc-manager";
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altr,sysmgr-syscon = <&sysmgr>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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};
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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};
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};
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@ -13,8 +13,18 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8b";
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Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson-gxbb";
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Board compatible values:
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- "geniatech,atv1200" (Meson6)
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- "minix,neo-x8" (Meson8)
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- "tronfy,mxq" (Meson8b)
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- "hardkernel,odroid-c1" (Meson8b)
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- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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@ -93,6 +93,14 @@ Required nodes:
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a core-module with regs and the compatible strings
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"arm,core-module-versatile", "syscon"
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Optional nodes:
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- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
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board mounted, this has a separate system controller that is
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defined in this node.
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Required properties:
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compatible = "arm,versatile-ib2-syscon", "syscon"
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ARM RealView Boards
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-------------------
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The RealView boards cover tailored evaluation boards that are used to explore
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@ -123,7 +131,9 @@ Required nodes:
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- syscon: some subnode of the RealView SoC node must be a
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system controller node pointing to the control registers,
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with the compatible string set to one of these tuples:
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with the compatible string set to one of these:
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"arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
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"arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
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"arm,realview-eb-syscon", "syscon"
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"arm,realview-pb1176-syscon", "syscon"
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"arm,realview-pb11mp-syscon", "syscon"
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@ -180,6 +190,7 @@ described under the RS1 memory mapping.
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Required properties (in root node):
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compatible = "arm,juno"; /* For Juno r0 board */
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compatible = "arm,juno-r1"; /* For Juno r1 board */
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compatible = "arm,juno-r2"; /* For Juno r2 board */
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Required nodes:
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The description for the board must include:
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@ -41,6 +41,10 @@ compatible: must be one of:
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- "atmel,sama5d43"
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- "atmel,sama5d44"
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Chipid required properties:
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- compatible: Should be "atmel,sama5d2-chipid"
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- reg : Should contain registers location and length
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PIT Timer required properties:
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- compatible: Should be "atmel,at91sam9260-pit"
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- reg: Should contain registers location and length
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@ -147,6 +151,65 @@ Example:
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clocks = <&clk32k>;
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};
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SHDWC SAMA5D2-Compatible Shutdown Controller
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1) shdwc node
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required properties:
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- compatible: should be "atmel,sama5d2-shdwc".
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- reg: should contain registers location and length
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- clocks: phandle to input clock.
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- #address-cells: should be one. The cell is the wake-up input index.
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- #size-cells: should be zero.
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optional properties:
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- debounce-delay-us: minimum wake-up inputs debouncer period in
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microseconds. It's usually a board-related property.
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- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
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The node contains child nodes for each wake-up input that the platform uses.
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2) input nodes
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Wake-up input nodes are usually described in the "board" part of the Device
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Tree. Note also that input 0 is linked to the wake-up pin and is frequently
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used.
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Required properties:
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- reg: should contain the wake-up input index [0 - 15].
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Optional properties:
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- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
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by the child, forces the wake-up of the core power supply on a high level.
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The default is to be active low.
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Example:
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On the SoC side:
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shdwc@f8048010 {
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compatible = "atmel,sama5d2-shdwc";
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reg = <0xf8048010 0x10>;
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clocks = <&clk32k>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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};
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||||
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On the board side:
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shdwc@f8048010 {
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debounce-delay-us = <976>;
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input@0 {
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reg = <0>;
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};
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input@1 {
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reg = <1>;
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atmel,wakeup-active-high;
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};
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};
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Special Function Registers (SFR)
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||||
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||||
Special Function Registers (SFR) manage specific aspects of the integrated
|
||||
@ -155,7 +218,7 @@ elsewhere.
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||||
|
||||
required properties:
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||||
- compatible: Should be "atmel,<chip>-sfr", "syscon".
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<chip> can be "sama5d3" or "sama5d4".
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<chip> can be "sama5d3", "sama5d4" or "sama5d2".
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||||
- reg: Should contain registers location and length
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||||
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||||
sfr@f0038000 {
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||||
|
29
Bindings/arm/axis.txt
Normal file
29
Bindings/arm/axis.txt
Normal file
@ -0,0 +1,29 @@
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Axis Communications AB
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ARTPEC series SoC Device Tree Bindings
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||||
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ARTPEC-6 ARM SoC
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================
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||||
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Required root node properties:
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- compatible = "axis,artpec6";
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||||
|
||||
ARTPEC-6 System Controller
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||||
--------------------------
|
||||
|
||||
The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
|
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and resets.
|
||||
|
||||
Required properties:
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- compatible: "axis,artpec6-syscon", "syscon"
|
||||
- reg: Address and length of the register bank.
|
||||
|
||||
Example:
|
||||
syscon {
|
||||
compatible = "axis,artpec6-syscon", "syscon";
|
||||
reg = <0xf8000000 0x48>;
|
||||
};
|
||||
|
||||
ARTPEC-6 Development board:
|
||||
---------------------------
|
||||
Required root node properties:
|
||||
- compatible = "axis,artpec6-dev-board", "axis,artpec6";
|
10
Bindings/arm/bcm/brcm,vulcan-soc.txt
Normal file
10
Bindings/arm/bcm/brcm,vulcan-soc.txt
Normal file
@ -0,0 +1,10 @@
|
||||
Broadcom Vulcan device tree bindings
|
||||
------------------------------------
|
||||
|
||||
Boards with Broadcom Vulcan shall have the following root property:
|
||||
|
||||
Broadcom Vulcan Evaluation Board:
|
||||
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
|
||||
|
||||
Generic Vulcan board:
|
||||
compatible = "brcm,vulcan-soc";
|
@ -34,6 +34,7 @@ specific to ARM.
|
||||
Definition: must contain one of the following:
|
||||
"arm,cci-400"
|
||||
"arm,cci-500"
|
||||
"arm,cci-550"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
@ -99,8 +100,9 @@ specific to ARM.
|
||||
"arm,cci-400-pmu,r0"
|
||||
"arm,cci-400-pmu,r1"
|
||||
"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
|
||||
secure acces to CCI registers
|
||||
secure access to CCI registers
|
||||
"arm,cci-500-pmu,r0"
|
||||
"arm,cci-550-pmu,r0"
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: Integer cells. A register entry, expressed
|
||||
|
@ -19,6 +19,7 @@ its hardware characteristcs.
|
||||
- "arm,coresight-etm3x", "arm,primecell";
|
||||
- "arm,coresight-etm4x", "arm,primecell";
|
||||
- "qcom,coresight-replicator1x", "arm,primecell";
|
||||
- "arm,coresight-stm", "arm,primecell"; [1]
|
||||
|
||||
* reg: physical base address and length of the register
|
||||
set(s) of the component.
|
||||
@ -36,6 +37,14 @@ its hardware characteristcs.
|
||||
layout using the generic DT graph presentation found in
|
||||
"bindings/graph.txt".
|
||||
|
||||
* Additional required properties for System Trace Macrocells (STM):
|
||||
* reg: along with the physical base address and length of the register
|
||||
set as described above, another entry is required to describe the
|
||||
mapping of the extended stimulus port area.
|
||||
|
||||
* reg-names: the only acceptable values are "stm-base" and
|
||||
"stm-stimulus-base", each corresponding to the areas defined in "reg".
|
||||
|
||||
* Required properties for devices that don't show up on the AMBA bus, such as
|
||||
non-configurable replicators:
|
||||
|
||||
@ -202,3 +211,22 @@ Example:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
4. STM
|
||||
stm@20100000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x20100000 0 0x1000>,
|
||||
<0 0x28000000 0 0x180000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
port {
|
||||
stm_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
[1]. There is currently two version of STM: STM32 and STM500. Both
|
||||
have the same HW interface and as such don't need an explicit binding name.
|
||||
|
@ -167,6 +167,7 @@ nodes to be present and contain the properties described below.
|
||||
"arm,cortex-r5"
|
||||
"arm,cortex-r7"
|
||||
"brcm,brahma-b15"
|
||||
"brcm,vulcan"
|
||||
"cavium,thunder"
|
||||
"faraday,fa526"
|
||||
"intel,sa110"
|
||||
@ -178,6 +179,7 @@ nodes to be present and contain the properties described below.
|
||||
"marvell,sheeva-v5"
|
||||
"nvidia,tegra132-denver"
|
||||
"qcom,krait"
|
||||
"qcom,kryo"
|
||||
"qcom,scorpion"
|
||||
- enable-method
|
||||
Value type: <stringlist>
|
||||
@ -190,7 +192,6 @@ nodes to be present and contain the properties described below.
|
||||
can be one of:
|
||||
"allwinner,sun6i-a31"
|
||||
"allwinner,sun8i-a23"
|
||||
"arm,psci"
|
||||
"arm,realview-smp"
|
||||
"brcm,bcm-nsp-smp"
|
||||
"brcm,brahma-b15"
|
||||
@ -250,7 +251,7 @@ nodes to be present and contain the properties described below.
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A u32 value that represents the running time dynamic
|
||||
power coefficient in units of mW/MHz/uVolt^2. The
|
||||
power coefficient in units of mW/MHz/uV^2. The
|
||||
coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
|
@ -135,6 +135,10 @@ LS1043A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
|
||||
|
||||
LS1043A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
|
||||
|
||||
LS2080A ARMv8 based Simulator model
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
|
||||
|
@ -11,43 +11,9 @@ QEMU exposes the control and data register to ARM guests as memory mapped
|
||||
registers; their location is communicated to the guest's UEFI firmware in the
|
||||
DTB that QEMU places at the bottom of the guest's DRAM.
|
||||
|
||||
The guest writes a selector value (a key) to the selector register, and then
|
||||
can read the corresponding data (produced by QEMU) via the data register. If
|
||||
the selected entry is writable, the guest can rewrite it through the data
|
||||
register.
|
||||
The authoritative guest-side hardware interface documentation to the fw_cfg
|
||||
device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
|
||||
|
||||
The selector register takes keys in big endian byte order.
|
||||
|
||||
The data register allows accesses with 8, 16, 32 and 64-bit width (only at
|
||||
offset 0 of the register). Accesses larger than a byte are interpreted as
|
||||
arrays, bundled together only for better performance. The bytes constituting
|
||||
such a word, in increasing address order, correspond to the bytes that would
|
||||
have been transferred by byte-wide accesses in chronological order.
|
||||
|
||||
The interface allows guest firmware to download various parameters and blobs
|
||||
that affect how the firmware works and what tables it installs for the guest
|
||||
OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and
|
||||
initrd images for direct kernel booting, virtual machine UUID, SMP information,
|
||||
virtual NUMA topology, and so on.
|
||||
|
||||
The authoritative registry of the valid selector values and their meanings is
|
||||
the QEMU source code; the structure of the data blobs corresponding to the
|
||||
individual key values is also defined in the QEMU source code.
|
||||
|
||||
The presence of the registers can be verified by selecting the "signature" blob
|
||||
with key 0x0000, and reading four bytes from the data register. The returned
|
||||
signature is "QEMU".
|
||||
|
||||
The outermost protocol (involving the write / read sequences of the control and
|
||||
data registers) is expected to be versioned, and/or described by feature bits.
|
||||
The interface revision / feature bitmap can be retrieved with key 0x0001. The
|
||||
blob to be read from the data register has size 4, and it is to be interpreted
|
||||
as a uint32_t value in little endian byte order. The current value
|
||||
(corresponding to the above outer protocol) is zero.
|
||||
|
||||
The guest kernel is not expected to use these registers (although it is
|
||||
certainly allowed to); the device tree bindings are documented here because
|
||||
this is where device tree bindings reside in general.
|
||||
|
||||
Required properties:
|
||||
|
||||
|
@ -1,29 +1,33 @@
|
||||
Hisilicon Platforms Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
Hi6220 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi6220";
|
||||
|
||||
Hi4511 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi3620-hi4511";
|
||||
|
||||
HiP04 D01 Board
|
||||
Hi6220 SoC
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip04-d01";
|
||||
|
||||
HiP01 ca9x2 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip01-ca9x2";
|
||||
- compatible = "hisilicon,hi6220";
|
||||
|
||||
HiKey Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
|
||||
|
||||
HiP01 ca9x2 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip01-ca9x2";
|
||||
|
||||
HiP04 D01 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip04-d01";
|
||||
|
||||
HiP05 D02 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip05-d02";
|
||||
|
||||
HiP06 D03 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip06-d03";
|
||||
|
||||
Hisilicon system controller
|
||||
|
||||
Required properties:
|
||||
|
@ -22,6 +22,8 @@ SoCs:
|
||||
compatible = "ti,k2l", "ti,keystone"
|
||||
- Keystone 2 Edison
|
||||
compatible = "ti,k2e", "ti,keystone"
|
||||
- K2G
|
||||
compatible = "ti,k2g", "ti,keystone"
|
||||
|
||||
Boards:
|
||||
- Keystone 2 Hawking/Kepler EVM
|
||||
@ -32,3 +34,6 @@ Boards:
|
||||
|
||||
- Keystone 2 Edison EVM
|
||||
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
|
||||
|
||||
- K2G EVM
|
||||
compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
|
||||
|
@ -84,6 +84,12 @@ Optional properties:
|
||||
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
|
||||
Example:
|
||||
|
||||
|
35
Bindings/arm/marvell/ap806-system-controller.txt
Normal file
35
Bindings/arm/marvell/ap806-system-controller.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Marvell Armada AP806 System Controller
|
||||
======================================
|
||||
|
||||
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
|
||||
SoCs. It contains a system controller, which provides a number
|
||||
registers giving access to numerous features: clocks, pin-muxing and
|
||||
many other SoC configuration items. This DT binding allows to describe
|
||||
this system controller.
|
||||
|
||||
The Device Tree node representing the AP806 system controller provides
|
||||
a number of clocks:
|
||||
|
||||
- 0: clock of CPU cluster 0
|
||||
- 1: clock of CPU cluster 1
|
||||
- 2: fixed PLL at 1200 Mhz
|
||||
- 3: MSS clock, derived from the fixed PLL
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"marvell,ap806-system-controller", "syscon"
|
||||
- reg: register area of the AP806 system controller
|
||||
- #clock-cells: must be set to 1
|
||||
- clock-output-names: must be defined to:
|
||||
"ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
|
||||
|
||||
Example:
|
||||
|
||||
syscon: system-controller@6f4000 {
|
||||
compatible = "marvell,ap806-system-controller", "syscon";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
|
||||
"ap-fixed", "ap-mss";
|
||||
reg = <0x6f4000 0x1000>;
|
||||
};
|
16
Bindings/arm/marvell/armada-37xx.txt
Normal file
16
Bindings/arm/marvell/armada-37xx.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Marvell Armada 37xx Platforms Device Tree Bindings
|
||||
--------------------------------------------------
|
||||
|
||||
Boards using a SoC of the Marvell Armada 37xx family must carry the
|
||||
following root node property:
|
||||
|
||||
- compatible: must contain "marvell,armada3710"
|
||||
|
||||
In addition, boards using the Marvell Armada 3720 SoC shall have the
|
||||
following property before the previous one:
|
||||
|
||||
- compatible: must contain "marvell,armada3720"
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
|
24
Bindings/arm/marvell/armada-7k-8k.txt
Normal file
24
Bindings/arm/marvell/armada-7k-8k.txt
Normal file
@ -0,0 +1,24 @@
|
||||
Marvell Armada 7K/8K Platforms Device Tree Bindings
|
||||
---------------------------------------------------
|
||||
|
||||
Boards using a SoC of the Marvell Armada 7K or 8K families must carry
|
||||
the following root node property:
|
||||
|
||||
- compatible, with one of the following values:
|
||||
|
||||
- "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 7020
|
||||
|
||||
- "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 7040
|
||||
|
||||
- "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 8020
|
||||
|
||||
- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 8040
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,armada7040-db", "marvell,armada7040",
|
||||
"marvell,armada-ap806-quad", "marvell,armada-ap806";
|
83
Bindings/arm/marvell/cp110-system-controller0.txt
Normal file
83
Bindings/arm/marvell/cp110-system-controller0.txt
Normal file
@ -0,0 +1,83 @@
|
||||
Marvell Armada CP110 System Controller 0
|
||||
========================================
|
||||
|
||||
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
|
||||
SoCs. It contains two sets of system control registers, System
|
||||
Controller 0 and System Controller 1. This Device Tree binding allows
|
||||
to describe the first system controller, which provides registers to
|
||||
configure various aspects of the SoC.
|
||||
|
||||
The Device Tree node representing this System Controller 0 provides a
|
||||
number of clocks:
|
||||
|
||||
- a set of core clocks
|
||||
- a set of gatable clocks
|
||||
|
||||
Those clocks can be referenced by other Device Tree nodes using two
|
||||
cells:
|
||||
- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
|
||||
gatable clocks.
|
||||
- The second cell identifies the particular core clock or gatable
|
||||
clocks.
|
||||
|
||||
The following clocks are available:
|
||||
- Core clocks
|
||||
- 0 0 APLL
|
||||
- 0 1 PPv2 core
|
||||
- 0 2 EIP
|
||||
- 0 3 Core
|
||||
- 0 4 NAND core
|
||||
- Gatable clocks
|
||||
- 1 0 Audio
|
||||
- 1 1 Comm Unit
|
||||
- 1 2 NAND
|
||||
- 1 3 PPv2
|
||||
- 1 4 SDIO
|
||||
- 1 5 MG Domain
|
||||
- 1 6 MG Core
|
||||
- 1 7 XOR1
|
||||
- 1 8 XOR0
|
||||
- 1 9 GOP DP
|
||||
- 1 11 PCIe x1 0
|
||||
- 1 12 PCIe x1 1
|
||||
- 1 13 PCIe x4
|
||||
- 1 14 PCIe / XOR
|
||||
- 1 15 SATA
|
||||
- 1 16 SATA USB
|
||||
- 1 17 Main
|
||||
- 1 18 SD/MMC
|
||||
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
|
||||
- 1 22 USB3H0
|
||||
- 1 23 USB3H1
|
||||
- 1 24 USB3 Device
|
||||
- 1 25 EIP150
|
||||
- 1 26 EIP197
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"marvell,cp110-system-controller0", "syscon";
|
||||
- reg: register area of the CP110 system controller 0
|
||||
- #clock-cells: must be set to 2
|
||||
- core-clock-output-names must be set to:
|
||||
"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
|
||||
- gate-clock-output-names must be set to:
|
||||
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
|
||||
Example:
|
||||
|
||||
cpm_syscon0: system-controller@440000 {
|
||||
compatible = "marvell,cp110-system-controller0", "syscon";
|
||||
reg = <0x440000 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
|
||||
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
};
|
@ -19,9 +19,12 @@ SoC. Currently known SoC compatibles are:
|
||||
And in addition, the compatible shall be extended with the specific
|
||||
board. Currently known boards are:
|
||||
|
||||
"buffalo,linkstation-lsqvl"
|
||||
"buffalo,linkstation-lsvl"
|
||||
"buffalo,linkstation-lswsxl"
|
||||
"buffalo,linkstation-lswxl"
|
||||
"buffalo,linkstation-lswvl"
|
||||
"buffalo,lschlv2"
|
||||
"buffalo,lswvl"
|
||||
"buffalo,lswxl"
|
||||
"buffalo,lsxhl"
|
||||
"buffalo,lsxl"
|
||||
"cloudengines,pogo02"
|
@ -11,6 +11,7 @@ compatible: Must contain one of
|
||||
"mediatek,mt6589"
|
||||
"mediatek,mt6592"
|
||||
"mediatek,mt6795"
|
||||
"mediatek,mt7623"
|
||||
"mediatek,mt8127"
|
||||
"mediatek,mt8135"
|
||||
"mediatek,mt8173"
|
||||
@ -33,6 +34,9 @@ Supported boards:
|
||||
- Evaluation board for MT6795(Helio X10):
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
|
||||
- Evaluation board for MT7623:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
||||
- MTK mt8127 tablet moose EVB:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
|
||||
|
@ -42,7 +42,8 @@ Examples:
|
||||
Consumer:
|
||||
========
|
||||
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
|
||||
Documentation/devicetree/bindings/arm/gic.txt for further details.
|
||||
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
|
||||
further details.
|
||||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
interrupts = <GIC_SPI request_number interrupt_level>
|
||||
|
@ -23,6 +23,7 @@ Optional properties:
|
||||
during suspend.
|
||||
- ti,no-reset-on-init: When present, the module should not be reset at init
|
||||
- ti,no-idle-on-init: When present, the module should not be idled at init
|
||||
- ti,no-idle: When present, the module is never allowed to idle.
|
||||
|
||||
Example:
|
||||
|
||||
@ -132,6 +133,9 @@ Boards:
|
||||
- AM335X Bone : Low cost community board
|
||||
compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
|
||||
|
||||
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
|
||||
compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3"
|
||||
|
||||
- AM335X OrionLXm : Substation Automation Platform
|
||||
compatible = "novatech,am335x-lxm", "ti,am33xx"
|
||||
|
||||
@ -154,7 +158,7 @@ Boards:
|
||||
compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM43x EPOS EVM
|
||||
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
|
||||
compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x"
|
||||
|
||||
- AM437x GP EVM
|
||||
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
|
||||
@ -168,6 +172,9 @@ Boards:
|
||||
- AM57XX SBC-AM57x
|
||||
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM5728 IDK
|
||||
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
|
9
Bindings/arm/oxnas.txt
Normal file
9
Bindings/arm/oxnas.txt
Normal file
@ -0,0 +1,9 @@
|
||||
Oxford Semiconductor OXNAS SoCs Family device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the OX810SE SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "oxsemi,ox810se"
|
||||
|
||||
Board compatible values:
|
||||
- "wd,mbwe" (OX810SE)
|
@ -22,6 +22,8 @@ Required properties:
|
||||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
"brcm,vulcan-pmu"
|
||||
"cavium,thunder-pmu"
|
||||
"qcom,scorpion-pmu"
|
||||
"qcom,scorpion-mp-pmu"
|
||||
"qcom,krait-pmu"
|
||||
@ -46,6 +48,16 @@ Optional properties:
|
||||
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
||||
events.
|
||||
|
||||
- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
|
||||
(SDER) is accessible. This will cause the driver to do
|
||||
any setup required that is only possible in ARMv7 secure
|
||||
state. If not present the ARMv7 SDER will not be touched,
|
||||
which means the PMU may fail to operate unless external
|
||||
code (bootloader or security monitor) has performed the
|
||||
appropriate initialisation. Note that this property is
|
||||
not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
|
||||
in Non-secure state.
|
||||
|
||||
Example:
|
||||
|
||||
pmu {
|
||||
|
51
Bindings/arm/qcom.txt
Normal file
51
Bindings/arm/qcom.txt
Normal file
@ -0,0 +1,51 @@
|
||||
QCOM device tree bindings
|
||||
-------------------------
|
||||
|
||||
Some qcom based bootloaders identify the dtb blob based on a set of
|
||||
device properties like SoC and platform and revisions of those components.
|
||||
To support this scheme, we encode this information into the board compatible
|
||||
string.
|
||||
|
||||
Each board must specify a top-level board compatible string with the following
|
||||
format:
|
||||
|
||||
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
|
||||
|
||||
The 'SoC' and 'board' elements are required. All other elements are optional.
|
||||
|
||||
The 'SoC' element must be one of the following strings:
|
||||
|
||||
apq8016
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
msm8916
|
||||
msm8974
|
||||
msm8996
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
liquid
|
||||
dragonboard
|
||||
mtp
|
||||
sbc
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
as v1. If all versions of the 'board_version' elements match, then a
|
||||
wildcard '*' should be used, e.g. 'v*'.
|
||||
|
||||
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
|
||||
|
||||
Examples:
|
||||
|
||||
"qcom,msm8916-v1-cdp-pm8916-v2.1"
|
||||
|
||||
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
|
||||
2.1.
|
||||
|
||||
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
|
||||
|
||||
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
|
||||
foundry 2.
|
@ -39,6 +39,10 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- GeekBuying GeekBox:
|
||||
Required root node properties:
|
||||
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
|
||||
|
||||
- Google Brain (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
@ -87,6 +91,10 @@ Rockchip platforms device tree bindings
|
||||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
- mqmaker MiQi:
|
||||
Required root node properties:
|
||||
- compatible = "mqmaker,miqi", "rockchip,rk3288";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
|
||||
@ -97,4 +105,8 @@ Rockchip platforms device tree bindings
|
||||
|
||||
- Rockchip RK3228 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
- Rockchip RK3399 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
|
||||
|
@ -2,6 +2,8 @@
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
|
||||
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
|
@ -6,4 +6,4 @@ few properties of different peripheral controllers.
|
||||
misc node required properties:
|
||||
|
||||
- compatible Should be "st,spear1340-misc", "syscon".
|
||||
- reg: Address range of misc space upto 8K
|
||||
- reg: Address range of misc space up to 8K
|
||||
|
@ -11,5 +11,6 @@ using one of the following compatible strings:
|
||||
allwinner,sun7i-a20
|
||||
allwinner,sun8i-a23
|
||||
allwinner,sun8i-a33
|
||||
allwinner,sun8i-a83t
|
||||
allwinner,sun8i-h3
|
||||
allwinner,sun9i-a80
|
||||
|
@ -1,16 +1,20 @@
|
||||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
== Power Management Controller Node ==
|
||||
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
|
||||
must contain "nvidia,tegra30-pmc". For Tegra114, must contain
|
||||
"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
|
||||
Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
|
||||
above, where <chip> is tegra132.
|
||||
- compatible : Should contain one of the following:
|
||||
For Tegra20 must contain "nvidia,tegra20-pmc".
|
||||
For Tegra30 must contain "nvidia,tegra30-pmc".
|
||||
For Tegra114 must contain "nvidia,tegra114-pmc"
|
||||
For Tegra124 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra132 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra210 must contain "nvidia,tegra210-pmc"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
@ -68,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
Optional nodes:
|
||||
- powergates : This node contains a hierarchy of power domain nodes, which
|
||||
should match the powergates on the Tegra SoC. See "Powergate
|
||||
Nodes" below.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
@ -113,3 +122,76 @@ pmc@7000f400 {
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
== Powergate Nodes ==
|
||||
|
||||
Each of the powergate nodes represents a power-domain on the Tegra SoC
|
||||
that can be power-gated by the Tegra PMC. The name of the powergate node
|
||||
should be one of the below. Note that not every powergate is applicable
|
||||
to all Tegra devices and the following list shows which powergates are
|
||||
applicable to which devices. Please refer to the Tegra TRM for more
|
||||
details on the various powergates.
|
||||
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
Required properties:
|
||||
- clocks: Must contain an entry for each clock required by the PMC for
|
||||
controlling a power-gate. See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each reset required by the PMC for
|
||||
controlling a power-gate. See ../reset/reset.txt for details.
|
||||
- #power-domain-cells: Must be 0.
|
||||
|
||||
Example:
|
||||
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
== Powergate Clients ==
|
||||
|
||||
Hardware blocks belonging to a power domain should contain a "power-domains"
|
||||
property that is a phandle pointing to the corresponding powergate node.
|
||||
|
||||
Example:
|
||||
|
||||
adma: adma@702e2000 {
|
||||
...
|
||||
power-domains = <&pd_audio>;
|
||||
...
|
||||
};
|
||||
|
@ -23,7 +23,7 @@ scu:
|
||||
see binding for arm/scu.txt
|
||||
|
||||
interrupt-controller:
|
||||
see binding for arm/gic.txt
|
||||
see binding for interrupt-controller/arm,gic.txt
|
||||
|
||||
timer:
|
||||
see binding for arm/twd.txt
|
||||
|
@ -11,8 +11,10 @@ Required properties:
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "cavium,octeon-7130-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
- "marvell,armada-380-ahci"
|
||||
- "marvell,armada-3700-ahci"
|
||||
- "snps,dwc-ahci"
|
||||
- "snps,exynos5440-ahci"
|
||||
- "snps,spear-ahci"
|
||||
@ -30,6 +32,10 @@ Optional properties:
|
||||
- target-supply : regulator for SATA target power
|
||||
- phys : reference to the SATA PHY node
|
||||
- phy-names : must be "sata-phy"
|
||||
- ports-implemented : Mask that indicates which ports that the HBA supports
|
||||
are available for software to use. Useful if PORTS_IMPL
|
||||
is not programmed by the BIOS, which is true with
|
||||
some embedded SOC's.
|
||||
|
||||
Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
|
@ -1,29 +0,0 @@
|
||||
btmrvl
|
||||
------
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must be "btmrvl,cfgdata"
|
||||
|
||||
Optional properties:
|
||||
|
||||
- btmrvl,cal-data : Calibration data downloaded to the device during
|
||||
initialization. This is an array of 28 values(u8).
|
||||
|
||||
- btmrvl,gpio-gap : gpio and gap (in msecs) combination to be
|
||||
configured.
|
||||
|
||||
Example:
|
||||
|
||||
GPIO pin 13 is configured as a wakeup source and GAP is set to 100 msecs
|
||||
in below example.
|
||||
|
||||
btmrvl {
|
||||
compatible = "btmrvl,cfgdata";
|
||||
|
||||
btmrvl,cal-data = /bits/ 8 <
|
||||
0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
|
||||
0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
|
||||
0x00 0x00 0xf0 0x00>;
|
||||
btmrvl,gpio-gap = <0x0d64>;
|
||||
};
|
41
Bindings/clock/artpec6.txt
Normal file
41
Bindings/clock/artpec6.txt
Normal file
@ -0,0 +1,41 @@
|
||||
* Clock bindings for Axis ARTPEC-6 chip
|
||||
|
||||
The bindings are based on the clock provider binding in
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are two external inputs to the main clock controller which should be
|
||||
provided using the common clock bindings.
|
||||
- "sys_refclk": External 50 Mhz oscillator (required)
|
||||
- "i2s_refclk": Alternate audio reference clock (optional).
|
||||
|
||||
Main clock controller
|
||||
---------------------
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
|
||||
- compatible: Should be "axis,artpec6-clkctrl"
|
||||
- reg: Must contain the base address and length of the system controller
|
||||
- clocks: Must contain a phandle entry for each clock in clock-names
|
||||
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
|
||||
ones are the audio reference clock ("i2s_refclk") and the audio fractional
|
||||
dividers ("frac_clk0" and "frac_clk1").
|
||||
|
||||
Examples:
|
||||
|
||||
ext_clk: ext_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl@f8000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "axis,artpec6-clkctrl";
|
||||
reg = <0xf8000000 0x48>;
|
||||
clocks = <&ext_clk>;
|
||||
clock-names = "sys_refclk";
|
||||
};
|
@ -8,7 +8,10 @@ Required properties:
|
||||
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
|
||||
- #clock-cells : from common clock binding; Should always be set to 0.
|
||||
- reg : Address and length of the axi-clkgen register set.
|
||||
- clocks : Phandle and clock specifier for the parent clock.
|
||||
- clocks : Phandle and clock specifier for the parent clock(s). This must
|
||||
either reference one clock if only the first clock input is connected or two
|
||||
if both clock inputs are connected. For the later case the clock connected
|
||||
to the first input must be specified first.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
25
Bindings/clock/axs10x-i2s-pll-clock.txt
Normal file
25
Bindings/clock/axs10x-i2s-pll-clock.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Binding for the AXS10X I2S PLL clock
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "snps,axs10x-i2s-pll-clock"
|
||||
- reg : address and length of the I2S PLL register set.
|
||||
- clocks: shall be the input parent clock phandle for the PLL.
|
||||
- #clock-cells: from common clock binding; Should always be set to 0.
|
||||
|
||||
Example:
|
||||
pll_clock: pll_clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2s_clock@100a0 {
|
||||
compatible = "snps,axs10x-i2s-pll-clock";
|
||||
reg = <0x100a0 0x10>;
|
||||
clocks = <&pll_clock>;
|
||||
#clock-cells = <0>;
|
||||
};
|
@ -92,6 +92,7 @@ PLL and leaf clock compatible strings for Cygnus are:
|
||||
"brcm,cygnus-lcpll0"
|
||||
"brcm,cygnus-mipipll"
|
||||
"brcm,cygnus-asiu-clk"
|
||||
"brcm,cygnus-audiopll"
|
||||
|
||||
The following table defines the set of PLL/clock index and ID for Cygnus.
|
||||
These clock IDs are defined in:
|
||||
@ -131,6 +132,11 @@ These clock IDs are defined in:
|
||||
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
|
||||
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
|
||||
|
||||
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
|
||||
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
|
||||
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
|
||||
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
|
||||
|
||||
Northstar and Northstar Plus
|
||||
------
|
||||
PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
|
||||
|
46
Bindings/clock/hi3519-crg.txt
Normal file
46
Bindings/clock/hi3519-crg.txt
Normal file
@ -0,0 +1,46 @@
|
||||
* Hisilicon Hi3519 Clock and Reset Generator(CRG)
|
||||
|
||||
The Hi3519 CRG module provides clock and reset signals to various
|
||||
controllers within the SoC.
|
||||
|
||||
This binding uses the following bindings:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
|
||||
|
||||
- #reset-cells: should be 2.
|
||||
|
||||
A reset signal can be controlled by writing a bit register in the CRG module.
|
||||
The reset specifier consists of two cells. The first cell represents the
|
||||
register offset relative to the base address. The second cell represents the
|
||||
bit index in the register.
|
||||
|
||||
Example: CRG nodes
|
||||
CRG: clock-reset-controller@12010000 {
|
||||
compatible = "hisilicon,hi3519-crg";
|
||||
reg = <0x12010000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
Example: consumer nodes
|
||||
i2c0: i2c@12110000 {
|
||||
compatible = "hisilicon,hi3519-i2c";
|
||||
reg = <0x12110000 0x1000>;
|
||||
clocks = <&CRG HI3519_I2C0_RST>;
|
||||
resets = <&CRG 0xe4 0>;
|
||||
};
|
@ -94,6 +94,7 @@ clocks and IDs.
|
||||
csi_sel 79
|
||||
iim_gate 80
|
||||
gpu2d_gate 81
|
||||
ckli_gate 82
|
||||
|
||||
Examples:
|
||||
|
||||
|
52
Bindings/clock/lpc1850-creg-clk.txt
Normal file
52
Bindings/clock/lpc1850-creg-clk.txt
Normal file
@ -0,0 +1,52 @@
|
||||
* NXP LPC1850 CREG clocks
|
||||
|
||||
The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
|
||||
control registers for two low speed clocks. One of the clocks is a
|
||||
32 kHz oscillator driver with power up/down and clock gating. Next
|
||||
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
|
||||
|
||||
These clocks are used by the RTC and the Event Router peripherials.
|
||||
The 32 kHz can also be routed to other peripherials to enable low
|
||||
power modes.
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Should be "nxp,lpc1850-creg-clk"
|
||||
- #clock-cells:
|
||||
Shall have value <1>.
|
||||
- clocks:
|
||||
Shall contain a phandle to the fixed 32 kHz crystal.
|
||||
|
||||
The creg-clk node must be a child of the creg syscon node.
|
||||
|
||||
The following clocks are available from the clock node.
|
||||
|
||||
Clock ID Name
|
||||
0 1 kHz clock
|
||||
1 32 kHz Oscillator
|
||||
|
||||
Example:
|
||||
soc {
|
||||
creg: syscon@40043000 {
|
||||
compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
|
||||
reg = <0x40043000 0x1000>;
|
||||
|
||||
creg_clk: clock-controller {
|
||||
compatible = "nxp,lpc1850-creg-clk";
|
||||
clocks = <&xtal32>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
};
|
||||
|
||||
rtc: rtc@40046000 {
|
||||
...
|
||||
clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
|
||||
clock-names = "rtc", "reg";
|
||||
...
|
||||
};
|
||||
};
|
39
Bindings/clock/microchip,pic32.txt
Normal file
39
Bindings/clock/microchip,pic32.txt
Normal file
@ -0,0 +1,39 @@
|
||||
Microchip PIC32 Clock Controller Binding
|
||||
----------------------------------------
|
||||
Microchip clock controller is consists of few oscillators, PLL, multiplexer
|
||||
and few divider modules.
|
||||
|
||||
This binding uses common clock bindings.
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "microchip,pic32mzda-clk".
|
||||
- reg: shall contain base address and length of clock registers.
|
||||
- #clock-cells: shall be 1.
|
||||
|
||||
Optional properties:
|
||||
- microchip,pic32mzda-sosc: shall be added only if platform has
|
||||
secondary oscillator connected.
|
||||
|
||||
Example:
|
||||
rootclk: clock-controller@1f801200 {
|
||||
compatible = "microchip,pic32mzda-clk";
|
||||
reg = <0x1f801200 0x200>;
|
||||
#clock-cells = <1>;
|
||||
/* optional */
|
||||
microchip,pic32mzda-sosc;
|
||||
};
|
||||
|
||||
|
||||
The clock consumer shall specify the desired clock-output of the clock
|
||||
controller (as defined in [2]) by specifying output-id in its "clock"
|
||||
phandle cell.
|
||||
[2] include/dt-bindings/clock/microchip,pic32-clock.h
|
||||
|
||||
For example for UART2:
|
||||
uart2: serial@2 {
|
||||
compatible = "microchip,pic32mzda-uart";
|
||||
reg = <>;
|
||||
interrupts = <>;
|
||||
clocks = <&rootclk PB2CLK>;
|
||||
};
|
@ -50,7 +50,7 @@ Required properties for I2C mode:
|
||||
|
||||
Example:
|
||||
|
||||
clock@0,70110000 {
|
||||
clock@70110000 {
|
||||
compatible = "nvidia,tegra124-dfll";
|
||||
reg = <0 0x70110000 0 0x100>, /* DFLL control */
|
||||
<0 0x70110000 0 0x100>, /* I2C output control */
|
||||
|
35
Bindings/clock/oxnas,stdclk.txt
Normal file
35
Bindings/clock/oxnas,stdclk.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Oxford Semiconductor OXNAS SoC Family Standard Clocks
|
||||
================================================
|
||||
|
||||
Please also refer to clock-bindings.txt in this directory for common clock
|
||||
bindings usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "oxsemi,ox810se-stdclk"
|
||||
- #clock-cells: 1, see below
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||||
|
||||
For OX810SE, the clock indices are :
|
||||
- 0: LEON
|
||||
- 1: DMA_SGDMA
|
||||
- 2: CIPHER
|
||||
- 3: SATA
|
||||
- 4: AUDIO
|
||||
- 5: USBMPH
|
||||
- 6: ETHA
|
||||
- 7: PCIA
|
||||
- 8: NAND
|
||||
|
||||
example:
|
||||
|
||||
sys: sys-ctrl@000000 {
|
||||
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
|
||||
reg = <0x000000 0x100000>;
|
||||
|
||||
stdclk: stdclk {
|
||||
compatible = "oxsemi,ox810se-stdclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
|
||||
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
||||
|
||||
Required Properties:
|
||||
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
|
||||
- compatible: has to be "qca,<soctype>-pll" and one of the following
|
||||
fallbacks:
|
||||
- "qca,ar7100-pll"
|
||||
- "qca,ar7240-pll"
|
||||
@ -21,8 +21,8 @@ Optional properties:
|
||||
|
||||
Example:
|
||||
|
||||
memory-controller@18050000 {
|
||||
compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
|
||||
pll-controller@18050000 {
|
||||
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
|
||||
reg = <0x18050000 0x20>;
|
||||
|
||||
clock-names = "ref";
|
||||
|
@ -7,6 +7,7 @@ Required properties :
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-ipq4019"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8916"
|
||||
"qcom,gcc-msm8960"
|
||||
|
@ -61,7 +61,7 @@ Examples
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>;
|
||||
clock-names = "sci_ick";
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
|
@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
|
@ -16,7 +16,7 @@ Required Properties:
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
|
@ -15,7 +15,7 @@ Required Properties:
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
|
62
Bindings/clock/rockchip,rk3399-cru.txt
Normal file
62
Bindings/clock/rockchip,rk3399-cru.txt
Normal file
@ -0,0 +1,62 @@
|
||||
* Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
The RK3399 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
|
||||
- compatible: CRU should be "rockchip,rk3399-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0x0 0xff750000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3399-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff1a0000 {
|
||||
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff180000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
@ -40,7 +40,7 @@ address is common of all subnode.
|
||||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[7]
|
||||
Each subnode should use the binding described in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
|
@ -10,6 +10,7 @@ Required properties:
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
|
||||
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
@ -18,6 +19,7 @@ Required properties:
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
|
||||
@ -39,12 +41,14 @@ Required properties:
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
|
||||
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
|
||||
"allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
|
||||
"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
|
||||
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
|
||||
@ -57,9 +61,12 @@ Required properties:
|
||||
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
|
||||
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
|
||||
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
|
||||
"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
|
||||
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
|
||||
"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
|
||||
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
|
||||
@ -69,6 +76,8 @@ Required properties:
|
||||
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
|
||||
"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
@ -77,6 +86,7 @@ Required properties:
|
||||
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
|
||||
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
|
||||
"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
|
||||
"allwinner,sun6i-a31-display-clk" - for the display clocks
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
|
41
Bindings/clock/ti/adpll.txt
Normal file
41
Bindings/clock/ti/adpll.txt
Normal file
@ -0,0 +1,41 @@
|
||||
Binding for Texas Instruments ADPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped ADPLL with two to three selectable input clocks
|
||||
and three to four children.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of "ti,dm814-adpll-s-clock" or
|
||||
"ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
- clocks : link phandles of parent clocks clkinp and clkinpulow, note
|
||||
that the adpll-s-clock also has an optional clkinphif
|
||||
- reg : address and length of the register set for controlling the ADPLL.
|
||||
|
||||
Examples:
|
||||
adpll_mpu_ck: adpll@40 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-s-clock";
|
||||
reg = <0x40 0x40>;
|
||||
clocks = <&devosc_ck &devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow", "clkinphif";
|
||||
clock-output-names = "481c5040.adpll.dcoclkldo",
|
||||
"481c5040.adpll.clkout",
|
||||
"481c5040.adpll.clkoutx2",
|
||||
"481c5040.adpll.clkouthif";
|
||||
};
|
||||
|
||||
adpll_dsp_ck: adpll@80 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x80 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5080.adpll.dcoclkldo",
|
||||
"481c5080.adpll.clkout",
|
||||
"481c5080.adpll.clkoutldo";
|
||||
};
|
@ -9,6 +9,8 @@ Required properties:
|
||||
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
|
||||
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
|
||||
"apm,xgene-device-clock" - for a X-Gene device clock
|
||||
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
|
||||
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
|
||||
|
||||
Required properties for SoC or PCP PLL clocks:
|
||||
- reg : shall be the physical PLL register address for the pll clock.
|
||||
|
21
Bindings/crypto/fsl-imx-scc.txt
Normal file
21
Bindings/crypto/fsl-imx-scc.txt
Normal file
@ -0,0 +1,21 @@
|
||||
Freescale Security Controller (SCC)
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx25-scc".
|
||||
- reg : Should contain register location and length.
|
||||
- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
|
||||
- interrupt-names : Should specify the names "scm" and "smn" for the
|
||||
SCM IRQ and SMN IRQ.
|
||||
- clocks: Should contain the clock driving the SCC core.
|
||||
- clock-names: Should be set to "ipg".
|
||||
|
||||
Example:
|
||||
|
||||
scc: crypto@53fac000 {
|
||||
compatible = "fsl,imx25-scc";
|
||||
reg = <0x53fac000 0x4000>;
|
||||
clocks = <&clks 111>;
|
||||
clock-names = "ipg";
|
||||
interrupts = <49>, <50>;
|
||||
interrupt-names = "scm", "smn";
|
||||
};
|
@ -23,10 +23,8 @@ Required properties:
|
||||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts, should contain
|
||||
following entries:
|
||||
- first : feed control interrupt (required for all variants),
|
||||
- second : hash interrupt (required only for samsung,s5pv210-secss).
|
||||
- interrupts : interrupt specifiers of SSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
|
26
Bindings/devfreq/event/exynos-nocp.txt
Normal file
26
Bindings/devfreq/event/exynos-nocp.txt
Normal file
@ -0,0 +1,26 @@
|
||||
|
||||
* Samsung Exynos NoC (Network on Chip) Probe device
|
||||
|
||||
The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
|
||||
NoC provides the primitive values to get the performance data. The packets
|
||||
that the Network on Chip (NoC) probes detects are transported over
|
||||
the network infrastructure to observer units. You can configure probes to
|
||||
capture packets with header or data on the data request response network,
|
||||
or as traffic debug or statistic collectors. Exynos542x bus has multiple
|
||||
NoC probes to provide bandwidth information about behavior of the SoC
|
||||
that you can use while analyzing system performance.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,exynos5420-nocp"
|
||||
- reg: physical base address of each NoC Probe and length of memory mapped region.
|
||||
|
||||
Optional properties:
|
||||
- clock-names : the name of clock used by the NoC Probe, "nocp"
|
||||
- clocks : phandles for clock specified in "clock-names" property
|
||||
|
||||
Example : NoC Probe nodes in Device Tree are listed below.
|
||||
|
||||
nocp_mem0_0: nocp@10CA1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
};
|
409
Bindings/devfreq/exynos-bus.txt
Normal file
409
Bindings/devfreq/exynos-bus.txt
Normal file
@ -0,0 +1,409 @@
|
||||
* Generic Exynos Bus frequency device
|
||||
|
||||
The Samsung Exynos SoC has many buses for data transfer between DRAM
|
||||
and sub-blocks in SoC. Most Exynos SoCs share the common architecture
|
||||
for buses. Generally, each bus of Exynos SoC includes a source clock
|
||||
and a power line, which are able to change the clock frequency
|
||||
of the bus in runtime. To monitor the usage of each bus in runtime,
|
||||
the driver uses the PPMU (Platform Performance Monitoring Unit), which
|
||||
is able to measure the current load of sub-blocks.
|
||||
|
||||
The Exynos SoC includes the various sub-blocks which have the each AXI bus.
|
||||
The each AXI bus has the owned source clock but, has not the only owned
|
||||
power line. The power line might be shared among one more sub-blocks.
|
||||
So, we can divide into two type of device as the role of each sub-block.
|
||||
There are two type of bus devices as following:
|
||||
- parent bus device
|
||||
- passive bus device
|
||||
|
||||
Basically, parent and passive bus device share the same power line.
|
||||
The parent bus device can only change the voltage of shared power line
|
||||
and the rest bus devices (passive bus device) depend on the decision of
|
||||
the parent bus device. If there are three blocks which share the VDD_xxx
|
||||
power line, Only one block should be parent device and then the rest blocks
|
||||
should depend on the parent device as passive device.
|
||||
|
||||
VDD_xxx |--- A block (parent)
|
||||
|--- B block (passive)
|
||||
|--- C block (passive)
|
||||
|
||||
There are a little different composition among Exynos SoC because each Exynos
|
||||
SoC has different sub-blocks. Therefore, such difference should be specified
|
||||
in devicetree file instead of each device driver. In result, this driver
|
||||
is able to support the bus frequency for all Exynos SoCs.
|
||||
|
||||
Required properties for all bus devices:
|
||||
- compatible: Should be "samsung,exynos-bus".
|
||||
- clock-names : the name of clock used by the bus, "bus".
|
||||
- clocks : phandles for clock specified in "clock-names" property.
|
||||
- operating-points-v2: the OPP table including frequency/voltage information
|
||||
to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
|
||||
|
||||
Required properties only for parent bus device:
|
||||
- vdd-supply: the regulator to provide the buses with the voltage.
|
||||
- devfreq-events: the devfreq-event device to monitor the current utilization
|
||||
of buses.
|
||||
|
||||
Required properties only for passive bus device:
|
||||
- devfreq: the parent bus device.
|
||||
|
||||
Optional properties only for parent bus device:
|
||||
- exynos,saturation-ratio: the percentage value which is used to calibrate
|
||||
the performance count against total cycle count.
|
||||
- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
|
||||
which is used to calculate the max voltage.
|
||||
|
||||
Detailed correlation between sub-blocks and power line according to Exynos SoC:
|
||||
- In case of Exynos3250, there are two power line as following:
|
||||
VDD_MIF |--- DMC
|
||||
|
||||
VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC
|
||||
|--- G3D
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- FSYS
|
||||
|--- LCD0
|
||||
|--- PERIR
|
||||
|--- ISP
|
||||
|--- CAM
|
||||
|
||||
- In case of Exynos4210, there is one power line as following:
|
||||
VDD_INT |--- DMC (parent device)
|
||||
|--- LEFTBUS
|
||||
|--- PERIL
|
||||
|--- MFC(L)
|
||||
|--- G3D
|
||||
|--- TV
|
||||
|--- LCD0
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- MFC(R)
|
||||
|--- CAM
|
||||
|--- FSYS
|
||||
|--- GPS
|
||||
|--- LCD0
|
||||
|--- LCD1
|
||||
|
||||
- In case of Exynos4x12, there are two power line as following:
|
||||
VDD_MIF |--- DMC
|
||||
|
||||
VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC(L)
|
||||
|--- G3D
|
||||
|--- TV
|
||||
|--- IMAGE
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- MFC(R)
|
||||
|--- CAM
|
||||
|--- FSYS
|
||||
|--- GPS
|
||||
|--- LCD0
|
||||
|--- ISP
|
||||
|
||||
- In case of Exynos5422, there are two power line as following:
|
||||
VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
|
||||
|--- DREX 1
|
||||
|
||||
VDD_INT |--- NoC_Core (parent device)
|
||||
|--- G2D
|
||||
|--- G3D
|
||||
|--- DISP1
|
||||
|--- NoC_WCORE
|
||||
|--- GSCL
|
||||
|--- MSCL
|
||||
|--- ISP
|
||||
|--- MFC
|
||||
|--- GEN
|
||||
|--- PERIS
|
||||
|--- PERIC
|
||||
|--- FSYS
|
||||
|--- FSYS2
|
||||
|
||||
Example1:
|
||||
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
|
||||
power line (regulator). The MIF (Memory Interface) AXI bus is used to
|
||||
transfer data between DRAM and CPU and uses the VDD_MIF regulator.
|
||||
|
||||
- MIF (Memory Interface) block
|
||||
: VDD_MIF |--- DMC (Dynamic Memory Controller)
|
||||
|
||||
- INT (Internal) block
|
||||
: VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC
|
||||
|--- G3D
|
||||
|--- RIGHTBUS
|
||||
|--- FSYS
|
||||
|--- LCD0
|
||||
|--- PERIR
|
||||
|--- ISP
|
||||
|--- CAM
|
||||
|
||||
- MIF bus's frequency/voltage table
|
||||
-----------------------
|
||||
|Lv| Freq | Voltage |
|
||||
-----------------------
|
||||
|L1| 50000 |800000 |
|
||||
|L2| 100000 |800000 |
|
||||
|L3| 134000 |800000 |
|
||||
|L4| 200000 |825000 |
|
||||
|L5| 400000 |875000 |
|
||||
-----------------------
|
||||
|
||||
- INT bus's frequency/voltage table
|
||||
----------------------------------------------------------
|
||||
|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
|
||||
| name| |LCD0 | | | || |
|
||||
| | |FSYS | | | || |
|
||||
| | |MFC | | | || |
|
||||
----------------------------------------------------------
|
||||
|Mode |*parent|passive |passive|passive|passive|| |
|
||||
----------------------------------------------------------
|
||||
|Lv |Frequency ||Voltage |
|
||||
----------------------------------------------------------
|
||||
|L1 |50000 |50000 |50000 |50000 |50000 ||900000 |
|
||||
|L2 |80000 |80000 |80000 |80000 |80000 ||900000 |
|
||||
|L3 |100000 |100000 |100000 |100000 |100000 ||1000000 |
|
||||
|L4 |134000 |134000 |200000 |200000 | ||1000000 |
|
||||
|L5 |200000 |200000 |400000 |300000 | ||1000000 |
|
||||
----------------------------------------------------------
|
||||
|
||||
Example2 :
|
||||
The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
|
||||
is listed below:
|
||||
|
||||
bus_dmc: bus_dmc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu_dmc CLK_DIV_DMC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <825000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <875000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_lcd0: bus_lcd0 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_200>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mcuisp: bus_mcuisp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mcuisp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_isp: bus_isp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_266>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_isp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peril: bus_peril {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_100>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peril_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mcuisp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_isp_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peril_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Usage case to handle the frequency and voltage of bus on runtime
|
||||
in exynos3250-rinato.dts is listed below:
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>; /* VDD_MIF */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_lcd0 {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mcuisp {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_isp {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peril {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
79
Bindings/display/arm,hdlcd.txt
Normal file
79
Bindings/display/arm,hdlcd.txt
Normal file
@ -0,0 +1,79 @@
|
||||
ARM HDLCD
|
||||
|
||||
This is a display controller found on several development platforms produced
|
||||
by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
|
||||
streamer that reads the data from a framebuffer and sends it to a single
|
||||
digital encoder (DVI or HDMI).
|
||||
|
||||
Required properties:
|
||||
- compatible: "arm,hdlcd"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: One interrupt used by the display controller to notify the
|
||||
interrupt controller when any of the interrupt sources programmed in
|
||||
the interrupt mask register have activated.
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For HDLCD it should contain:
|
||||
- "pxlclk" for the clock feeding the output PLL of the controller.
|
||||
|
||||
Required sub-nodes:
|
||||
- port: The HDLCD connection to an encoder chip. The connection is modeled
|
||||
using the OF graph bindings specified in
|
||||
Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
|
||||
used for the framebuffer; if not present, the framebuffer may be located
|
||||
anywhere in memory.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x2b000000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&oscclk5>;
|
||||
clock-names = "pxlclk";
|
||||
port {
|
||||
hdlcd_output: endpoint@0 {
|
||||
remote-endpoint = <&hdmi_enc_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* HDMI encoder on I2C bus */
|
||||
i2c@7ffa0000 {
|
||||
....
|
||||
hdmi-transmitter@70 {
|
||||
compatible = ".....";
|
||||
reg = <0x70>;
|
||||
port@0 {
|
||||
hdmi_enc_input: endpoint {
|
||||
remote-endpoint = <&hdlcd_output>;
|
||||
};
|
||||
|
||||
hdmi_enc_output: endpoint {
|
||||
remote-endpoint = <&hdmi_1_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi1: connector@1 {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
port {
|
||||
hdmi_1_port: endpoint {
|
||||
remote-endpoint = <&hdmi_enc_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
};
|
@ -35,6 +35,22 @@ Optional properties for HDMI:
|
||||
as an interrupt/status bit in the HDMI controller
|
||||
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
|
||||
|
||||
Required properties for DPI:
|
||||
- compatible: Should be "brcm,bcm2835-dpi"
|
||||
- reg: Physical base address and length of the registers
|
||||
- clocks: a) core: The core clock the unit runs on
|
||||
b) pixel: The pixel clock that feeds the pixelvalve
|
||||
- port: Port node with a single endpoint connecting to the panel
|
||||
device, as defined in [1]
|
||||
|
||||
Required properties for V3D:
|
||||
- compatible: Should be "brcm,bcm2835-v3d"
|
||||
- reg: Physical base address and length of the V3D's registers
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
@ -60,6 +76,38 @@ hdmi: hdmi@7e902000 {
|
||||
clock-names = "pixel", "hdmi";
|
||||
};
|
||||
|
||||
dpi: dpi@7e208000 {
|
||||
compatible = "brcm,bcm2835-dpi";
|
||||
reg = <0x7e208000 0x8c>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>,
|
||||
<&clocks BCM2835_CLOCK_DPI>;
|
||||
clock-names = "core", "pixel";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "ontat,yx700wv03", "simple-panel";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
52
Bindings/display/bridge/analogix_dp.txt
Normal file
52
Bindings/display/bridge/analogix_dp.txt
Normal file
@ -0,0 +1,52 @@
|
||||
Analogix Display Port bridge bindings
|
||||
|
||||
Required properties for dp-controller:
|
||||
-compatible:
|
||||
platform specific such as:
|
||||
* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
-interrupts:
|
||||
interrupt combiner values.
|
||||
-clocks:
|
||||
from common clock binding: handle to dp clock.
|
||||
-clock-names:
|
||||
from common clock binding: Shall be "dp".
|
||||
-interrupt-parent:
|
||||
phandle to Interrupt combiner node.
|
||||
-phys:
|
||||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-force-hpd:
|
||||
Indicate driver need force hpd when hpd detect failed, this
|
||||
is used for some eDP screen which don't have hpd signal.
|
||||
-hpd-gpios:
|
||||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug detection
|
||||
-port@[X]: SoC specific port nodes with endpoint definitions as defined
|
||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
please refer to the SoC specific binding document:
|
||||
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
|
||||
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x10000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
clocks = <&clock 342>;
|
||||
clock-names = "dp";
|
||||
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
};
|
@ -5,7 +5,8 @@ Exynos series of SoCs which transfers the image data from a video memory
|
||||
buffer to an external LCD interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "samsung,exynos5433-decon";
|
||||
- compatible: value should be one of:
|
||||
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
|
||||
- reg: physical base address and length of the DECON registers set.
|
||||
- interrupts: should contain a list of all DECON IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier format
|
||||
@ -16,7 +17,7 @@ Required properties:
|
||||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
- clock-names: list of clock names sorted in the same order as the clocks
|
||||
property. Must contain "aclk_decon", "aclk_smmu_decon0x",
|
||||
property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
|
||||
"aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
|
||||
"sclk_decon_eclk"
|
||||
- ports: contains a port which is connected to mic node. address-cells and
|
||||
|
@ -1,20 +1,3 @@
|
||||
Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
|
||||
|
||||
DisplayPort is industry standard to accommodate the growing board adoption
|
||||
of digital display technology within the PC and CE industries.
|
||||
It consolidates the internal and external connection methods to reduce device
|
||||
complexity and cost. It also supports necessary features for important cross
|
||||
industry applications and provides performance scalability to enable the next
|
||||
generation of displays that feature higher color depths, refresh rates, and
|
||||
display resolutions.
|
||||
|
||||
eDP (embedded display port) device is compliant with Embedded DisplayPort
|
||||
standard as follows,
|
||||
- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
|
||||
- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
|
||||
|
||||
eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
|
||||
|
||||
The Exynos display port interface should be configured based on
|
||||
the type of panel connected to it.
|
||||
|
||||
@ -48,26 +31,6 @@ Required properties for dp-controller:
|
||||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
-samsung,color-space:
|
||||
input video data format.
|
||||
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
|
||||
-samsung,dynamic-range:
|
||||
dynamic range for input video data.
|
||||
VESA = 0, CEA = 1
|
||||
-samsung,ycbcr-coeff:
|
||||
YCbCr co-efficients for input video.
|
||||
COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
|
||||
-samsung,color-depth:
|
||||
number of bits per colour component.
|
||||
COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
|
||||
-samsung,link-rate:
|
||||
link rate supported by the panel.
|
||||
LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
|
||||
-samsung,lane-count:
|
||||
number of lanes supported by the panel.
|
||||
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/display-timing.txt
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-interlaced:
|
||||
@ -83,17 +46,31 @@ Optional properties for dp-controller:
|
||||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug
|
||||
detection
|
||||
Video interfaces:
|
||||
Device node can contain video interface port nodes according to [1].
|
||||
The following are properties specific to those nodes:
|
||||
-video interfaces: Device node can contain video interface port
|
||||
nodes according to [1].
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||
|
||||
endpoint node connected to bridge or panel node:
|
||||
- remote-endpoint: specifies the endpoint in panel or bridge node.
|
||||
This node is required in all kinds of exynos dp
|
||||
to represent the connection between dp and bridge
|
||||
or dp and panel.
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
|
||||
-phys (required)
|
||||
-phy-names (required)
|
||||
-hpd-gpios (optional)
|
||||
force-hpd (optional)
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Deprecated properties for DisplayPort:
|
||||
-interlaced: deprecated prop that can parsed from drm_display_mode.
|
||||
-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,color-space: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,hpd-gpio: deprecated name for hpd-gpios.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
@ -112,13 +89,6 @@ SOC specific portion:
|
||||
|
||||
Board Specific portion:
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lcd_timing>;
|
||||
lcd_timing: 1366x768 {
|
||||
@ -135,18 +105,9 @@ Board Specific portion:
|
||||
};
|
||||
|
||||
ports {
|
||||
port {
|
||||
port@0 {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
...
|
||||
port {
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -6,6 +6,7 @@ Required properties:
|
||||
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
|
||||
"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
|
||||
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
|
||||
"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
|
||||
"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
|
||||
- reg: physical base address and length of the registers set for the device
|
||||
- interrupts: should contain DSI interrupt
|
||||
@ -40,7 +41,7 @@ Video interfaces:
|
||||
endpoint node connected from mic node (reg = 0):
|
||||
- remote-endpoint: specifies the endpoint in mic node. This node is required
|
||||
for Exynos5433 mipi dsi. So mic can access to panel node
|
||||
thoughout this dsi node.
|
||||
throughout this dsi node.
|
||||
endpoint node connected to panel node (reg = 1):
|
||||
- remote-endpoint: specifies the endpoint in panel node. This node is
|
||||
required in all kinds of exynos mipi dsi to represent
|
||||
|
@ -5,6 +5,7 @@ Required properties:
|
||||
1) "samsung,exynos4210-hdmi"
|
||||
2) "samsung,exynos4212-hdmi"
|
||||
3) "samsung,exynos5420-hdmi"
|
||||
4) "samsung,exynos5433-hdmi"
|
||||
- reg: physical base address of the hdmi and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
@ -12,6 +13,11 @@ Required properties:
|
||||
a) phandle of the gpio controller node.
|
||||
b) pin number within the gpio controller.
|
||||
c) optional flags and pull up/down.
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 4210, 4212, 5420 and 5433:
|
||||
- clocks: list of clock IDs from SoC clock driver.
|
||||
a) hdmi: Gate of HDMI IP bus clock.
|
||||
b) sclk_hdmi: Gate of HDMI special clock.
|
||||
@ -25,9 +31,24 @@ Required properties:
|
||||
sclk_pixel.
|
||||
- clock-names: aliases as per driver requirements for above clock IDs:
|
||||
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 5433:
|
||||
- clocks: list of clock specifiers according to common clock bindings.
|
||||
a) hdmi_pclk: Gate of HDMI IP APB bus.
|
||||
b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
|
||||
d) i_tmds_clk: Gate of HDMI TMDS clock.
|
||||
e) i_pixel_clk: Gate of HDMI pixel clock.
|
||||
f) i_spdif_clk: Gate of HDMI SPDIF clock.
|
||||
g) oscclk: Oscillator clock, used as parent of following *_user clocks
|
||||
in case HDMI-PHY is not operational.
|
||||
h) tmds_clko: TMDS clock generated by HDMI-PHY.
|
||||
i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
j) pixel_clko: Pixel clock generated by HDMI-PHY.
|
||||
k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
- clock-names: aliases for above clock specfiers.
|
||||
- samsung,sysreg: handle to syscon used to control the system registers.
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -12,7 +12,8 @@ Required properties:
|
||||
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
|
||||
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
|
||||
"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
|
||||
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
|
||||
"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
|
||||
"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
|
||||
|
||||
- reg: physical base address and length of the FIMD registers set.
|
||||
|
||||
|
@ -6,17 +6,24 @@ Required properties:
|
||||
* "fsl,vf610-dcu".
|
||||
|
||||
- reg: Address and length of the register set for dcu.
|
||||
- clocks: From common clock binding: handle to dcu clock.
|
||||
- clock-names: From common clock binding: Shall be "dcu".
|
||||
- clocks: Handle to "dcu" and "pix" clock (in the order below)
|
||||
This can be the same clock (e.g. LS1021a)
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
|
||||
Examples:
|
||||
dcu: dcu@2ce0000 {
|
||||
compatible = "fsl,ls1021a-dcu";
|
||||
reg = <0x0 0x2ce0000 0x0 0x10000>;
|
||||
clocks = <&platform_clk 0>;
|
||||
clock-names = "dcu";
|
||||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
};
|
||||
|
18
Bindings/display/fsl,tcon.txt
Normal file
18
Bindings/display/fsl,tcon.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Device Tree bindings for Freescale TCON Driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
* "fsl,vf610-tcon".
|
||||
|
||||
- reg: Address and length of the register set for tcon.
|
||||
- clocks: From common clock binding: handle to tcon ipg clock.
|
||||
- clock-names: From common clock binding: Shall be "ipg".
|
||||
|
||||
Examples:
|
||||
timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
status = "okay";
|
||||
};
|
72
Bindings/display/hisilicon/dw-dsi.txt
Normal file
72
Bindings/display/hisilicon/dw-dsi.txt
Normal file
@ -0,0 +1,72 @@
|
||||
Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
|
||||
|
||||
A DSI Host Controller resides in the middle of display controller and external
|
||||
HDMI converter or panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-dsi".
|
||||
- reg: physical base address and length of dsi controller's registers.
|
||||
- clocks: contains APB clock phandle + clock-specifier pair.
|
||||
- clock-names: should be "pclk".
|
||||
- ports: contains DSI controller input and output sub port.
|
||||
The input port connects to ADE output port with the reg value "0".
|
||||
The output port with the reg value "1", it could connect to panel or
|
||||
any other bridge endpoints.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
A example of HiKey board hi6220 SoC and board specific DT entry:
|
||||
Example:
|
||||
|
||||
SoC specific:
|
||||
dsi: dsi@f4107800 {
|
||||
compatible = "hisilicon,hi6220-dsi";
|
||||
reg = <0x0 0xf4107800 0x0 0x100>;
|
||||
clocks = <&media_ctrl HI6220_DSI_PCLK>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 0 for input port */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <&ade_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Board specific:
|
||||
&dsi {
|
||||
status = "ok";
|
||||
|
||||
ports {
|
||||
/* 1 for output port */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi_out0: endpoint@0 {
|
||||
remote-endpoint = <&adv7533_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
...
|
||||
|
||||
adv7533: adv7533@39 {
|
||||
...
|
||||
|
||||
port {
|
||||
adv7533_in: endpoint {
|
||||
remote-endpoint = <&dsi_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
64
Bindings/display/hisilicon/hisi-ade.txt
Normal file
64
Bindings/display/hisilicon/hisi-ade.txt
Normal file
@ -0,0 +1,64 @@
|
||||
Device-Tree bindings for hisilicon ADE display controller driver
|
||||
|
||||
ADE (Advanced Display Engine) is the display controller which grab image
|
||||
data from memory, do composition, do post image processing, generate RGB
|
||||
timing stream and transfer to DSI.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-ade".
|
||||
- reg: physical base address and length of the ADE controller's registers.
|
||||
- hisilicon,noc-syscon: ADE NOC QoS syscon.
|
||||
- resets: The ADE reset controller node.
|
||||
- interrupt: the ldi vblank interrupt number used.
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: should contain:
|
||||
"clk_ade_core" for the ADE core clock.
|
||||
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
||||
jpeg codec.
|
||||
"clk_ade_pix" for the ADE pixel clok.
|
||||
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
||||
phandle + clock-specifier pairs.
|
||||
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
||||
The rate of "clk_ade_core" could be "360000000" or "180000000";
|
||||
The rate of "clk_codec_jpeg" could be or less than "1440000000".
|
||||
These rate values could be configured according to performance and power
|
||||
consumption.
|
||||
- port: the output port. This contains one endpoint subnode, with its
|
||||
remote-endpoint set to the phandle of the connected DSI input endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent.
|
||||
|
||||
|
||||
A example of HiKey board hi6220 SoC specific DT entry:
|
||||
Example:
|
||||
|
||||
ade: ade@f4100000 {
|
||||
compatible = "hisilicon,hi6220-ade";
|
||||
reg = <0x0 0xf4100000 0x0 0x7800>;
|
||||
reg-names = "ade_base";
|
||||
hisilicon,noc-syscon = <&medianoc_ade>;
|
||||
resets = <&media_ctrl MEDIA_ADE>;
|
||||
interrupts = <0 115 4>; /* ldi interrupt */
|
||||
|
||||
clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>,
|
||||
<&media_ctrl HI6220_ADE_PIX_SRC>;
|
||||
/*clock name*/
|
||||
clock-names = "clk_ade_core",
|
||||
"clk_codec_jpeg",
|
||||
"clk_ade_pix";
|
||||
|
||||
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>;
|
||||
assigned-clock-rates = <360000000>, <288000000>;
|
||||
dma-coherent;
|
||||
|
||||
port {
|
||||
ade_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
@ -62,6 +62,7 @@ Required properties:
|
||||
display-timings are used instead.
|
||||
|
||||
Optional properties (required if display-timings are used):
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- display-timings : A node that describes the display timings as defined in
|
||||
Documentation/devicetree/bindings/display/display-timing.txt.
|
||||
- fsl,data-mapping : should be "spwg" or "jeida"
|
||||
|
203
Bindings/display/mediatek/mediatek,disp.txt
Normal file
203
Bindings/display/mediatek/mediatek,disp.txt
Normal file
@ -0,0 +1,203 @@
|
||||
Mediatek display subsystem
|
||||
==========================
|
||||
|
||||
The Mediatek display subsystem consists of various DISP function blocks in the
|
||||
MMSYS register space. The connections between them can be configured by output
|
||||
and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
|
||||
of frame signal are distributed to the other function blocks by a DISP_MUTEX
|
||||
function block.
|
||||
|
||||
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
|
||||
|
||||
DISP function blocks
|
||||
====================
|
||||
|
||||
A display stream starts at a source function block that reads pixel data from
|
||||
memory and ends with a sink function block that drives pixels on a display
|
||||
interface, or writes pixels back to memory. All DISP function blocks have
|
||||
their own register space, interrupt, and clock gate. The blocks that can
|
||||
access memory additionally have to list the IOMMU and local arbiter they are
|
||||
connected to.
|
||||
|
||||
For a description of the display interface sink function blocks, see
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
|
||||
|
||||
Required properties (all function blocks):
|
||||
- compatible: "mediatek,<chip>-disp-<function>", one of
|
||||
"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
|
||||
"mediatek,<chip>-disp-rdma" - read DMA / line buffer
|
||||
"mediatek,<chip>-disp-wdma" - write DMA
|
||||
"mediatek,<chip>-disp-color" - color processor
|
||||
"mediatek,<chip>-disp-aal" - adaptive ambient light controller
|
||||
"mediatek,<chip>-disp-gamma" - gamma correction
|
||||
"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
|
||||
"mediatek,<chip>-disp-split" - split stream to two encoders
|
||||
"mediatek,<chip>-disp-ufoe" - data compression engine
|
||||
"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
|
||||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
For most function blocks this is just a single clock input. Only the DSI and
|
||||
DPI controller nodes have multiple clock inputs. These are documented in
|
||||
mediatek,dsi.txt and mediatek,dpi.txt, respectively.
|
||||
|
||||
Required properties (DMA function blocks):
|
||||
- compatible: Should be one of
|
||||
"mediatek,<chip>-disp-ovl"
|
||||
"mediatek,<chip>-disp-rdma"
|
||||
"mediatek,<chip>-disp-wdma"
|
||||
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
||||
in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
|
||||
- iommus: Should point to the respective IOMMU block with master port as
|
||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
||||
for details.
|
||||
|
||||
Examples:
|
||||
|
||||
mmsys: clock-controller@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
ovl1: ovl@1400d000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1400f000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma2: rdma@14010000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
wdma1: wdma@14012000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
};
|
||||
|
||||
color1: color@14014000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14014000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
||||
};
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
};
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
};
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
/* See mediatek,dsi.txt for details */
|
||||
};
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
/* See mediatek,dpi.txt for details */
|
||||
};
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
35
Bindings/display/mediatek/mediatek,dpi.txt
Normal file
35
Bindings/display/mediatek/mediatek,dpi.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Mediatek DPI Device
|
||||
===================
|
||||
|
||||
The Mediatek DPI function block is a sink of the display subsystem and
|
||||
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
|
||||
output bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dpi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "engine", and "pll"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached HDMI or LVDS encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
compatible = "mediatek,mt8173-dpi";
|
||||
reg = <0 0x1401d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
|
||||
<&mmsys CLK_MM_DPI_ENGINE>,
|
||||
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
||||
clock-names = "pixel", "engine", "pll";
|
||||
|
||||
port {
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
60
Bindings/display/mediatek/mediatek,dsi.txt
Normal file
60
Bindings/display/mediatek/mediatek,dsi.txt
Normal file
@ -0,0 +1,60 @@
|
||||
Mediatek DSI Device
|
||||
===================
|
||||
|
||||
The Mediatek DSI function block is a sink of the display subsystem and can
|
||||
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
|
||||
channel output.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "engine", "digital", and "hs"
|
||||
- phys: phandle link to the MIPI D-PHY controller.
|
||||
- phy-names: must contain "dphy"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
|
||||
|
||||
MIPI TX Configuration Module
|
||||
============================
|
||||
|
||||
The MIPI TX configuration module controls the MIPI D-PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-mipi-tx"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-output-names: name of the output clock line to the DSI encoder
|
||||
- #clock-cells: must be <0>;
|
||||
- #phy-cells: must be <0>.
|
||||
|
||||
Example:
|
||||
|
||||
mipi_tx0: mipi-dphy@10215000 {
|
||||
compatible = "mediatek,mt8173-mipi-tx";
|
||||
reg = <0 0x10215000 0 0x1000>;
|
||||
clocks = <&clk26m>;
|
||||
clock-output-names = "mipi_tx0_pll";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
compatible = "mediatek,mt8173-dsi";
|
||||
reg = <0 0x1401b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
|
||||
<&mipi_tx0>;
|
||||
clock-names = "engine", "digital", "hs";
|
||||
phys = <&mipi_tx0>;
|
||||
phy-names = "dphy";
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
@ -44,9 +44,34 @@ Optional properties:
|
||||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- port: DSI controller output port. This contains one endpoint subnode, with its
|
||||
remote-endpoint set to the phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- port: DSI controller output port, containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: set to phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
|
||||
to the physical lanes on the given platform. The value contained in
|
||||
index n describes what logical data lane is mapped to the physical data
|
||||
lane n (DATAn, where n lies between 0 and 3).
|
||||
|
||||
For example:
|
||||
|
||||
qcom,data-lane-map = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA3 is mapped to
|
||||
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
|
||||
to phys DATA2 and logic DATA2 to phys DATA3.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
|
||||
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
|
||||
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
|
||||
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
|
||||
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
|
||||
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
|
||||
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
|
||||
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
|
||||
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
@ -131,6 +156,7 @@ Example:
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -11,6 +11,7 @@ Required properties:
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- reg-names: "core_physical"
|
||||
- interrupts: The interrupt signal from the hdmi block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
|
||||
@ -18,6 +19,8 @@ Required properties:
|
||||
- qcom,hdmi-tx-hpd-gpio: hpd pin
|
||||
- core-vdda-supply: phandle to supply regulator
|
||||
- hdmi-mux-supply: phandle to mux regulator
|
||||
- phys: the phandle for the HDMI PHY device
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
|
||||
Optional properties:
|
||||
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
|
||||
@ -27,15 +30,38 @@ Optional properties:
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-1: the "sleep" pinctrl state
|
||||
|
||||
HDMI PHY:
|
||||
Required properties:
|
||||
- compatible: Could be the following
|
||||
* "qcom,hdmi-phy-8660"
|
||||
* "qcom,hdmi-phy-8960"
|
||||
* "qcom,hdmi-phy-8974"
|
||||
* "qcom,hdmi-phy-8084"
|
||||
* "qcom,hdmi-phy-8996"
|
||||
- #phy-cells: Number of cells in a PHY specifier; Should be 0.
|
||||
- reg: Physical base address and length of the registers of the PHY sub blocks.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "hdmi_phy"
|
||||
* "hdmi_pll"
|
||||
For HDMI PHY on msm8996, these additional register regions are required:
|
||||
* "hdmi_tx_l0"
|
||||
* "hdmi_tx_l1"
|
||||
* "hdmi_tx_l3"
|
||||
* "hdmi_tx_l4"
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- core-vdda-supply: phandle to vdda regulator device node
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: qcom,hdmi-tx-8960@4a00000 {
|
||||
hdmi: hdmi@4a00000 {
|
||||
compatible = "qcom,hdmi-tx-8960";
|
||||
reg-names = "core_physical";
|
||||
reg = <0x04a00000 0x1000>;
|
||||
reg = <0x04a00000 0x2f0>;
|
||||
interrupts = <GIC_SPI 79 0>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names =
|
||||
@ -54,5 +80,21 @@ Example:
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
|
||||
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
|
||||
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi_phy";
|
||||
};
|
||||
|
||||
hdmi_phy: phy@4a00400 {
|
||||
compatible = "qcom,hdmi-phy-8960";
|
||||
reg-names = "hdmi_phy",
|
||||
"hdmi_pll";
|
||||
reg = <0x4a00400 0x60>,
|
||||
<0x4a00500 0x100>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names = "slave_iface_clk";
|
||||
clocks = <&mmcc HDMI_S_AHB_CLK>;
|
||||
core-vdda-supply = <&pm8921_hdmi_mvs>;
|
||||
};
|
||||
};
|
||||
|
7
Bindings/display/panel/innolux,at070tn92.txt
Normal file
7
Bindings/display/panel/innolux,at070tn92.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Innolux AT070TN92 7.0" WQVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,at070tn92"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
7
Bindings/display/panel/lg,lp120up1.txt
Normal file
7
Bindings/display/panel/lg,lp120up1.txt
Normal file
@ -0,0 +1,7 @@
|
||||
LG 12.0" (1920x1280 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp120up1"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
7
Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
Normal file
7
Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Olimex 4.3" TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "olimex,lcd-olinuxino-43-ts"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
7
Bindings/display/panel/ontat,yx700wv03.txt
Normal file
7
Bindings/display/panel/ontat,yx700wv03.txt
Normal file
@ -0,0 +1,7 @@
|
||||
On Tat Industrial Company 7" DPI TFT panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ontat,yx700wv03"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
8
Bindings/display/panel/tpk,f07a-0102.txt
Normal file
8
Bindings/display/panel/tpk,f07a-0102.txt
Normal file
@ -0,0 +1,8 @@
|
||||
TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with,
|
||||
800 x 480 (WVGA) LCD panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tpk,f07a-0102"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user