Import device-tree files from Linux 5.12
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@ -32,7 +32,7 @@ Optional node properties:
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- "#thermal-sensor-cells" Used to expose itself to thermal fw.
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Read more about iio bindings at
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Documentation/devicetree/bindings/iio/iio-bindings.txt
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https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/
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Example:
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ncp15wb473@0 {
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bindings for GPIO bitbanged I2C
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maintainers:
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- Wolfram Sang <wolfram@the-dreams.de>
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- Wolfram Sang <wsa@kernel.org>
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
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maintainers:
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- Wolfram Sang <wolfram@the-dreams.de>
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- Oleksij Rempel <o.rempel@pengutronix.de>
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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@ -14,8 +14,9 @@ description: >
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Industrial I/O subsystem bindings for ADC controller found in
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Ingenic JZ47xx SoCs.
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ADC clients must use the format described in iio-bindings.txt, giving
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a phandle and IIO specifier pair ("io-channels") to the ADC controller.
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ADC clients must use the format described in
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https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
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giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
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properties:
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compatible:
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@ -24,7 +24,9 @@ properties:
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description: >
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List of phandle and IIO specifier pairs.
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Each pair defines one ADC channel to which a joystick axis is connected.
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See Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
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See
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https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml
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for details.
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'#address-cells':
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const: 1
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@ -5,7 +5,10 @@ Required properties:
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- compatible: must be "resistive-adc-touch"
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The device must be connected to an ADC device that provides channels for
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position measurement and optional pressure.
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Refer to ../iio/iio-bindings.txt for details
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Refer to
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https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml
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for details
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- iio-channels: must have at least two channels connected to an ADC device.
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These should correspond to the channels exposed by the ADC device and should
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have the right index as the ADC device registers them. These channels
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CZ.NIC's Turris Omnia LEDs driver
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maintainers:
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- Marek Behún <marek.behun@nic.cz>
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- Marek Behún <kabel@kernel.org>
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description:
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This module adds support for the RGB LEDs found on the front panel of the
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@ -72,7 +72,9 @@ Required child device properties:
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pwm|regulator|rtc|sysctrl|usb]";
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A few child devices require ADC channels from the GPADC node. Those follow the
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standard bindings from iio/iio-bindings.txt and iio/adc/adc.txt
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standard bindings from
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https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml
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and Documentation/devicetree/bindings/iio/adc/adc.yaml
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abx500-temp : io-channels "aux1" and "aux2" for measuring external
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temperatures.
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@ -16,14 +16,14 @@ Optional subnodes:
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The sub-functions of CPCAP get their own node with their own compatible values,
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which are described in the following files:
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- ../power/supply/cpcap-battery.txt
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- ../power/supply/cpcap-charger.txt
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- ../regulator/cpcap-regulator.txt
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- ../phy/phy-cpcap-usb.txt
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- ../input/cpcap-pwrbutton.txt
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- ../rtc/cpcap-rtc.txt
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- ../leds/leds-cpcap.txt
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- ../iio/adc/cpcap-adc.txt
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- Documentation/devicetree/bindings/power/supply/cpcap-battery.txt
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- Documentation/devicetree/bindings/power/supply/cpcap-charger.txt
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- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
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- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
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- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
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- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt
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- Documentation/devicetree/bindings/leds/leds-cpcap.txt
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- Documentation/devicetree/bindings/iio/adc/motorola,cpcap-adc.yaml
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The only exception is the audio codec. Instead of a compatible value its
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node must be named "audio-codec".
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@ -32,7 +32,7 @@ required:
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- interrupts
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- interrupt-names
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |
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@ -49,7 +49,7 @@ properties:
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description:
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Reference to an nvmem node for the MAC address
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nvmem-cells-names:
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nvmem-cell-names:
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const: mac-address
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phy-connection-type:
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@ -65,6 +65,71 @@ KSZ9031:
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step is 60ps. The default value is the neutral setting, so setting
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rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
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The KSZ9031 hardware supports a range of skew values from negative to
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positive, where the specific range is property dependent. All values
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specified in the devicetree are offset by the minimum value so they
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can be represented as positive integers in the devicetree since it's
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difficult to represent a negative number in the devictree.
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The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
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Pad Skew Value Delay (ps) Devicetree Value
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------------------------------------------------------
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0_0000 -900ps 0
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0_0001 -840ps 60
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0_0010 -780ps 120
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0_0011 -720ps 180
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0_0100 -660ps 240
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0_0101 -600ps 300
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0_0110 -540ps 360
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0_0111 -480ps 420
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0_1000 -420ps 480
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0_1001 -360ps 540
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0_1010 -300ps 600
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0_1011 -240ps 660
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0_1100 -180ps 720
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0_1101 -120ps 780
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0_1110 -60ps 840
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0_1111 0ps 900
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1_0000 60ps 960
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1_0001 120ps 1020
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1_0010 180ps 1080
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1_0011 240ps 1140
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1_0100 300ps 1200
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1_0101 360ps 1260
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1_0110 420ps 1320
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1_0111 480ps 1380
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1_1000 540ps 1440
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1_1001 600ps 1500
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1_1010 660ps 1560
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1_1011 720ps 1620
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1_1100 780ps 1680
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1_1101 840ps 1740
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1_1110 900ps 1800
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1_1111 960ps 1860
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The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
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data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
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Pad Skew Value Delay (ps) Devicetree Value
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------------------------------------------------------
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0000 -420ps 0
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0001 -360ps 60
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0010 -300ps 120
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0011 -240ps 180
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0100 -180ps 240
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0101 -120ps 300
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0110 -60ps 360
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0111 0ps 420
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1000 60ps 480
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1001 120ps 540
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1010 180ps 600
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1011 240ps 660
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1100 300ps 720
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1101 360ps 780
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1110 420ps 840
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1111 480ps 900
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Optional properties:
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Maximum value of 1860, default value 900:
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@ -120,11 +185,21 @@ KSZ9131:
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Examples:
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/* Attach to an Ethernet device with autodetected PHY */
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&enet {
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rxc-skew-ps = <1800>;
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rxdv-skew-ps = <0>;
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txc-skew-ps = <1800>;
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txen-skew-ps = <0>;
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status = "okay";
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};
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/* Attach to an explicitly-specified PHY */
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mdio {
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <3000>;
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rxc-skew-ps = <1800>;
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rxdv-skew-ps = <0>;
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txc-skew-ps = <3000>;
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txc-skew-ps = <1800>;
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txen-skew-ps = <0>;
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reg = <0>;
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};
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@ -133,3 +208,20 @@ Examples:
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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References
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Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
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http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
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Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
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http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
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Notes:
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Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
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was missing extended register 106 (transmit data pad skews), and
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incorrectly specified the ps per step as 200ps/step instead of
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120ps/step. The latest update to this document reflects the latest
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revision of the Micrel specification even though usage in the kernel
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still reflects that incorrect document.
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@ -2,7 +2,7 @@
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/*
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* Constant for device tree bindings for Turris Mox module configuration bus
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*
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* Copyright (C) 2019 Marek Behun <marek.behun@nic.cz>
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* Copyright (C) 2019 Marek Behún <kabel@kernel.org>
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*/
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#ifndef _DT_BINDINGS_BUS_MOXTET_H
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memory {
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device_type = "memory";
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/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
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reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
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0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
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};
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@ -40,6 +40,9 @@
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ethernet1 = &cpsw_emac1;
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spi0 = &spi0;
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spi1 = &spi1;
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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};
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cpus {
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@ -32,7 +32,8 @@
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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@ -389,6 +390,7 @@
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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marvell,reg-init = <3 18 0 0x4985>;
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/* irq is connected to &pcawan pin 7 */
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};
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@ -334,14 +334,6 @@
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};
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&pinctrl {
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atmel,mux-mask = <
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/* A B C */
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0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
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0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
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0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
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0x003FFFFF 0x003F8000 0x00000000 /* pioD */
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>;
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adc {
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pinctrl_adc_default: adc_default {
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atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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@ -84,8 +84,8 @@
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pinctrl-0 = <&pinctrl_macb0_default>;
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phy-mode = "rmii";
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ethernet-phy@0 {
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reg = <0x0>;
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ethernet-phy@7 {
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reg = <0x7>;
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interrupt-parent = <&pioA>;
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interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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@ -308,14 +308,6 @@
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#reset-cells = <1>;
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};
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bsc_intr: interrupt-controller@7ef00040 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7ef00040 0x30>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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aon_intr: interrupt-controller@7ef00100 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7ef00100 0x30>;
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@ -362,8 +354,6 @@
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reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
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reg-names = "bsc", "auto-i2c";
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clock-frequency = <97500>;
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interrupt-parent = <&bsc_intr>;
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interrupts = <0>;
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status = "disabled";
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};
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@ -405,8 +395,6 @@
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reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
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reg-names = "bsc", "auto-i2c";
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clock-frequency = <97500>;
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interrupt-parent = <&bsc_intr>;
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interrupts = <1>;
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status = "disabled";
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};
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};
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@ -433,6 +433,7 @@
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pinctrl-0 = <&pinctrl_usdhc2>;
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cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vdd_sd1_reg>;
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status = "disabled";
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};
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@ -442,5 +443,6 @@
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&pinctrl_usdhc3_cdwp>;
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cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vdd_sd0_reg>;
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status = "disabled";
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};
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@ -210,9 +210,6 @@
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100>;
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};
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@ -222,9 +219,6 @@
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio_spi 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100>;
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};
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};
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};
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@ -243,6 +237,22 @@
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status = "okay";
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};
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&gpio_spi {
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eth0-phy-hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "eth0-phy";
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};
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eth1-phy-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "eth1-phy";
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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@ -14,5 +14,6 @@
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};
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&gpmi {
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fsl,use-minimum-ecc;
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status = "okay";
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};
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@ -24,6 +24,9 @@
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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@ -22,6 +22,11 @@
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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mmc3 = &mmc4;
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mmc4 = &mmc5;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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@ -770,14 +770,6 @@
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ti,max-div = <2>;
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};
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sha2md5_fck: sha2md5_fck@15c8 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3_div_ck>;
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ti,bit-shift = <1>;
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reg = <0x15c8>;
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};
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usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
|
@ -25,6 +25,11 @@
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
i2c4 = &i2c5;
|
||||
mmc0 = &mmc1;
|
||||
mmc1 = &mmc2;
|
||||
mmc2 = &mmc3;
|
||||
mmc3 = &mmc4;
|
||||
mmc4 = &mmc5;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
|
@ -606,6 +606,15 @@
|
||||
compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe03fff 0xef00019d /* pioA */
|
||||
0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
|
||||
0xffffffff 0xffffffff 0xf83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
|
@ -19,3 +19,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
broken-cd; /* card detect is broken on *some* boards */
|
||||
};
|
||||
|
@ -34,7 +34,7 @@
|
||||
vmmc-supply = <®_dcdc1>;
|
||||
disable-wp;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
|
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -289,10 +289,6 @@
|
||||
vcc-pm-supply = <®_aldo1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&ext_osc32k>;
|
||||
};
|
||||
|
||||
&spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -995,9 +995,9 @@
|
||||
compatible = "allwinner,sun8i-a23-rsb";
|
||||
reg = <0x07083000 0x400>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&r_ccu 13>;
|
||||
clocks = <&r_ccu CLK_R_APB2_RSB>;
|
||||
clock-frequency = <3000000>;
|
||||
resets = <&r_ccu 7>;
|
||||
resets = <&r_ccu RST_R_APB2_RSB>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&r_rsb_pins>;
|
||||
status = "disabled";
|
||||
|
@ -198,6 +198,7 @@
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
|
@ -348,6 +348,7 @@
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <0 75 0x4>;
|
||||
dma-coherent;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
|
@ -354,6 +354,7 @@
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
|
@ -124,7 +124,7 @@
|
||||
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
|
@ -35,7 +35,7 @@
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
|
@ -67,7 +67,7 @@
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
|
@ -130,7 +130,7 @@
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
|
@ -1,7 +1,7 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for CZ.NIC Turris Mox Board
|
||||
* 2019 by Marek Behun <marek.behun@nic.cz>
|
||||
* 2019 by Marek Behún <kabel@kernel.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
@ -310,9 +310,11 @@
|
||||
};
|
||||
|
||||
CP11X_LABEL(sata0): sata@540000 {
|
||||
compatible = "marvell,armada-8k-ahci";
|
||||
compatible = "marvell,armada-8k-ahci",
|
||||
"generic-ahci";
|
||||
reg = <0x540000 0x30000>;
|
||||
dma-coherent;
|
||||
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&CP11X_LABEL(clk) 1 15>,
|
||||
<&CP11X_LABEL(clk) 1 16>;
|
||||
#address-cells = <1>;
|
||||
@ -320,12 +322,10 @@
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
sata-port@1 {
|
||||
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
@ -10,7 +10,7 @@
|
||||
model = "NVIDIA Jetson TX2 Developer Kit";
|
||||
compatible = "nvidia,p2771-0000", "nvidia,tegra186";
|
||||
|
||||
aconnect {
|
||||
aconnect@2900000 {
|
||||
status = "okay";
|
||||
|
||||
dma-controller@2930000 {
|
||||
|
@ -23,7 +23,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon console=ttyS0,115200n8";
|
||||
bootargs = "earlycon console=ttyS0,115200n8 fw_devlink=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
|
@ -73,7 +73,7 @@
|
||||
snps,rxpbl = <8>;
|
||||
};
|
||||
|
||||
aconnect {
|
||||
aconnect@2900000 {
|
||||
compatible = "nvidia,tegra186-aconnect",
|
||||
"nvidia,tegra210-aconnect";
|
||||
clocks = <&bpmp TEGRA186_CLK_APE>,
|
||||
|
@ -651,6 +651,8 @@
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
|
||||
clock-names = "mclk";
|
||||
realtek,jd-src = <2>;
|
||||
sound-name-prefix = "CVB-RT";
|
||||
|
||||
@ -658,7 +660,6 @@
|
||||
rt5658_ep: endpoint {
|
||||
remote-endpoint = <&i2s1_dap_ep>;
|
||||
mclk-fs = <256>;
|
||||
clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -5,6 +5,10 @@
|
||||
model = "NVIDIA Jetson Xavier NX (SD-card)";
|
||||
compatible = "nvidia,p3668-0000", "nvidia,tegra194";
|
||||
|
||||
aliases {
|
||||
mmc0 = "/bus@0/mmc@3400000";
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
/* SDMMC1 (SD/MMC) */
|
||||
mmc@3400000 {
|
||||
|
@ -5,6 +5,10 @@
|
||||
model = "NVIDIA Jetson Xavier NX (eMMC)";
|
||||
compatible = "nvidia,p3668-0001", "nvidia,tegra194";
|
||||
|
||||
aliases {
|
||||
mmc0 = "/bus@0/mmc@3460000";
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
/* SDMMC4 (eMMC) */
|
||||
mmc@3460000 {
|
||||
|
@ -14,7 +14,6 @@
|
||||
i2c5 = "/bus@0/i2c@31c0000";
|
||||
i2c6 = "/bus@0/i2c@c250000";
|
||||
i2c7 = "/bus@0/i2c@31e0000";
|
||||
mmc0 = "/bus@0/mmc@3460000";
|
||||
rtc0 = "/bpmp/i2c/pmic@3c";
|
||||
rtc1 = "/bus@0/rtc@c2a0000";
|
||||
serial0 = &tcu;
|
||||
|
Loading…
Reference in New Issue
Block a user