cxgbe(4): Update T4 and T5 firmwares to 1.14.2.0.
Obtained from: Chelsio Communications MFC after: 3 days
This commit is contained in:
Navdeep Parhar
parent
577f7474b0
commit
c7dbd80213
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=285527
@ -1201,7 +1201,7 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.14.2.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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@ -1225,7 +1225,7 @@ t5fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.14.2.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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File diff suppressed because it is too large
Load Diff
9486
sys/dev/cxgbe/firmware/t4fw-1.14.2.0.bin.uu
Normal file
9486
sys/dev/cxgbe/firmware/t4fw-1.14.2.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -112,7 +112,7 @@
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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# TP_VLAN_PRI_MAP to select filter tuples
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# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
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@ -125,7 +125,7 @@
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP RX payload
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tp_pmrx = 34, 512
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tp_pmrx = 34
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# TP RX payload page size
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tp_pmrx_pagesize = 64K
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@ -135,7 +135,7 @@
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP TX payload
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tp_pmtx = 32, 512
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tp_pmtx = 32
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# TP TX payload page size
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tp_pmtx_pagesize = 64K
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@ -146,6 +146,9 @@
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# TP OFLD MTUs
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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
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# ULPRX iSCSI Page Sizes
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reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
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# Some "definitions" to make the rest of this a bit more readable. We support
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# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
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# per function per port ...
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@ -392,7 +395,7 @@
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pmask = all # access to all four ports ...
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nserver = 16
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nhash = 2048
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tp_l2t = 1024
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tp_l2t = 1020
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protocol = iscsi_initiator_fofld
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tp_ddp_iscsi = 2
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iscsi_ntask = 2048
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@ -413,6 +416,7 @@
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nhash = 2048
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tp_l2t = 4
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protocol = fcoe_initiator
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tp_ddp = 1
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fcoe_nfcf = 16
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@ -543,8 +547,8 @@
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dcb_app_tlv[2] = 3260, socketnum, 5
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[fini]
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version = 0x14250012
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checksum = 0x22f592a9
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version = 0x1425001c
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checksum = 0x63a652b3
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
10447
sys/dev/cxgbe/firmware/t5fw-1.14.2.0.bin.uu
Normal file
10447
sys/dev/cxgbe/firmware/t5fw-1.14.2.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,49 +1,34 @@
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# Chelsio T5 Factory Default configuration file.
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#
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# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved.
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# Copyright (C) 2010-2015 Chelsio Communications. All rights reserved.
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#
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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
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# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
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# IN PHYSICAL DAMAGE TO T4 ADAPTERS.
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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
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# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
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# TO ADAPTERS.
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# This file provides the default, power-on configuration for 4-port T4-based
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# This file provides the default, power-on configuration for 4-port T5-based
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# adapters shipped from the factory. These defaults are designed to address
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# the needs of the vast majority of T4 customers. The basic idea is to have
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# a default configuration which allows a customer to plug a T4 adapter in and
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# have it work regardless of OS, driver or application except in the most
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# unusual and/or demanding customer applications.
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# the needs of the vast majority of Terminator customers. The basic idea is to
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# have a default configuration which allows a customer to plug a Terminator
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# adapter in and have it work regardless of OS, driver or application except in
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# the most unusual and/or demanding customer applications.
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#
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# Many of the T4 resources which are described by this configuration are
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# finite. This requires balancing the configuration/operation needs of
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# Many of the Terminator resources which are described by this configuration
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# are finite. This requires balancing the configuration/operation needs of
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# device drivers across OSes and a large number of customer application.
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#
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# Some of the more important resources to allocate and their constaints are:
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# 1. Virtual Interfaces: 128.
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# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
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# must use a power of 2 Ingress Queues.
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# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
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# power of 2 Egress Queues.
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# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
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# Virtual Functions based off of a Physical Function all get the
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# same umber of MSI-X Vectors as the base Physical Function.
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# Additionally, regardless of whether Virtual Functions are enabled or
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# not, their MSI-X "needs" are counted by the PCI-E implementation.
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# And finally, all Physical Funcations capable of supporting Virtual
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# Functions (PF0-3) must have the same number of configured TotalVFs in
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# their SR-IOV Capabilities.
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# 1. Virtual Interfaces: 256.
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# 2. Ingress Queues with Free Lists: 1024.
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# 3. Egress Queues: 128K.
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# 4. MSI-X Vectors: 1088.
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# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
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# address matching on Ingress Packets.
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#
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# Some of the important OS/Driver resource needs are:
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# 6. Some OS Drivers will manage all resources through a single Physical
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# Function (currently PF0 but it could be any Physical Function). Thus,
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# this "Unified PF" will need to have enough resources allocated to it
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# to allow for this. And because of the MSI-X resource allocation
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# constraints mentioned above, this probably means we'll either have to
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# severely limit the TotalVFs if we continue to use PF0 as the Unified PF
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# or we'll need to move the Unified PF into the PF4-7 range since those
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# Physical Functions don't have any Virtual Functions associated with
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# them.
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# Function (currently PF4 but it could be any Physical Function).
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# 7. Some OS Drivers will manage different ports and functions (NIC,
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# storage, etc.) on different Physical Functions. For example, NIC
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# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
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@ -64,12 +49,10 @@
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# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
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# (Plus a few for Firmware Event Queues, etc.)
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#
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# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
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# Virtual Machines to directly access T4 functionality via SR-IOV
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# Virtual Functions and "PCI Device Passthrough" -- this is especially
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# true for the NIC application functionality. (Note that there is
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# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual
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# Functions so this is in fact solely limited to NIC.)
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# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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# Machines to directly access T6 functionality via SR-IOV Virtual Functions
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# and "PCI Device Passthrough" -- this is especially true for the NIC
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# application functionality.
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#
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@ -80,7 +63,7 @@
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rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
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# PL_TIMEOUT register
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pl_timeout_value = 200 # the timeout value in units of us
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pl_timeout_value = 10000 # the timeout value in units of us
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# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
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# Page Size and a 64B L1 Cache Line Size. It programs the
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@ -138,7 +121,7 @@
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
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# filter control: compact, fcoemask
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@ -146,14 +129,14 @@
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# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
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# protocol, tos, vlan, vnic_id, port, fcoe
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# valid filterModes are described the Terminator 5 Data Book
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filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
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filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
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# filter tuples enforced in LE active region (equal to or subset of filterMode)
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filterMask = protocol, fcoe
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP RX payload
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tp_pmrx = 30, 512
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tp_pmrx = 30
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# TP RX payload page size
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tp_pmrx_pagesize = 64K
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@ -163,7 +146,7 @@
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP TX payload
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tp_pmtx = 50, 512
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tp_pmtx = 50
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# TP TX payload page size
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tp_pmtx_pagesize = 64K
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@ -183,6 +166,9 @@
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# TP_PARA_REG0
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reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
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# ULPRX iSCSI Page Sizes
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reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
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# LE_DB_CONFIG
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reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable
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@ -218,7 +204,7 @@
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# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
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# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
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# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
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#
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#
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# NVI_OFLD = 0 # Offload uses NIC function to access ports
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# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
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# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
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@ -322,20 +308,21 @@
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# PF2_INT = 8 # NCPUS
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# PF3_INT = 8 # NCPUS
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# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
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#
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#
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# PF4_INT = 128 # NMSIX_UNIFIED
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# PF5_INT = 32 # NMSIX_STORAGE
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# PF6_INT = 32 # NMSIX_STORAGE
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# PF7_INT = 0 # Nothing Assigned
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# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
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#
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#
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# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
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#
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#
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# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
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# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
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#
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# NVF = 16
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# For those OSes which manage different ports on different PFs, we need
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# only enough resources to support a single port's NIC application functions
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# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
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@ -354,6 +341,7 @@
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cmask = all # access to all channels
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pmask = 0x1 # access to only one port
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[function "1"]
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nvf = 16 # NVF on this function
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wx_caps = all # write/execute permissions for all commands
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@ -366,6 +354,7 @@
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cmask = all # access to all channels
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pmask = 0x2 # access to only one port
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[function "2"]
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nvf = 16 # NVF on this function
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wx_caps = all # write/execute permissions for all commands
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@ -378,6 +367,7 @@
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cmask = all # access to all channels
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pmask = 0x4 # access to only one port
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[function "3"]
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nvf = 16 # NVF on this function
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wx_caps = all # write/execute permissions for all commands
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@ -390,6 +380,7 @@
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cmask = all # access to all channels
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pmask = 0x8 # access to only one port
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# Some OS Drivers manage all application functions for all ports via PF4.
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# Thus we need to provide a large number of resources here. For Egress
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# Queues we need to account for both TX Queues as well as Free List Queues
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@ -403,6 +394,7 @@
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niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
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nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
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neq = 256 # NEQ_UNIFIED + NEQ_WD
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nqpcq = 12288
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nexactf = 40 # NMPSTCAM_UNIFIED
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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@ -412,7 +404,7 @@
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nfilter = 496 # number of filter region entries
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nserver = 496 # number of server region entries
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nhash = 12288 # number of hash region entries
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protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
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protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif
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tp_l2t = 3072
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tp_ddp = 2
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tp_ddp_iscsi = 2
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@ -420,6 +412,7 @@
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tp_pbl = 5
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tp_rq = 7
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# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
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# need to have Virtual Interfaces on each of the four ports with up to NCPUS
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# "Queue Sets" each.
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@ -431,7 +424,7 @@
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niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
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nethctrl = 32 # NPORTS*NCPUS
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neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
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nexactf = 4 # NPORTS
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nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nserver = 16
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@ -444,6 +437,7 @@
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iscsi_nconn_per_session = 1
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iscsi_ninitiator_instance = 64
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[function "6"]
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wx_caps = all # write/execute permissions for all commands
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r_caps = all # read permissions for all commands
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@ -463,6 +457,8 @@
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fcoe_nfcf = 16
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fcoe_nvnp = 32
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fcoe_nssn = 1024
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fcoe_nfcb = 256
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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@ -477,6 +473,7 @@
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nexactf = 8 # NPORTS + DCBX +
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nfilter = 16 # number of filter region entries
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# For Virtual functions, we only allow NIC functionality and we only allow
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# access to one port (1 << PF). Note that because of limitations in the
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# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
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@ -494,6 +491,7 @@
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cmask = all # access to all channels
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pmask = 0x1 # access to only one port ...
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[function "1/*"] # NVF
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wx_caps = 0x82 # DMAQ | VF
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r_caps = 0x86 # DMAQ | VF | PORT
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@ -505,6 +503,7 @@
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cmask = all # access to all channels
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pmask = 0x2 # access to only one port ...
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[function "2/*"] # NVF
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wx_caps = 0x82 # DMAQ | VF
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r_caps = 0x86 # DMAQ | VF | PORT
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@ -516,6 +515,7 @@
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cmask = all # access to all channels
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pmask = 0x4 # access to only one port ...
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[function "3/*"] # NVF
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wx_caps = 0x82 # DMAQ | VF
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r_caps = 0x86 # DMAQ | VF | PORT
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@ -527,6 +527,7 @@
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cmask = all # access to all channels
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pmask = 0x8 # access to only one port ...
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# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
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# for packets from the wire as well as the loopback path of the L2 switch. The
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# folling params control how the buffer memory is distributed and the L2 flow
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@ -552,6 +553,7 @@
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "1"]
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dcb = ppp, dcbx
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bg_mem = 25
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@ -563,6 +565,7 @@
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "2"]
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dcb = ppp, dcbx
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bg_mem = 25
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@ -574,6 +577,7 @@
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dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
|
||||
[port "3"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
@ -585,9 +589,10 @@
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
|
||||
[fini]
|
||||
version = 0x14250016
|
||||
checksum = 0xafaf8723
|
||||
version = 0x1425001c
|
||||
checksum = 0xb1c3ae38
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
@ -6342,9 +6342,9 @@ sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
|
||||
F_FW_CMD_REQUEST | F_FW_CMD_READ |
|
||||
V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
|
||||
ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
|
||||
ldst_cmd.u.mps.fid_ctl =
|
||||
ldst_cmd.u.mps.rplc.fid_idx =
|
||||
htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
|
||||
V_FW_LDST_CMD_CTL(i));
|
||||
V_FW_LDST_CMD_IDX(i));
|
||||
|
||||
rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
|
||||
"t4mps");
|
||||
@ -6360,10 +6360,10 @@ sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
|
||||
rc = 0;
|
||||
} else {
|
||||
sbuf_printf(sb, " %08x %08x %08x %08x",
|
||||
be32toh(ldst_cmd.u.mps.rplc127_96),
|
||||
be32toh(ldst_cmd.u.mps.rplc95_64),
|
||||
be32toh(ldst_cmd.u.mps.rplc63_32),
|
||||
be32toh(ldst_cmd.u.mps.rplc31_0));
|
||||
be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
|
||||
be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
|
||||
be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
|
||||
be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
|
||||
}
|
||||
} else
|
||||
sbuf_printf(sb, "%36s", "");
|
||||
|
||||
@ -501,25 +501,23 @@ write_tx_wr(void *dst, struct toepcb *toep, unsigned int immdlen,
|
||||
|
||||
/* for iscsi, the mode & submode setting is per-packet */
|
||||
if (toep->ulp_mode == ULP_MODE_ISCSI)
|
||||
wr_ulp_mode = V_FW_OFLD_TX_DATA_WR_ULPMODE(ulp_mode >> 4) |
|
||||
V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(ulp_mode & 3);
|
||||
wr_ulp_mode = V_TX_ULP_MODE(ulp_mode >> 4) |
|
||||
V_TX_ULP_SUBMODE(ulp_mode & 3);
|
||||
else
|
||||
wr_ulp_mode = V_FW_OFLD_TX_DATA_WR_ULPMODE(toep->ulp_mode);
|
||||
wr_ulp_mode = V_TX_ULP_MODE(toep->ulp_mode);
|
||||
|
||||
txwr->lsodisable_to_proxy =
|
||||
htobe32(wr_ulp_mode |
|
||||
V_FW_OFLD_TX_DATA_WR_URGENT(0) | /* XXX */
|
||||
V_FW_OFLD_TX_DATA_WR_SHOVE(shove));
|
||||
txwr->lsodisable_to_flags = htobe32(wr_ulp_mode | V_TX_URG(0) | /*XXX*/
|
||||
V_TX_SHOVE(shove));
|
||||
txwr->plen = htobe32(plen);
|
||||
|
||||
if (txalign > 0) {
|
||||
struct tcpcb *tp = intotcpcb(toep->inp);
|
||||
|
||||
if (plen < 2 * tp->t_maxseg || is_10G_port(toep->port))
|
||||
txwr->lsodisable_to_proxy |=
|
||||
txwr->lsodisable_to_flags |=
|
||||
htobe32(F_FW_OFLD_TX_DATA_WR_LSODISABLE);
|
||||
else
|
||||
txwr->lsodisable_to_proxy |=
|
||||
txwr->lsodisable_to_flags |=
|
||||
htobe32(F_FW_OFLD_TX_DATA_WR_ALIGNPLD |
|
||||
(tp->t_flags & TF_NODELAY ? 0 :
|
||||
F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE));
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER= 1.11.27.0
|
||||
T4FW_VER= 1.14.2.0
|
||||
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES+= t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER= 1.11.27.0
|
||||
T5FW_VER= 1.14.2.0
|
||||
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES+= t5fw.fw
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user