Merge rev 1.11 (-mno-align-long-strings) into Gcc 3.2.1 release.
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4172a45f81
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=107597
@ -51,14 +51,6 @@ Boston, MA 02111-1307, USA. */
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#define CHECK_STACK_LIMIT (-1)
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#endif
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#warning NEED TO REVISIT "PIC_REG_USED" AND -mprofiler-epilogue SUPPORT
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#if 0
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#define PIC_REG_USED \
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(flag_pic && (current_function_uses_pic_offset_table \
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|| current_function_uses_const_pool \
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|| profile_flag || profile_block_flag))
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#endif
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/* Processor costs (relative to an add) */
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static const
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struct processor_costs size_cost = { /* costs for tunning for size */
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@ -918,6 +910,27 @@ override_options ()
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int const pta_size = sizeof (processor_alias_table) / sizeof (struct pta);
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/* Set the default values for switches whose default depends on TARGET_64BIT
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in case they weren't overwriten by command line options. */
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if (TARGET_64BIT)
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{
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if (flag_omit_frame_pointer == 2)
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flag_omit_frame_pointer = 1;
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if (flag_asynchronous_unwind_tables == 2)
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flag_asynchronous_unwind_tables = 1;
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if (flag_pcc_struct_return == 2)
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flag_pcc_struct_return = 0;
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}
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else
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{
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if (flag_omit_frame_pointer == 2)
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flag_omit_frame_pointer = 0;
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if (flag_asynchronous_unwind_tables == 2)
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flag_asynchronous_unwind_tables = 0;
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if (flag_pcc_struct_return == 2)
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flag_pcc_struct_return = 1;
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}
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#ifdef SUBTARGET_OVERRIDE_OPTIONS
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SUBTARGET_OVERRIDE_OPTIONS;
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#endif
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@ -1225,13 +1238,14 @@ optimization_options (level, size)
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if (level > 1)
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flag_schedule_insns = 0;
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#endif
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if (TARGET_64BIT && optimize >= 1)
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flag_omit_frame_pointer = 1;
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if (TARGET_64BIT)
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{
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flag_pcc_struct_return = 0;
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flag_asynchronous_unwind_tables = 1;
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}
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/* The default values of these switches depend on the TARGET_64BIT
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that is not known at this moment. Mark these values with 2 and
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let user the to override these. In case there is no command line option
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specifying them, we will set the defaults in override_options. */
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if (optimize >= 1)
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flag_omit_frame_pointer = 2;
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flag_pcc_struct_return = 2;
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flag_asynchronous_unwind_tables = 2;
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}
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/* Table of valid machine attributes. */
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@ -6874,8 +6888,7 @@ ix86_expand_vector_move (mode, operands)
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/* Make operand1 a register if it isn't already. */
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if ((reload_in_progress | reload_completed) == 0
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&& !register_operand (operands[0], mode)
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&& !register_operand (operands[1], mode)
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&& operands[1] != CONST0_RTX (mode))
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&& !register_operand (operands[1], mode))
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{
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rtx temp = force_reg (GET_MODE (operands[1]), operands[1]);
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emit_move_insn (operands[0], temp);
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@ -10973,14 +10986,10 @@ static const struct builtin_description bdesc_2arg[] =
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpgtss", IX86_BUILTIN_CMPGTSS, LT, 1 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpgess", IX86_BUILTIN_CMPGESS, LE, 1 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, EQ, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, LT, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, LE, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, LT, 1 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, LE, 1 },
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{ MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
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{ MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
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