Define only the CP15 register operations that are valid for the architecture.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=276213
@ -99,12 +99,13 @@
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#if __ARM_ARCH >= 6
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/* From ARMv6: */
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#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */
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#endif
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#if __ARM_ARCH >= 7
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/* From ARMv7: */
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#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */
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#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */
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#endif
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/*
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* CP15 C6 registers
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*/
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@ -118,7 +119,7 @@
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/*
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* CP15 C7 registers
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*/
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH >= 7 && defined(SMP)
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/* From ARMv7: */
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#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */
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#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */
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@ -128,14 +129,14 @@
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#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */
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#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH == 6
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/* Deprecated in ARMv7 */
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#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */
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#endif
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#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */
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#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH == 6
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/* Only ARMv6: */
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#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */
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#endif
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@ -147,7 +148,7 @@
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#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */
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#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH >= 7
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/* From ARMv7: */
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#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */
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#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */
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@ -155,24 +156,24 @@
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#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */
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#endif
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH == 6
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/* Only ARMv6: */
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#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */
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#endif
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#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */
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#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH == 6
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/* Only ARMv6: */
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#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */
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#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */
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#endif
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH >= 7
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/* From ARMv7: */
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#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */
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#endif
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH == 6
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/* Only ARMv6: */
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#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */
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#endif
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@ -182,7 +183,7 @@
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/*
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* CP15 C8 registers
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*/
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#if __ARM_ARCH >= 6
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#if __ARM_ARCH >= 7 && defined(SMP)
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/* From ARMv7: */
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#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
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#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */
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@ -229,4 +230,9 @@
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#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */
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#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
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/*
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* CP15 C15 registers
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*/
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#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */
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#endif /* !MACHINE_SYSREG_H */
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