Add a PCI driver that follows the Arm DEN0115 spec
Add a n attachment to the pci_host_generic driver for the Arm DEN0115 PCI Configuration Space Access Firmware Interface [1]. This can be used when PCI controllers need to implement quirks in the PCI root bus. To handle this the firmware implements a SMCCC interface the driver can use to read and write the configuration register. This has been tested on a Raspberry Pi 4 booting with EDK2. [1] https://developer.arm.com/documentation/den0115/latest Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D39228
This commit is contained in:
Andrew Turner
parent
7029f2c887
commit
c9a05c0722
@ -359,6 +359,7 @@ dev/ofw/ofw_pcib.c optional fdt pci
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dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi
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dev/pci/pci_host_generic.c optional pci
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dev/pci/pci_host_generic_acpi.c optional pci acpi
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dev/pci/pci_host_generic_den0115.c optional pci acpi
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dev/pci/pci_host_generic_fdt.c optional pci fdt
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dev/pci/pci_dw_mv.c optional pci fdt
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dev/pci/pci_dw.c optional pci fdt
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247
sys/dev/pci/pci_host_generic_den0115.c
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247
sys/dev/pci/pci_host_generic_den0115.c
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@ -0,0 +1,247 @@
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/*-
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* Copyright (c) 2022 Andrew Turner
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* Copyright (c) 2023 Arm Ltd
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/acpica/acpi_pcibvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pci_host_generic_acpi.h>
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#include <dev/psci/psci.h>
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#include "pcib_if.h"
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static device_probe_t pci_host_acpi_smccc_probe;
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static device_attach_t pci_host_acpi_smccc_attach;
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static pcib_read_config_t pci_host_acpi_smccc_read_config;
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static pcib_write_config_t pci_host_acpi_smccc_write_config;
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static int
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pci_host_acpi_smccc_probe(device_t dev)
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{
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ACPI_DEVICE_INFO *devinfo;
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struct resource *res;
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ACPI_HANDLE h;
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uint32_t smccc_version;
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int rid, root;
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if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
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ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
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return (ENXIO);
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root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
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AcpiOsFree(devinfo);
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if (!root)
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return (ENXIO);
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/*
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* Check we have memory resources. We may have a non-memory
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* mapped device, e.g. using the Arm PCI Configuration Space
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* Access Firmware Interface (DEN0115).
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*/
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res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
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if (res != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
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return (ENXIO);
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}
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/* Check the SMCCC is at least v1.1 */
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smccc_version = smccc_get_version();
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if (SMCCC_VERSION_MAJOR(smccc_version) > 1 ||
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(SMCCC_VERSION_MAJOR(smccc_version) == 1 &&
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SMCCC_VERSION_MINOR(smccc_version) == 0)) {
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device_set_desc(dev,
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"ARM PCI Firmware config space host controller");
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return (BUS_PROBE_SPECIFIC);
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}
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return (EINVAL);
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}
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#define SMCCC_PCI_VERSION \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \
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SMCCC_STD_SECURE_SERVICE_CALLS, 0x130)
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#define SMCCC_PCI_FEATURES \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \
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SMCCC_STD_SECURE_SERVICE_CALLS, 0x131)
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#define SMCCC_PCI_READ \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \
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SMCCC_STD_SECURE_SERVICE_CALLS, 0x132)
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#define SMCCC_PCI_WRITE \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \
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SMCCC_STD_SECURE_SERVICE_CALLS, 0x133)
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#define SMCCC_PCI_GET_SEG_INFO \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \
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SMCCC_STD_SECURE_SERVICE_CALLS, 0x134)
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CTASSERT(SMCCC_PCI_VERSION == 0x84000130);
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CTASSERT(SMCCC_PCI_FEATURES == 0x84000131);
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CTASSERT(SMCCC_PCI_READ == 0x84000132);
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CTASSERT(SMCCC_PCI_WRITE == 0x84000133);
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CTASSERT(SMCCC_PCI_GET_SEG_INFO == 0x84000134);
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#define SMCCC_PCI_MAJOR(x) (((x) >> 16) & 0x7fff)
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#define SMCCC_PCI_MINOR(x) ((x) & 0xffff)
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#define SMCCC_PCI_SEG_END(x) (((x) >> 8) & 0xff)
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#define SMCCC_PCI_SEG_START(x) ((x) & 0xff)
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static bool
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pci_host_acpi_smccc_has_feature(uint32_t pci_func_id)
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{
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struct arm_smccc_res result;
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if (psci_callfn(SMCCC_PCI_FEATURES, pci_func_id, 0, 0, 0, 0, 0, 0,
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&result) < 0) {
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return (false);
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}
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return (true);
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}
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static int
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pci_host_acpi_smccc_attach(device_t dev)
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{
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struct generic_pcie_acpi_softc *sc;
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struct arm_smccc_res result;
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int end, start;
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int error;
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sc = device_get_softc(dev);
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sc->base.quirks |= PCIE_CUSTOM_CONFIG_SPACE_QUIRK;
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MPASS(psci_callfn != NULL);
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/* Check there is a version */
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if (psci_callfn(SMCCC_PCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &result) < 0) {
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device_printf(dev,
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"Failed to read the SMCCC PCI version: %lx\n", result.a0);
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return (ENXIO);
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}
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if (bootverbose) {
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device_printf(dev, "Firmware v%d.%d\n",
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SMCCC_PCI_MAJOR((uint32_t)result.a0),
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SMCCC_PCI_MINOR((uint32_t)result.a0));
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}
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if (!pci_host_acpi_smccc_has_feature(SMCCC_PCI_READ) ||
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!pci_host_acpi_smccc_has_feature(SMCCC_PCI_WRITE)) {
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device_printf(dev, "Missing read/write functions\n");
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return (ENXIO);
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}
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error = pci_host_generic_acpi_init(dev);
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if (error != 0)
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return (error);
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if (pci_host_acpi_smccc_has_feature(SMCCC_PCI_GET_SEG_INFO) &&
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psci_callfn(SMCCC_PCI_GET_SEG_INFO, sc->base.ecam, 0, 0, 0, 0, 0,
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0, &result) == SMCCC_RET_SUCCESS) {
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start = SMCCC_PCI_SEG_START(result.a1);
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end = SMCCC_PCI_SEG_END(result.a1);
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sc->base.bus_start = MAX(sc->base.bus_start, start);
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sc->base.bus_end = MIN(sc->base.bus_end, end);
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}
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static uint32_t
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pci_host_acpi_smccc_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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struct generic_pcie_acpi_softc *sc;
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struct arm_smccc_res result;
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uint32_t addr;
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sc = device_get_softc(dev);
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if ((bus < sc->base.bus_start) || (bus > sc->base.bus_end))
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return (~0U);
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if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
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(reg > PCIE_REGMAX))
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return (~0U);
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addr = (sc->base.ecam << 16) | (bus << 8) | (slot << 3) | (func << 0);
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if (psci_callfn(SMCCC_PCI_READ, addr, reg, bytes, 0, 0, 0, 0,
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&result) < 0) {
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return (~0U);
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}
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return (result.a1);
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}
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static void
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pci_host_acpi_smccc_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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struct generic_pcie_acpi_softc *sc;
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struct arm_smccc_res result;
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uint32_t addr;
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sc = device_get_softc(dev);
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if ((bus < sc->base.bus_start) || (bus > sc->base.bus_end))
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return;
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if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
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(reg > PCIE_REGMAX))
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return;
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addr = (sc->base.ecam << 16) | (bus << 8) | (slot << 3) | (func << 0);
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psci_callfn(SMCCC_PCI_WRITE, addr, reg, bytes, val, 0, 0, 0, &result);
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}
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static device_method_t generic_pcie_acpi_smccc_methods[] = {
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DEVMETHOD(device_probe, pci_host_acpi_smccc_probe),
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DEVMETHOD(device_attach, pci_host_acpi_smccc_attach),
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/* pcib interface */
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DEVMETHOD(pcib_read_config, pci_host_acpi_smccc_read_config),
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DEVMETHOD(pcib_write_config, pci_host_acpi_smccc_write_config),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, generic_pcie_acpi_smccc_driver,
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generic_pcie_acpi_smccc_methods,
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sizeof(struct generic_pcie_acpi_softc), generic_pcie_acpi_driver);
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DRIVER_MODULE(pcib_smccc, acpi, generic_pcie_acpi_smccc_driver, 0, 0);
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