Add support for MSI-X interrupts in the virtio network device and make that
the default. The current behavior of advertising a single MSI vector can be requested by setting the environment variable "BHYVE_USE_MSI" to "true". The use of MSI is not compliant with the virtio specification and will be eventually phased out. Submitted by: Gopakumar T Obtained from: NetApp
This commit is contained in:
parent
8faceb3292
commit
c9b4e98754
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=246109
@ -166,6 +166,94 @@ pci_parse_slot(char *opt, int legacy)
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}
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}
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static int
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pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
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{
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if (offset < pi->pi_msix.pba_offset)
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return (0);
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if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
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return (0);
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}
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return (1);
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}
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int
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pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
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uint64_t value)
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{
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int msix_entry_offset;
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int tab_index;
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char *dest;
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/* support only 4 or 8 byte writes */
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if (size != 4 && size != 8)
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return (-1);
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/*
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* Return if table index is beyond what device supports
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*/
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tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (tab_index >= pi->pi_msix.table_count)
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return (-1);
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msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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/* support only aligned writes */
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if ((msix_entry_offset % size) != 0)
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return (-1);
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dest = (char *)(pi->pi_msix.table + tab_index);
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dest += msix_entry_offset;
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if (size == 4)
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*((uint32_t *)dest) = value;
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else
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*((uint64_t *)dest) = value;
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return (0);
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}
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uint64_t
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pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
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{
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char *dest;
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int msix_entry_offset;
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int tab_index;
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uint64_t retval = ~0;
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/* support only 4 or 8 byte reads */
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if (size != 4 && size != 8)
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return (retval);
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msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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/* support only aligned reads */
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if ((msix_entry_offset % size) != 0) {
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return (retval);
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}
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tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (tab_index < pi->pi_msix.table_count) {
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/* valid MSI-X Table access */
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dest = (char *)(pi->pi_msix.table + tab_index);
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dest += msix_entry_offset;
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if (size == 4)
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retval = *((uint32_t *)dest);
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else
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retval = *((uint64_t *)dest);
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} else if (pci_valid_pba_offset(pi, offset)) {
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/* return 0 for PBA access */
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retval = 0;
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}
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return (retval);
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}
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static int
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pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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@ -178,8 +266,7 @@ pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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for (i = 0; i <= PCI_BARMAX; i++) {
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if (pdi->pi_bar[i].type == PCIBAR_IO &&
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port >= pdi->pi_bar[i].addr &&
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port + bytes <=
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pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
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port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
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offset = port - pdi->pi_bar[i].addr;
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if (in)
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*eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
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@ -484,13 +571,95 @@ pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
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return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
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}
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static void
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pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
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uint32_t msix_tab_size, int nextptr)
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{
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CTASSERT(sizeof(struct msixcap) == 12);
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assert(msix_tab_size % 4096 == 0);
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bzero(msixcap, sizeof(struct msixcap));
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msixcap->capid = PCIY_MSIX;
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msixcap->nextptr = nextptr;
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/*
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* Message Control Register, all fields set to
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* zero except for the Table Size.
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* Note: Table size N is encoded as N-1
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*/
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msixcap->msgctrl = msgnum - 1;
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/*
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* MSI-X BAR setup:
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* - MSI-X table start at offset 0
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* - PBA table starts at a 4K aligned offset after the MSI-X table
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*/
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msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
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msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
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}
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static void
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pci_msix_table_init(struct pci_devinst *pi, int table_entries)
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{
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int i, table_size;
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assert(table_entries > 0);
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assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
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table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
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pi->pi_msix.table = malloc(table_size);
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bzero(pi->pi_msix.table, table_size);
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/* set mask bit of vector control register */
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for (i = 0; i < table_entries; i++)
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pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
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}
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int
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pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
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{
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uint16_t pba_index;
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uint32_t tab_size;
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struct msixcap msixcap;
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assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
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assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
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tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
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/* Align table size to nearest 4K */
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tab_size = roundup2(tab_size, 4096);
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pi->pi_msix.table_bar = barnum;
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pi->pi_msix.pba_bar = barnum;
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pi->pi_msix.table_offset = 0;
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pi->pi_msix.table_count = msgnum;
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pi->pi_msix.pba_offset = tab_size;
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/* calculate the MMIO size required for MSI-X PBA */
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pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8);
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pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE;
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pci_msix_table_init(pi, msgnum);
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pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0);
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/* allocate memory for MSI-X Table and PBA */
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pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
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tab_size + pi->pi_msix.pba_size);
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return (pci_emul_add_capability(pi, (u_char *)&msixcap,
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sizeof(msixcap)));
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}
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void
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msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val)
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{
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uint16_t msgctrl, rwmask;
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int off, table_bar;
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off = offset - capoff;
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table_bar = pi->pi_msix.table_bar;
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/* Message Control Register */
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@ -502,6 +671,7 @@ msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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val = msgctrl;
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pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
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pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
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}
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CFGWRITE(pi, offset, val, bytes);
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@ -589,6 +759,9 @@ pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
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case PCIY_MSI:
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msicap_cfgwrite(pi, capoff, offset, bytes, val);
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break;
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case PCIY_MSIX:
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msixcap_cfgwrite(pi, capoff, offset, bytes, val);
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break;
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default:
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break;
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}
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@ -668,6 +841,35 @@ pci_msi_msgnum(struct pci_devinst *pi)
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return (0);
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}
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int
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pci_msix_enabled(struct pci_devinst *pi)
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{
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return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
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}
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void
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pci_generate_msix(struct pci_devinst *pi, int index)
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{
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struct msix_table_entry *mte;
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if (!pci_msix_enabled(pi))
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return;
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if (pi->pi_msix.function_mask)
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return;
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if (index >= pi->pi_msix.table_count)
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return;
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mte = &pi->pi_msix.table[index];
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if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
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/* XXX Set PBA bit if interrupt is disabled */
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vm_lapic_irq(pi->pi_vmctx,
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(mte->addr >> 12) & 0xff, mte->msg_data & 0xff);
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}
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}
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void
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pci_generate_msi(struct pci_devinst *pi, int msg)
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{
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@ -96,6 +96,8 @@ struct msix_table_entry {
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* for the size that should be emulated.
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*/
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#define MSIX_TABLE_ENTRY_SIZE 16
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#define MAX_MSIX_TABLE_ENTRIES 2048
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#define PBA_TABLE_ENTRY_SIZE 8
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struct pci_devinst {
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struct pci_devemu *pi_d;
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@ -120,6 +122,8 @@ struct pci_devinst {
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size_t table_offset;
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int table_count;
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size_t pba_offset;
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size_t pba_size;
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int function_mask;
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struct msix_table_entry *table; /* allocated at runtime */
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} pi_msix;
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@ -168,6 +172,10 @@ int pci_msix_enabled(struct pci_devinst *pi);
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int pci_msi_msgnum(struct pci_devinst *pi);
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void pci_parse_slot(char *opt, int legacy);
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void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
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int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
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int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
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uint64_t value);
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uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
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static __inline void
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pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
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@ -59,17 +59,17 @@ __FBSDID("$FreeBSD$");
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/*
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* PCI config-space register offsets
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*/
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#define VTNET_R_CFG0 20
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#define VTNET_R_CFG1 21
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#define VTNET_R_CFG2 22
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#define VTNET_R_CFG3 23
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#define VTNET_R_CFG4 24
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#define VTNET_R_CFG5 25
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#define VTNET_R_CFG6 26
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#define VTNET_R_CFG7 27
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#define VTNET_R_MAX 27
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#define VTNET_R_CFG0 24
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#define VTNET_R_CFG1 25
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#define VTNET_R_CFG2 26
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#define VTNET_R_CFG3 27
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#define VTNET_R_CFG4 28
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#define VTNET_R_CFG5 29
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#define VTNET_R_CFG6 30
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#define VTNET_R_CFG7 31
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#define VTNET_R_MAX 31
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#define VTNET_REGSZ VTNET_R_MAX+1
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#define VTNET_REGSZ VTNET_R_MAX+1
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/*
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* Host capabilities
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@ -88,6 +88,8 @@ __FBSDID("$FreeBSD$");
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#define VTNET_MAXQ 3
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static int use_msix = 1;
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struct vring_hqueue {
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/* Internal state */
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uint16_t hq_size;
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@ -144,8 +146,23 @@ struct pci_vtnet_softc {
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uint64_t vsc_pfn[VTNET_MAXQ];
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struct vring_hqueue vsc_hq[VTNET_MAXQ];
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uint16_t vsc_msix_table_idx[VTNET_MAXQ];
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};
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/*
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* Return the size of IO BAR that maps virtio header and device specific
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* region. The size would vary depending on whether MSI-X is enabled or
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* not.
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*/
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static uint64_t
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pci_vtnet_iosize(struct pci_devinst *pi)
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{
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if (pci_msix_enabled(pi))
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return (VTNET_REGSZ);
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else
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return (VTNET_REGSZ - (VTCFG_R_CFG1 - VTCFG_R_MSIX));
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}
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/*
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* Return the number of available descriptors in the vring taking care
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* of the 16-bit index wraparound.
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@ -344,8 +361,13 @@ pci_vtnet_tap_rx(struct pci_vtnet_softc *sc)
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hq->hq_cur_aidx = aidx;
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if ((*hq->hq_avail_flags & VRING_AVAIL_F_NO_INTERRUPT) == 0) {
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sc->vsc_isr |= 1;
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pci_generate_msi(sc->vsc_pi, 0);
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if (use_msix) {
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pci_generate_msix(sc->vsc_pi,
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sc->vsc_msix_table_idx[VTNET_RXQ]);
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} else {
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sc->vsc_isr |= 1;
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pci_generate_msi(sc->vsc_pi, 0);
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}
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}
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}
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@ -438,8 +460,13 @@ pci_vtnet_proctx(struct pci_vtnet_softc *sc, struct vring_hqueue *hq)
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* Generate an interrupt if able
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*/
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if ((*hq->hq_avail_flags & VRING_AVAIL_F_NO_INTERRUPT) == 0) {
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sc->vsc_isr |= 1;
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pci_generate_msi(sc->vsc_pi, 0);
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if (use_msix) {
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pci_generate_msix(sc->vsc_pi,
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sc->vsc_msix_table_idx[VTNET_TXQ]);
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} else {
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sc->vsc_isr |= 1;
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pci_generate_msi(sc->vsc_pi, 0);
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}
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}
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}
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@ -512,6 +539,7 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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unsigned char digest[16];
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char nstr[80];
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struct pci_vtnet_softc *sc;
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const char *env_msi;
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/*
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* Access to guest memory is required. Fail if
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@ -527,6 +555,14 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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sc->vsc_pi = pi;
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pthread_mutex_init(&sc->vsc_mtx, NULL);
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/*
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* Use MSI if set by user
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*/
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if ((env_msi = getenv("BHYVE_USE_MSI")) != NULL) {
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if (strcasecmp(env_msi, "yes") == 0)
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use_msix = 0;
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}
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/*
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* Attempt to open the tap device
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@ -594,7 +630,24 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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pci_set_cfgdata16(pi, PCIR_VENDOR, VIRTIO_VENDOR);
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pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
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pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_TYPE_NET);
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pci_emul_add_msicap(pi, 1);
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if (use_msix) {
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/* MSI-X support */
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int i;
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for (i = 0; i < VTNET_MAXQ; i++)
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sc->vsc_msix_table_idx[i] = VIRTIO_MSI_NO_VECTOR;
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/*
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* BAR 1 used to map MSI-X table and PBA
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*/
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if (pci_emul_add_msixcap(pi, VTNET_MAXQ, 1))
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return (1);
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} else {
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/* MSI support */
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pci_emul_add_msicap(pi, 1);
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}
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pci_emul_alloc_bar(pi, 0, PCIBAR_IO, VTNET_REGSZ);
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return (0);
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@ -609,6 +662,21 @@ static void (*pci_vtnet_qnotify[VTNET_MAXQ])(struct pci_vtnet_softc *) = {
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pci_vtnet_ping_ctlq
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};
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static uint64_t
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vtnet_adjust_offset(struct pci_devinst *pi, uint64_t offset)
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{
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/*
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* Device specific offsets used by guest would change based on
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* whether MSI-X capability is enabled or not
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*/
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if (!pci_msix_enabled(pi)) {
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if (offset >= VTCFG_R_MSIX)
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return (offset + (VTCFG_R_CFG1 - VTCFG_R_MSIX));
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}
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return (offset);
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}
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static void
|
||||
pci_vtnet_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size, uint64_t value)
|
||||
@ -616,9 +684,17 @@ pci_vtnet_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
struct pci_vtnet_softc *sc = pi->pi_arg;
|
||||
void *ptr;
|
||||
|
||||
if (use_msix) {
|
||||
if (baridx == pi->pi_msix.table_bar ||
|
||||
baridx == pi->pi_msix.pba_bar) {
|
||||
pci_emul_msix_twrite(pi, offset, size, value);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
assert(baridx == 0);
|
||||
|
||||
if (offset + size > VTNET_REGSZ) {
|
||||
if (offset + size > pci_vtnet_iosize(pi)) {
|
||||
DPRINTF(("vtnet_write: 2big, offset %ld size %d\n",
|
||||
offset, size));
|
||||
return;
|
||||
@ -626,6 +702,8 @@ pci_vtnet_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
|
||||
pthread_mutex_lock(&sc->vsc_mtx);
|
||||
|
||||
offset = vtnet_adjust_offset(pi, offset);
|
||||
|
||||
switch (offset) {
|
||||
case VTCFG_R_GUESTCAP:
|
||||
assert(size == 4);
|
||||
@ -649,6 +727,15 @@ pci_vtnet_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
assert(size == 1);
|
||||
pci_vtnet_update_status(sc, value);
|
||||
break;
|
||||
case VTCFG_R_CFGVEC:
|
||||
assert(size == 2);
|
||||
sc->vsc_msix_table_idx[VTNET_CTLQ] = value;
|
||||
break;
|
||||
case VTCFG_R_QVEC:
|
||||
assert(size == 2);
|
||||
assert(sc->vsc_curq != VTNET_CTLQ);
|
||||
sc->vsc_msix_table_idx[sc->vsc_curq] = value;
|
||||
break;
|
||||
case VTNET_R_CFG0:
|
||||
case VTNET_R_CFG1:
|
||||
case VTNET_R_CFG2:
|
||||
@ -693,9 +780,16 @@ pci_vtnet_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
void *ptr;
|
||||
uint64_t value;
|
||||
|
||||
if (use_msix) {
|
||||
if (baridx == pi->pi_msix.table_bar ||
|
||||
baridx == pi->pi_msix.pba_bar) {
|
||||
return (pci_emul_msix_tread(pi, offset, size));
|
||||
}
|
||||
}
|
||||
|
||||
assert(baridx == 0);
|
||||
|
||||
if (offset + size > VTNET_REGSZ) {
|
||||
if (offset + size > pci_vtnet_iosize(pi)) {
|
||||
DPRINTF(("vtnet_read: 2big, offset %ld size %d\n",
|
||||
offset, size));
|
||||
return (0);
|
||||
@ -703,6 +797,8 @@ pci_vtnet_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
|
||||
pthread_mutex_lock(&sc->vsc_mtx);
|
||||
|
||||
offset = vtnet_adjust_offset(pi, offset);
|
||||
|
||||
switch (offset) {
|
||||
case VTCFG_R_HOSTCAP:
|
||||
assert(size == 4);
|
||||
@ -737,21 +833,30 @@ pci_vtnet_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
value = sc->vsc_isr;
|
||||
sc->vsc_isr = 0; /* a read clears this flag */
|
||||
break;
|
||||
case VTCFG_R_CFGVEC:
|
||||
assert(size == 2);
|
||||
value = sc->vsc_msix_table_idx[VTNET_CTLQ];
|
||||
break;
|
||||
case VTCFG_R_QVEC:
|
||||
assert(size == 2);
|
||||
assert(sc->vsc_curq != VTNET_CTLQ);
|
||||
value = sc->vsc_msix_table_idx[sc->vsc_curq];
|
||||
break;
|
||||
case VTNET_R_CFG0:
|
||||
case VTNET_R_CFG1:
|
||||
case VTNET_R_CFG2:
|
||||
case VTNET_R_CFG3:
|
||||
case VTNET_R_CFG4:
|
||||
case VTNET_R_CFG5:
|
||||
assert((size + offset) <= (VTNET_R_CFG5 + 1));
|
||||
ptr = &sc->vsc_macaddr[offset - VTNET_R_CFG0];
|
||||
if (size == 1) {
|
||||
value = *(uint8_t *) ptr;
|
||||
} else if (size == 2) {
|
||||
value = *(uint16_t *) ptr;
|
||||
} else {
|
||||
value = *(uint32_t *) ptr;
|
||||
}
|
||||
assert((size + offset) <= (VTNET_R_CFG5 + 1));
|
||||
ptr = &sc->vsc_macaddr[offset - VTNET_R_CFG0];
|
||||
if (size == 1) {
|
||||
value = *(uint8_t *) ptr;
|
||||
} else if (size == 2) {
|
||||
value = *(uint16_t *) ptr;
|
||||
} else {
|
||||
value = *(uint32_t *) ptr;
|
||||
}
|
||||
break;
|
||||
case VTNET_R_CFG6:
|
||||
assert(size != 4);
|
||||
|
@ -36,6 +36,7 @@
|
||||
#define VRING_DESC_F_INDIRECT (1 << 2)
|
||||
|
||||
#define VRING_AVAIL_F_NO_INTERRUPT 1
|
||||
#define VIRTIO_MSI_NO_VECTOR 0xFFFF
|
||||
|
||||
struct virtio_desc {
|
||||
uint64_t vd_addr;
|
||||
@ -78,6 +79,8 @@ struct virtio_used {
|
||||
#define VTCFG_R_QNOTIFY 16
|
||||
#define VTCFG_R_STATUS 18
|
||||
#define VTCFG_R_ISR 19
|
||||
#define VTCFG_R_CFGVEC 20
|
||||
#define VTCFG_R_QVEC 22
|
||||
#define VTCFG_R_CFG0 20 /* No MSI-X */
|
||||
#define VTCFG_R_CFG1 24 /* With MSI-X */
|
||||
#define VTCFG_R_MSIX 20
|
||||
|
Loading…
Reference in New Issue
Block a user