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Move an else case that was missed in r263676

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This commit is contained in:
Andrew Turner 2014-03-24 08:24:32 +00:00
parent 52c52d38d5
commit c9ccb0bb6b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=263679
1 changed files with 25 additions and 25 deletions
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50
sys/arm/include/pmap.h
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@ -421,6 +421,31 @@ extern int pmap_needs_pte_sync;
#define ARM_L2S_NRML_IWT_OWT (L2_C)
#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
#else
#define ARM_L1S_STRONG_ORD (0)
#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
#define ARM_L1S_DEVICE_SHARE (L1_S_B)
#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
#define ARM_L2L_STRONG_ORD (0)
#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
#define ARM_L2L_DEVICE_SHARE (L2_B)
#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
#define ARM_L2S_STRONG_ORD (0)
#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
#define ARM_L2S_DEVICE_SHARE (L2_B)
#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
#endif /* SMP */
#elif ARM_NMMUS > 1
/* More than one MMU class configured; use variables. */
@ -462,31 +487,6 @@ extern int pmap_needs_pte_sync;
#define L1_C_PROTO L1_C_PROTO_xscale
#define L2_S_PROTO L2_S_PROTO_xscale
#else
#define ARM_L1S_STRONG_ORD (0)
#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
#define ARM_L1S_DEVICE_SHARE (L1_S_B)
#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
#define ARM_L2L_STRONG_ORD (0)
#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
#define ARM_L2L_DEVICE_SHARE (L2_B)
#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
#define ARM_L2S_STRONG_ORD (0)
#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
#define ARM_L2S_DEVICE_SHARE (L2_B)
#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
#endif /* SMP */
#endif /* ARM_NMMUS > 1 */
#if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A