Remove unused functions and variables in cpufunc.[ch].
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a527975133
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cad703dc09
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=368635
@ -62,24 +62,10 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpufunc.h>
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/* PRIMARY CACHE VARIABLES */
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int arm_picache_size;
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int arm_picache_line_size;
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int arm_picache_ways;
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int arm_pdcache_size; /* and unified */
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int arm_pdcache_line_size;
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int arm_pdcache_ways;
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int arm_pcache_type;
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int arm_pcache_unified;
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int arm_dcache_align;
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int arm_dcache_align_mask;
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u_int arm_cache_level;
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u_int arm_cache_type[14];
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u_int arm_cache_loc;
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#ifdef CPU_MV_PJ4B
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static void pj4bv7_setup(void);
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#endif
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@ -155,16 +141,10 @@ u_int cputype;
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static void get_cachetype_cp15(void);
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/* Additional cache information local to this file. Log2 of some of the
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above numbers. */
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static int arm_dcache_l2_nsets;
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static int arm_dcache_l2_assoc;
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static int arm_dcache_l2_linesize;
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static void
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get_cachetype_cp15(void)
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{
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u_int ctype, isize, dsize, cpuid;
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u_int ctype, dsize, cpuid;
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u_int clevel, csize, i, sel;
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u_int multiplier;
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u_char type;
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@ -184,8 +164,6 @@ get_cachetype_cp15(void)
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if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
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__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
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: "=r" (clevel));
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arm_cache_level = clevel;
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arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level);
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i = 0;
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while ((type = (clevel & 0x7)) && i < 7) {
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if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
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@ -195,7 +173,6 @@ get_cachetype_cp15(void)
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: : "r" (sel));
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__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
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: "=r" (csize));
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arm_cache_type[sel] = csize;
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arm_dcache_align = 1 <<
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(CPUV7_CT_xSIZE_LEN(csize) + 4);
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arm_dcache_align_mask = arm_dcache_align - 1;
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@ -206,57 +183,22 @@ get_cachetype_cp15(void)
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: : "r" (sel));
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__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
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: "=r" (csize));
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arm_cache_type[sel] = csize;
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}
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i++;
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clevel >>= 3;
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}
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} else {
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if ((ctype & CPU_CT_S) == 0)
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arm_pcache_unified = 1;
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/*
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* If you want to know how this code works, go read the ARM ARM.
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*/
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arm_pcache_type = CPU_CT_CTYPE(ctype);
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if (arm_pcache_unified == 0) {
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isize = CPU_CT_ISIZE(ctype);
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multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
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if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
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if (isize & CPU_CT_xSIZE_M)
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arm_picache_line_size = 0; /* not present */
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else
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arm_picache_ways = 1;
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} else {
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arm_picache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(isize) - 1);
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}
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arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
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}
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dsize = CPU_CT_DSIZE(ctype);
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multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
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arm_dcache_align = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
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if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
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if (dsize & CPU_CT_xSIZE_M)
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arm_pdcache_line_size = 0; /* not present */
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else
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arm_pdcache_ways = 1;
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} else {
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arm_pdcache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(dsize) - 1);
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arm_dcache_align = 0; /* not present */
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}
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arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
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arm_dcache_align = arm_pdcache_line_size;
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arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2;
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arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
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arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
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CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
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out:
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arm_dcache_align_mask = arm_dcache_align - 1;
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@ -52,21 +52,6 @@ ENTRY(cpufunc_nullop)
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RET
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END(cpufunc_nullop)
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/*
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* Generic functions to write the internal coprocessor registers
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*
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* Currently these registers are
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* c1 - CPU Control
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* c3 - Domain Access Control
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*
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* All other registers are CPU architecture specific
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*/
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ENTRY(cpu_domains)
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mcr p15, 0, r0, c3, c0, 0
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RET
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END(cpu_domains)
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/*
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* Generic functions to read/modify/write the internal coprocessor registers
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*
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@ -90,35 +75,3 @@ ENTRY(cpufunc_control)
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RET
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END(cpufunc_control)
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/*
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* other potentially useful software functions are:
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* clean D cache entry and flush I cache entry
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* for the moment use cache_purgeID_E
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*/
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/* Random odd functions */
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/* Allocate and lock a cacheline for the specified address. */
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT() \
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mrc p15, 0, r2, c2, c0, 0; \
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mov r2, r2; \
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CPWAIT_BRANCH
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ENTRY(arm_lock_cache_line)
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mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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mov r1, #1
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mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
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CPWAIT()
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mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
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mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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mov r1, #0
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str r1, [r0]
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mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
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CPWAIT()
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RET
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END(arm_lock_cache_line)
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@ -87,11 +87,9 @@ extern u_int cputype;
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int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop (void);
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u_int cpufunc_control (u_int clear, u_int bic);
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void cpu_domains (u_int domains);
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#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
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@ -182,23 +180,9 @@ void cpu_reset (void) __attribute__((__noreturn__));
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*/
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/* PRIMARY CACHE VARIABLES */
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extern int arm_picache_size;
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extern int arm_picache_line_size;
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extern int arm_picache_ways;
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extern int arm_pdcache_size; /* and unified */
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extern int arm_pdcache_line_size;
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extern int arm_pdcache_ways;
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extern int arm_pcache_type;
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extern int arm_pcache_unified;
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extern int arm_dcache_align;
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extern int arm_dcache_align_mask;
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extern u_int arm_cache_level;
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extern u_int arm_cache_loc;
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extern u_int arm_cache_type[14];
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#define HAVE_INLINE_FFS
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@ -16,7 +16,6 @@ extern vm_offset_t abtstack;
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/* misc prototypes used by the many arm machdeps */
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struct trapframe;
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void arm_lock_cache_line(vm_offset_t);
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void init_proc0(vm_offset_t kstack);
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void halt(void);
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void abort_handler(struct trapframe *, int );
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