Setup decoding windows for ARMADA38X
It is necesarry to open memory windows on internal bus for AHCI driver to work correctly. Submitted by: Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: zbb Differential revision: https://reviews.freebsd.org/D9220
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ccd5b1b023
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=312747
@ -98,6 +98,7 @@ static void decode_win_usb_setup(u_long);
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static void decode_win_usb3_setup(u_long);
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static void decode_win_eth_setup(u_long);
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static void decode_win_sata_setup(u_long);
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static void decode_win_ahci_setup(u_long);
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static void decode_win_idma_setup(u_long);
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static void decode_win_xor_setup(u_long);
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@ -107,6 +108,7 @@ static void decode_win_usb3_dump(u_long);
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static void decode_win_eth_dump(u_long base);
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static void decode_win_idma_dump(u_long base);
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static void decode_win_xor_dump(u_long base);
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static void decode_win_sata_dump(u_long base);
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static int fdt_get_ranges(const char *, void *, int, int *, int *);
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#ifdef SOC_MV_ARMADA38X
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@ -139,6 +141,7 @@ static struct soc_node_spec soc_nodes[] = {
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{ "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
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{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
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{ "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
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{ "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_sata_dump },
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{ "mrvl,sata", &decode_win_sata_setup, NULL },
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{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
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{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
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@ -660,6 +663,11 @@ WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
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WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
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WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
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WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
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#if defined(SOC_MV_ARMADA38X)
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WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE);
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WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE);
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#endif
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#ifndef SOC_MV_DOVE
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WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
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WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
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@ -1999,6 +2007,55 @@ decode_win_sata_setup(u_long base)
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}
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}
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static void
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decode_win_ahci_setup(u_long base)
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{
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uint32_t br, cr, sz;
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int i, j;
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for (i = 0; i < MV_WIN_SATA_MAX; i++) {
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win_sata_cr_write(base, i, 0);
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win_sata_br_write(base, i, 0);
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win_sata_sz_write(base, i, 0);
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}
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for (i = 0; i < MV_WIN_DDR_MAX; i++) {
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if (ddr_is_active(i)) {
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cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
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(ddr_target(i) << IO_WIN_TGT_SHIFT) |
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IO_WIN_ENA_MASK;
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br = ddr_base(i);
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sz = (ddr_size(i) - 1) &
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(IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);
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/* Use first available SATA window */
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for (j = 0; j < MV_WIN_SATA_MAX; j++) {
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if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK)
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continue;
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/* BASE is set to DRAM base (0x00000000) */
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win_sata_br_write(base, j, br);
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/* CTRL targets DRAM ctrl with 0x0E or 0x0D */
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win_sata_cr_write(base, j, cr);
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/* SIZE is set to 16MB - max value */
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win_sata_sz_write(base, j, sz);
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break;
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}
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}
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}
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}
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static void
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decode_win_sata_dump(u_long base)
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{
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int i;
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for (i = 0; i < MV_WIN_SATA_MAX; i++)
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printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,
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win_sata_cr_read(base, i), win_sata_br_read(base, i),
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win_sata_sz_read(base,i));
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}
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static int
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decode_win_sata_valid(void)
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{
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@ -324,9 +324,16 @@
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#define MV_PCIE_CONTROL (0x1a00)
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#define MV_PCIE_ROOT_CMPLX (1 << 1)
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#if defined(SOC_MV_ARMADA38X)
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#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x60)
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#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x64)
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#define MV_WIN_SATA_SIZE(n) (0x10 * (n) + 0x68)
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#define MV_WIN_SATA_MAX 4
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#else
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#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
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#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
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#define MV_WIN_SATA_MAX 4
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#endif
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#if defined(SOC_MV_ARMADA38X)
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#define MV_BOOTROM_MEM_ADDR 0xFFF00000
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