bhyve: implement NVMe deallocate command
This adds support for the Dataset Management (DSM) command to the NVMe emulation in general, and more specifically, for the deallocate attribute (a.k.a. trim in the ATA protocol). If the backing storage for the namespace supports delete (i.e. deallocate), setting the deallocate attribute in a DSM will trim/delete the requested LBA ranges in the underlying storage. Reviewed by: jhb, araujo, imp Approved by: jhb (maintainer) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D21839
This commit is contained in:
Chuck Tuffli
parent
d31d525ef5
commit
cd65e08916
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=359364
@ -180,6 +180,7 @@ struct pci_nvme_blockstore {
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uint32_t sectsz;
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uint32_t sectsz_bits;
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uint64_t eui64;
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uint32_t deallocate:1;
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};
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struct pci_nvme_ioreq {
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@ -209,6 +210,15 @@ struct pci_nvme_ioreq {
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struct iovec iovpadding[NVME_MAX_BLOCKIOVS-BLOCKIF_IOV_MAX];
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};
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enum nvme_dsm_type {
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/* Dataset Management bit in ONCS reflects backing storage capability */
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NVME_DATASET_MANAGEMENT_AUTO,
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/* Unconditionally set Dataset Management bit in ONCS */
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NVME_DATASET_MANAGEMENT_ENABLE,
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/* Unconditionally clear Dataset Management bit in ONCS */
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NVME_DATASET_MANAGEMENT_DISABLE,
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};
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struct pci_nvme_softc {
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struct pci_devinst *nsc_pi;
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@ -246,6 +256,8 @@ struct pci_nvme_softc {
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uint32_t intr_coales_aggr_time; /* 0x08: uS to delay intr */
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uint32_t intr_coales_aggr_thresh; /* 0x08: compl-Q entries */
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uint32_t async_ev_config; /* 0x0B: async event config */
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enum nvme_dsm_type dataset_management;
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};
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@ -285,6 +297,9 @@ static void pci_nvme_io_partial(struct blockif_req *br, int err);
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((NVME_STATUS_SCT_MASK << NVME_STATUS_SCT_SHIFT) |\
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(NVME_STATUS_SC_MASK << NVME_STATUS_SC_SHIFT))
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#define NVME_ONCS_DSM (NVME_CTRLR_DATA_ONCS_DSM_MASK << \
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NVME_CTRLR_DATA_ONCS_DSM_SHIFT)
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static __inline void
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cpywithpad(char *dst, size_t dst_size, const char *src, char pad)
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{
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@ -363,6 +378,19 @@ pci_nvme_init_ctrldata(struct pci_nvme_softc *sc)
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(4 << NVME_CTRLR_DATA_CQES_MIN_SHIFT);
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cd->nn = 1; /* number of namespaces */
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cd->oncs = 0;
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switch (sc->dataset_management) {
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case NVME_DATASET_MANAGEMENT_AUTO:
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if (sc->nvstore.deallocate)
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cd->oncs |= NVME_ONCS_DSM;
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break;
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case NVME_DATASET_MANAGEMENT_ENABLE:
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cd->oncs |= NVME_ONCS_DSM;
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break;
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default:
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break;
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}
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cd->fna = 0x03;
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cd->power_state[0].mp = 10;
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@ -429,6 +457,9 @@ pci_nvme_init_nsdata(struct pci_nvme_softc *sc,
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nd->ncap = nd->nsze;
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nd->nuse = nd->nsze;
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if (nvstore->type == NVME_STOR_BLOCKIF)
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nvstore->deallocate = blockif_candelete(nvstore->ctx);
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nd->nlbaf = 0; /* NLBAF is a 0's based value (i.e. 1 LBA Format) */
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nd->flbas = 0;
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@ -1340,7 +1371,7 @@ pci_nvme_io_done(struct blockif_req *br, int err)
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uint16_t code, status;
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DPRINTF(("%s error %d %s", __func__, err, strerror(err)));
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/* TODO return correct error */
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code = err ? NVME_SC_DATA_TRANSFER_ERROR : NVME_SC_SUCCESS;
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pci_nvme_status_genc(&status, code);
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@ -1359,6 +1390,127 @@ pci_nvme_io_partial(struct blockif_req *br, int err)
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pthread_cond_signal(&req->cv);
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}
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static void
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pci_nvme_dealloc_sm(struct blockif_req *br, int err)
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{
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struct pci_nvme_ioreq *req = br->br_param;
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struct pci_nvme_softc *sc = req->sc;
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bool done = true;
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uint16_t status;
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if (err) {
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pci_nvme_status_genc(&status, NVME_SC_INTERNAL_DEVICE_ERROR);
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} else if ((req->prev_gpaddr + 1) == (req->prev_size)) {
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pci_nvme_status_genc(&status, NVME_SC_SUCCESS);
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} else {
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struct iovec *iov = req->io_req.br_iov;
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req->prev_gpaddr++;
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iov += req->prev_gpaddr;
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/* The iov_* values already include the sector size */
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req->io_req.br_offset = (off_t)iov->iov_base;
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req->io_req.br_resid = iov->iov_len;
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if (blockif_delete(sc->nvstore.ctx, &req->io_req)) {
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pci_nvme_status_genc(&status,
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NVME_SC_INTERNAL_DEVICE_ERROR);
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} else
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done = false;
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}
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if (done) {
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pci_nvme_set_completion(sc, req->nvme_sq, req->sqid,
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req->cid, 0, status, 0);
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pci_nvme_release_ioreq(sc, req);
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}
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}
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static int
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nvme_opc_dataset_mgmt(struct pci_nvme_softc *sc,
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struct nvme_command *cmd,
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struct pci_nvme_blockstore *nvstore,
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struct pci_nvme_ioreq *req,
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uint16_t *status)
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{
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int err = -1;
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if ((sc->ctrldata.oncs & NVME_ONCS_DSM) == 0) {
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pci_nvme_status_genc(status, NVME_SC_INVALID_OPCODE);
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goto out;
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}
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if (cmd->cdw11 & NVME_DSM_ATTR_DEALLOCATE) {
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struct nvme_dsm_range *range;
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uint32_t nr, r;
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int sectsz = sc->nvstore.sectsz;
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/*
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* DSM calls are advisory only, and compliant controllers
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* may choose to take no actions (i.e. return Success).
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*/
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if (!nvstore->deallocate) {
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pci_nvme_status_genc(status, NVME_SC_SUCCESS);
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goto out;
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}
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if (req == NULL) {
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pci_nvme_status_genc(status, NVME_SC_INTERNAL_DEVICE_ERROR);
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goto out;
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}
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/* copy locally because a range entry could straddle PRPs */
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range = calloc(1, NVME_MAX_DSM_TRIM);
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if (range == NULL) {
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pci_nvme_status_genc(status, NVME_SC_INTERNAL_DEVICE_ERROR);
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goto out;
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}
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nvme_prp_memcpy(sc->nsc_pi->pi_vmctx, cmd->prp1, cmd->prp2,
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(uint8_t *)range, NVME_MAX_DSM_TRIM, NVME_COPY_FROM_PRP);
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req->opc = cmd->opc;
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req->cid = cmd->cid;
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req->nsid = cmd->nsid;
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/*
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* If the request is for more than a single range, store
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* the ranges in the br_iov. Optimize for the common case
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* of a single range.
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*
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* Note that NVMe Number of Ranges is a zero based value
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*/
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nr = cmd->cdw10 & 0xff;
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req->io_req.br_iovcnt = 0;
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req->io_req.br_offset = range[0].starting_lba * sectsz;
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req->io_req.br_resid = range[0].length * sectsz;
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if (nr == 0) {
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req->io_req.br_callback = pci_nvme_io_done;
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} else {
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struct iovec *iov = req->io_req.br_iov;
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for (r = 0; r <= nr; r++) {
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iov[r].iov_base = (void *)(range[r].starting_lba * sectsz);
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iov[r].iov_len = range[r].length * sectsz;
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}
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req->io_req.br_callback = pci_nvme_dealloc_sm;
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/*
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* Use prev_gpaddr to track the current entry and
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* prev_size to track the number of entries
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*/
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req->prev_gpaddr = 0;
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req->prev_size = r;
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}
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err = blockif_delete(nvstore->ctx, &req->io_req);
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if (err)
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pci_nvme_status_genc(status, NVME_SC_INTERNAL_DEVICE_ERROR);
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free(range);
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}
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out:
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return (err);
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}
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static void
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pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
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@ -1411,16 +1563,27 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
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continue;
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}
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nblocks = (cmd->cdw12 & 0xFFFF) + 1;
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bytes = nblocks * sc->nvstore.sectsz;
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if (sc->nvstore.type == NVME_STOR_BLOCKIF) {
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req = pci_nvme_get_ioreq(sc);
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req->nvme_sq = sq;
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req->sqid = idx;
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}
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if (cmd->opc == NVME_OPC_DATASET_MANAGEMENT) {
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if (nvme_opc_dataset_mgmt(sc, cmd, &sc->nvstore, req,
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&status)) {
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pci_nvme_set_completion(sc, sq, idx, cmd->cid,
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0, status, 1);
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if (req)
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pci_nvme_release_ioreq(sc, req);
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}
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continue;
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}
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nblocks = (cmd->cdw12 & 0xFFFF) + 1;
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bytes = nblocks * sc->nvstore.sectsz;
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/*
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* If data starts mid-page and flows into the next page, then
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* increase page count
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@ -1869,6 +2032,7 @@ pci_nvme_parse_opts(struct pci_nvme_softc *sc, char *opts)
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sc->ioslots = NVME_IOSLOTS;
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sc->num_squeues = sc->max_queues;
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sc->num_cqueues = sc->max_queues;
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sc->dataset_management = NVME_DATASET_MANAGEMENT_AUTO;
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sectsz = 0;
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uopt = strdup(opts);
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@ -1913,6 +2077,13 @@ pci_nvme_parse_opts(struct pci_nvme_softc *sc, char *opts)
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}
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} else if (!strcmp("eui64", xopts)) {
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sc->nvstore.eui64 = htobe64(strtoull(config, NULL, 0));
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} else if (!strcmp("dsm", xopts)) {
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if (!strcmp("auto", config))
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sc->dataset_management = NVME_DATASET_MANAGEMENT_AUTO;
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else if (!strcmp("enable", config))
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sc->dataset_management = NVME_DATASET_MANAGEMENT_ENABLE;
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else if (!strcmp("disable", config))
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sc->dataset_management = NVME_DATASET_MANAGEMENT_DISABLE;
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} else if (optidx == 0) {
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snprintf(bident, sizeof(bident), "%d:%d",
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sc->nsc_pi->pi_slot, sc->nsc_pi->pi_func);
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@ -2032,8 +2203,12 @@ pci_nvme_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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sem_init(&sc->iosemlock, 0, sc->ioslots);
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pci_nvme_reset(sc);
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pci_nvme_init_ctrldata(sc);
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/*
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* Controller data depends on Namespace data so initialize Namespace
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* data first.
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*/
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pci_nvme_init_nsdata(sc, &sc->nsdata, 1, &sc->nvstore);
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pci_nvme_init_ctrldata(sc);
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pci_nvme_init_logpages(sc);
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pci_lintr_request(pi);
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