Prepare for adding psind == 1 support to armv6's pmap_enter().
Precompute the new PTE before entering the critical section. Eliminate duplication of the pmap and pv list unlock operations in pmap_enter() by implementing a single return path. Otherwise, the duplication will only increase with the upcoming support for psind == 1. Reviewed by: mmel Tested by: mmel Discussed with: kib, markj MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D16443
This commit is contained in:
Alan Cox
parent
5f9d7aafd8
commit
cd914c2fc2
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=336881
@ -3849,18 +3849,36 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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pv_entry_t pv;
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vm_paddr_t opa, pa;
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vm_page_t mpte2, om;
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boolean_t wired;
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int rv;
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va = trunc_page(va);
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mpte2 = NULL;
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wired = (flags & PMAP_ENTER_WIRED) != 0;
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KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
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KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
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("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
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va));
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KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
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va >= kmi.clean_eva,
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("%s: managed mapping within the clean submap", __func__));
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if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
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VM_OBJECT_ASSERT_LOCKED(m->object);
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KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
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("%s: flags %u has reserved bits set", __func__, flags));
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pa = VM_PAGE_TO_PHYS(m);
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npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
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if ((flags & VM_PROT_WRITE) == 0)
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npte2 |= PTE2_NM;
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if ((prot & VM_PROT_WRITE) == 0)
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npte2 |= PTE2_RO;
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KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
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("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
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if ((prot & VM_PROT_EXECUTE) == 0)
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npte2 |= PTE2_NX;
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if ((flags & PMAP_ENTER_WIRED) != 0)
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npte2 |= PTE2_W;
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if (va < VM_MAXUSER_ADDRESS)
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npte2 |= PTE2_U;
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if (pmap != kernel_pmap)
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npte2 |= PTE2_NG;
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rw_wlock(&pvh_global_lock);
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PMAP_LOCK(pmap);
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@ -3875,12 +3893,11 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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if (mpte2 == NULL) {
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KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
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("pmap_allocpte2 failed with sleep allowed"));
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sched_unpin();
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rw_wunlock(&pvh_global_lock);
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PMAP_UNLOCK(pmap);
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return (KERN_RESOURCE_SHORTAGE);
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rv = KERN_RESOURCE_SHORTAGE;
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goto out;
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}
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}
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} else
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mpte2 = NULL;
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pte1p = pmap_pte1(pmap, va);
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if (pte1_is_section(pte1_load(pte1p)))
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panic("%s: attempted on 1MB page", __func__);
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@ -3889,7 +3906,6 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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panic("%s: invalid L1 page table entry va=%#x", __func__, va);
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om = NULL;
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pa = VM_PAGE_TO_PHYS(m);
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opte2 = pte2_load(pte2p);
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opa = pte2_pa(opte2);
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/*
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@ -3902,9 +3918,9 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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* are valid mappings in them. Hence, if a user page is wired,
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* the PT2 page will be also.
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*/
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if (wired && !pte2_is_wired(opte2))
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if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
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pmap->pm_stats.wired_count++;
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else if (!wired && pte2_is_wired(opte2))
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else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
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pmap->pm_stats.wired_count--;
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/*
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@ -3953,11 +3969,10 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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* Enter on the PV list if part of our managed memory.
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*/
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if ((m->oflags & VPO_UNMANAGED) == 0) {
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KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
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("%s: managed mapping within the clean submap", __func__));
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if (pv == NULL)
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if (pv == NULL) {
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pv = get_pv_entry(pmap, FALSE);
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pv->pv_va = va;
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pv->pv_va = va;
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}
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TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
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} else if (pv != NULL)
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free_pv_entry(pmap, pv);
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@ -3965,28 +3980,17 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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/*
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* Increment counters
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*/
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if (wired)
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if (pte2_is_wired(npte2))
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pmap->pm_stats.wired_count++;
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validate:
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/*
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* Now validate mapping with desired protection/wiring.
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*/
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npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
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if (prot & VM_PROT_WRITE) {
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if (pte2_is_managed(npte2))
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vm_page_aflag_set(m, PGA_WRITEABLE);
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}
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else
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npte2 |= PTE2_RO;
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if ((prot & VM_PROT_EXECUTE) == 0)
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npte2 |= PTE2_NX;
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if (wired)
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npte2 |= PTE2_W;
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if (va < VM_MAXUSER_ADDRESS)
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npte2 |= PTE2_U;
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if (pmap != kernel_pmap)
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npte2 |= PTE2_NG;
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/*
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* If the mapping or permission bits are different, we need
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@ -4016,9 +4020,6 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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(opa != pa || (opte2 & PTE2_NX)))
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cache_icache_sync_fresh(va, pa, PAGE_SIZE);
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npte2 |= PTE2_A;
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if (flags & VM_PROT_WRITE)
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npte2 &= ~PTE2_NM;
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if (opte2 & PTE2_V) {
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/* Change mapping with break-before-make approach. */
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opte2 = pte2_load_clear(pte2p);
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@ -4063,10 +4064,13 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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vm_reserv_level_iffullpop(m) == 0)
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pmap_promote_pte1(pmap, pte1p, va);
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#endif
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rv = KERN_SUCCESS;
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out:
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sched_unpin();
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rw_wunlock(&pvh_global_lock);
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PMAP_UNLOCK(pmap);
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return (KERN_SUCCESS);
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return (rv);
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}
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/*
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