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Begin implementing correct MIPS24K sampling mode behaviour.

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* Add the interrupt bit in the configuration register
* Correctly set the counter register for the sampling overflow
  interrupt. The interrupt is asserted when bit 31 is set.
  So set the overflow value at 0x80000000 and subtract the
  programmed value as appropriate.
This commit is contained in:
Adrian Chadd 2011-10-07 06:13:38 +00:00
parent 0fe2573328
commit cdb59558b9
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=226091
1 changed files with 7 additions and 4 deletions
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11
sys/dev/hwpmc/hwpmc_mips24k.h
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@ -35,7 +35,7 @@
PMC_CAP_WRITE | PMC_CAP_INVERT | \
PMC_CAP_QUALIFIER)
#define MIPS24K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */
#define MIPS24K_PMC_USER_ENABLE 0x08 /* Count in USER mode */
#define MIPS24K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */
#define MIPS24K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */
@ -43,9 +43,12 @@
MIPS24K_PMC_SUPER_ENABLE | \
MIPS24K_PMC_KERNEL_ENABLE)
#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R))
#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
/*
* Interrupts are posted when bit 31 of the relevant
* counter is set.
*/
#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (0x80000000 - (R))
#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) ((P) - 0x80000000)
#define MIPS24K_PMC_SELECT 0x4 /* Which bit position the event starts at. */
#define MIPS24K_PMC_OFFSET 2 /* Control registers are 0, 2, 4, etc. */