arm64: Add Synopsys DWC3 driver
This add a driver for the Synopsys DWC3 driver found on multiple SoCs. It only supports host mode for now. MFC after: 1 month
This commit is contained in:
Emmanuel Vadot
parent
26b0cd3a95
commit
ce607eeb9d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=353533
@ -211,6 +211,7 @@ device ohci # OHCI USB interface
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device ehci # EHCI USB interface (USB 2.0)
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device ehci_mv # Marvell EHCI USB interface
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device xhci # XHCI USB interface (USB 3.0)
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device dwc3 # Synopsys DWC controller
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device aw_dwc3 # Allwinner DWC3 controller
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device usb # USB Bus (required)
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device ukbd # Keyboard
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@ -251,6 +251,7 @@ dev/uart/uart_cpu_arm64.c optional uart
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dev/uart/uart_dev_mu.c optional uart uart_mu
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dev/uart/uart_dev_pl011.c optional uart pl011
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dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220
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dev/usb/controller/dwc3.c optional fdt dwc3
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dev/usb/controller/ehci_mv.c optional ehci_mv fdt
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dev/usb/controller/generic_ehci.c optional ehci
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dev/usb/controller/generic_ehci_acpi.c optional ehci acpi
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349
sys/dev/usb/controller/dwc3.c
Normal file
349
sys/dev/usb/controller/dwc3.c
Normal file
@ -0,0 +1,349 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#include <dev/usb/controller/xhci.h>
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#include <dev/usb/controller/dwc3.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/phy/phy_usb.h>
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#include "generic_xhci.h"
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static struct ofw_compat_data compat_data[] = {
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{ "snps,dwc3", 1 },
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{ NULL, 0 }
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};
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struct snps_dwc3_softc {
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struct xhci_softc sc;
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device_t dev;
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char dr_mode[16];
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struct resource * mem_res;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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phandle_t node;
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phy_t usb2_phy;
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phy_t usb3_phy;
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};
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#define DWC3_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->bst, _sc->bsh, _off, _val)
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#define DWC3_READ(_sc, _off) \
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bus_space_read_4(_sc->bst, _sc->bsh, _off)
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static int
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snps_dwc3_attach_xhci(device_t dev)
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{
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struct snps_dwc3_softc *snps_sc = device_get_softc(dev);
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struct xhci_softc *sc = &snps_sc->sc;
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int err = 0, rid = 0;
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sc->sc_io_res = snps_sc->mem_res;
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sc->sc_io_tag = snps_sc->bst;
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sc->sc_io_hdl = snps_sc->bsh;
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sc->sc_io_size = rman_get_size(snps_sc->mem_res);
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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device_printf(dev, "Failed to allocate IRQ\n");
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return (ENXIO);
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}
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sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
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if (sc->sc_bus.bdev == NULL) {
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device_printf(dev, "Failed to add USB device\n");
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return (ENXIO);
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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sprintf(sc->sc_vendor, "Synopsys");
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device_set_desc(sc->sc_bus.bdev, "Synopsys");
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err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
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if (err != 0) {
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device_printf(dev, "Failed to setup IRQ, %d\n", err);
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sc->sc_intr_hdl = NULL;
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return (err);
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}
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err = xhci_init(sc, dev, 1);
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if (err != 0) {
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device_printf(dev, "Failed to init XHCI, with error %d\n", err);
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return (ENXIO);
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}
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err = xhci_start_controller(sc);
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if (err != 0) {
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device_printf(dev, "Failed to start XHCI controller, with error %d\n", err);
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return (ENXIO);
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}
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device_printf(sc->sc_bus.bdev, "trying to attach\n");
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err = device_probe_and_attach(sc->sc_bus.bdev);
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if (err != 0) {
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device_printf(dev, "Failed to initialize USB, with error %d\n", err);
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return (ENXIO);
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}
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return (0);
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}
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#if 0
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static void
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snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc)
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{
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uint32_t reg;
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reg = DWC3_READ(sc, DWC3_GCTL);
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device_printf(sc->dev, "GCTL: %x\n", reg);
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reg = DWC3_READ(sc, DWC3_GUCTL1);
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device_printf(sc->dev, "GUCTL1: %x\n", reg);
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reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);
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device_printf(sc->dev, "GUSB2PHYCFG0: %x\n", reg);
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reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0);
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device_printf(sc->dev, "GUSB3PIPECTL0: %x\n", reg);
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reg = DWC3_READ(sc, DWC3_DCFG);
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device_printf(sc->dev, "DCFG: %x\n", reg);
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}
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#endif
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static void
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snps_dwc3_reset(struct snps_dwc3_softc *sc)
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{
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uint32_t gctl, phy2, phy3;
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if (sc->usb2_phy)
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phy_enable(sc->usb2_phy);
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if (sc->usb3_phy)
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phy_enable(sc->usb3_phy);
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gctl = DWC3_READ(sc, DWC3_GCTL);
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gctl |= DWC3_GCTL_CORESOFTRESET;
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DWC3_WRITE(sc, DWC3_GCTL, gctl);
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phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);
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phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST;
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DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2);
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phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0);
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phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST;
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DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3);
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DELAY(1000);
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phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST;
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DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2);
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phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST;
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DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3);
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gctl &= ~DWC3_GCTL_CORESOFTRESET;
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DWC3_WRITE(sc, DWC3_GCTL, gctl);
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}
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static void
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snps_dwc3_configure_host(struct snps_dwc3_softc *sc)
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{
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uint32_t reg;
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reg = DWC3_READ(sc, DWC3_GCTL);
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reg &= ~DWC3_GCTL_PRTCAPDIR_MASK;
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reg |= DWC3_GCTL_PRTCAPDIR_HOST;
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DWC3_WRITE(sc, DWC3_GCTL, reg);
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}
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static void
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snps_dwc3_configure_phy(struct snps_dwc3_softc *sc)
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{
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char *phy_type;
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uint32_t reg;
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int nphy_types;
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phy_type = NULL;
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nphy_types = OF_getprop_alloc(sc->node, "phy_type", (void **)&phy_type);
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if (nphy_types <= 0)
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return;
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reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);
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if (strncmp(phy_type, "utmi_wide", 9) == 0) {
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reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf));
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reg |= DWC3_GUSB2PHYCFG0_PHYIF |
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DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS);
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} else {
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reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf));
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reg |= DWC3_GUSB2PHYCFG0_PHYIF |
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DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS);
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}
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DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg);
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}
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static void
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snps_dwc3_do_quirks(struct snps_dwc3_softc *sc)
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{
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uint32_t reg;
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reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);
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if (OF_hasprop(sc->node, "snps,dis-u2-freeclk-exists-quirk"))
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reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;
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else
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reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;
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if (OF_hasprop(sc->node, "snps,dis_u2_susphy_quirk"))
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reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20;
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else
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reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20;
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if (OF_hasprop(sc->node, "snps,dis_enblslpm_quirk"))
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reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM;
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else
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reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM;
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DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg);
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reg = DWC3_READ(sc, DWC3_GUCTL1);
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if (OF_hasprop(sc->node, "snps,dis-tx-ipgap-linecheck-quirk"))
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reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
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DWC3_WRITE(sc, DWC3_GUCTL1, reg);
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if (OF_hasprop(sc->node, "snps,dis-del-phy-power-chg-quirk")) {
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reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0);
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reg |= DWC3_GUSB3PIPECTL0_DELAYP1TRANS;
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DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg);
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}
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}
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static int
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snps_dwc3_probe(device_t dev)
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{
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struct snps_dwc3_softc *sc;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->node = ofw_bus_get_node(dev);
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OF_getprop(sc->node, "dr_mode", sc->dr_mode, sizeof(sc->dr_mode));
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if (strcmp(sc->dr_mode, "host") != 0) {
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device_printf(dev, "Only host mode is supported\n");
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return (ENXIO);
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}
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device_set_desc(dev, "Synopsys Designware DWC3");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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snps_dwc3_attach(device_t dev)
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{
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struct snps_dwc3_softc *sc;
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int rid = 0;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Failed to map memory\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->mem_res);
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sc->bsh = rman_get_bushandle(sc->mem_res);
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if (bootverbose)
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device_printf(dev, "snps id: %x\n", DWC3_READ(sc, DWC3_GSNPSID));
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/* Get the phys */
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phy_get_by_ofw_name(dev, sc->node, "usb2-phy", &sc->usb2_phy);
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phy_get_by_ofw_name(dev, sc->node, "usb3-phy", &sc->usb3_phy);
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snps_dwc3_reset(sc);
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snps_dwc3_configure_host(sc);
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snps_dwc3_configure_phy(sc);
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snps_dwc3_do_quirks(sc);
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#if 0
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snsp_dwc3_dump_regs(sc);
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#endif
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snps_dwc3_attach_xhci(dev);
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return (0);
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}
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static device_method_t snps_dwc3_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, snps_dwc3_probe),
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DEVMETHOD(device_attach, snps_dwc3_attach),
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DEVMETHOD_END
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};
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static driver_t snps_dwc3_driver = {
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"xhci",
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snps_dwc3_methods,
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sizeof(struct snps_dwc3_softc)
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};
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static devclass_t snps_dwc3_devclass;
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DRIVER_MODULE(snps_dwc3, simplebus, snps_dwc3_driver, snps_dwc3_devclass, 0, 0);
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MODULE_DEPEND(snps_dwc3, xhci, 1, 1, 1);
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116
sys/dev/usb/controller/dwc3.h
Normal file
116
sys/dev/usb/controller/dwc3.h
Normal file
@ -0,0 +1,116 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
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*
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* Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org>
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
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* $FreeBSD$
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*
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*/
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#ifndef _DWC3_H_
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#define _DWC3_H_
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#define DWC3_GSBUSCFG0 0xc100
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#define DWC3_GSBUSCFG1 0xc104
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#define DWC3_GTXTHRCFG 0xc108
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#define DWC3_GRXTHRCFG 0xc10C
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/* Global Core Control Register */
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#define DWC3_GCTL 0xc110
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#define DWC3_GCTL_PRTCAPDIR_MASK (0x3 << 12)
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#define DWC3_GCTL_PRTCAPDIR_HOST (0x1 << 12)
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#define DWC3_GCTL_PRTCAPDIR_DEVICE (0x2 << 12)
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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#define DWC3_GPMSTS 0xc114
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#define DWC3_GSTS 0xc118
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#define DWC3_GUCTL1 0xc11c
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#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28)
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#define DWC3_GSNPSID 0xc120
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#define DWC3_GGPIO 0xc124
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#define DWC3_GUID 0xc128
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#define DWC3_GUCTL 0xc12C
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#define DWC3_GBUSERRADDRLO 0xc130
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#define DWC3_GBUSERRADDRHI 0xc134
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#define DWC3_GPRTBIMAPLO 0xc138
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#define DWC3_GHWPARAMS0 0xc140
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#define DWC3_GHWPARAMS1 0xc144
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#define DWC3_GHWPARAMS2 0xc148
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#define DWC3_GHWPARAMS3 0xc14C
|
||||
#define DWC3_GHWPARAMS4 0xc150
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||||
#define DWC3_GHWPARAMS5 0xc154
|
||||
#define DWC3_GHWPARAMS6 0xc158
|
||||
#define DWC3_GHWPARAMS7 0xc15C
|
||||
#define DWC3_GDBGFIFOSPACE 0xc160
|
||||
#define DWC3_GDBGLTSSM 0xc164
|
||||
#define DWC3_GDBGLNMCC 0xc168
|
||||
#define DWC3_GDBGBMU 0xc16C
|
||||
#define DWC3_GDBGLSPMUX 0xc170
|
||||
#define DWC3_GDBGLSP 0xc174
|
||||
#define DWC3_GDBGEPINFO0 0xc178
|
||||
#define DWC3_GDBGEPINFO1 0xc17C
|
||||
#define DWC3_GPRTBIMAP_HSLO 0xc180
|
||||
#define DWC3_GPRTBIMAP_FSLO 0xc188
|
||||
|
||||
#define DWC3_GUSB2PHYCFG0 0xc200
|
||||
#define DWC3_GUSB2PHYCFG0_PHYSOFTRST (1 << 31)
|
||||
#define DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS (1 << 30)
|
||||
#define DWC3_GUSB2PHYCFG0_USBTRDTIM(n) ((n) << 10)
|
||||
#define DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS 9
|
||||
#define DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS 5
|
||||
#define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8)
|
||||
#define DWC3_GUSB2PHYCFG0_PHYSEL(x) ((x >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */
|
||||
#define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6)
|
||||
#define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4)
|
||||
#define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3)
|
||||
|
||||
#define DWC3_GUSB3PIPECTL0 0xc2c0
|
||||
#define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31)
|
||||
#define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18)
|
||||
|
||||
#define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * x)
|
||||
#define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * x)
|
||||
#define DWC3_GEVNTADRLO0 0xc400
|
||||
#define DWC3_GEVNTADRHI0 0xc404
|
||||
#define DWC3_GEVNTSIZ0 0xc408
|
||||
#define DWC3_GEVNTCOUNT0 0xc40C
|
||||
#define DWC3_GHWPARAMS8 0xc600
|
||||
#define DWC3_GTXFIFOPRIDEV 0xc610
|
||||
#define DWC3_GTXFIFOPRIHST 0xc618
|
||||
#define DWC3_GRXFIFOPRIHST 0xc61c
|
||||
#define DWC3_GFIFOPRIDBC 0xc620
|
||||
#define DWC3_GDMAHLRATIO 0xc624
|
||||
#define DWC3_GFLADJ 0xc630
|
||||
#define DWC3_DCFG 0xc700
|
||||
#define DWC3_DCTL 0xc704
|
||||
#define DWC3_DEVTEN 0xc708
|
||||
#define DWC3_DSTS 0xc70C
|
||||
#define DWC3_DGCMDPAR 0xc710
|
||||
#define DWC3_DGCMD 0xc714
|
||||
#define DWC3_DALEPENA 0xc720
|
||||
|
||||
#endif /* _DWC3_H_ */
|
||||
Loading…
Reference in New Issue
Block a user