Tunes to AHCI reset sequences:
- specification claims that 1 second is just a maximum controller reset time; implement controller reset properly to save almost 1 second of boot, and about half second of resume time; - enable channel interrupts only after channel status reset to fix duplicate device creation on resume due to unwanted device connection event; - as described in specification, wait for disk ready status after channel power-up; it is not so important when disk already touched by BIOS, but solves device not ready problems on resume and probably some other cases. - uncomment channel stop/start on soft-reset as it is declared mandatory by specification; it was commented due to some random drive detection problems on VIA and JMicron controllers, but I hope it is fixed by previous point.
This commit is contained in:
Alexander Motin
parent
9480550eca
commit
ce66729032
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=188621
@ -153,14 +153,19 @@ static int
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ata_ahci_ctlr_reset(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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int timeout;
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/* enable AHCI mode */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
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/* reset AHCI controller */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
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DELAY(1000000);
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR);
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for (timeout = 1000; timeout > 0; timeout--) {
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DELAY(1000);
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if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
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break;
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}
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if (timeout == 0) {
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device_printf(dev, "AHCI controller reset failure\n");
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return ENXIO;
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}
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@ -517,7 +522,7 @@ ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
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}
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static void
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ata_ahci_restart(device_t dev)
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ata_ahci_stop(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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@ -540,6 +545,16 @@ ata_ahci_restart(device_t dev)
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}
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}
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while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
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}
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static void
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ata_ahci_clo(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int32_t cmd;
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int offset = ch->unit << 7;
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int timeout;
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/* issue Command List Override if supported */
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
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@ -556,6 +571,15 @@ ata_ahci_restart(device_t dev)
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}
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while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
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}
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}
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static void
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ata_ahci_start(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int32_t cmd;
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int offset = ch->unit << 7;
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/* clear SATA error register */
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ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
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@ -571,19 +595,39 @@ ata_ahci_restart(device_t dev)
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(ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
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}
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static void
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ata_ahci_wait_ready(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = ch->unit << 7;
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int timeout = 0;
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while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) &
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(ATA_S_BUSY | ATA_S_DRQ)) {
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DELAY(1000);
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if (timeout++ > 1000) {
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device_printf(dev, "port is not ready\n");
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break;
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}
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}
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if (bootverbose)
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device_printf(dev, "ready wait time=%dms\n", timeout);
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}
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static u_int32_t
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ata_ahci_softreset(device_t dev, int port)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = ch->unit << 7;
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int timeout = 0;
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#ifdef AHCI_PM
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struct ata_ahci_cmd_tab *ctp =
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(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
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/* kick controller into sane state if needed */
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ata_ahci_restart(dev);
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/* kick controller into sane state */
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ata_ahci_stop(dev);
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ata_ahci_clo(dev);
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ata_ahci_start(dev);
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/* pull reset active */
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bzero(ctp->cfis, 64);
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@ -607,18 +651,7 @@ ata_ahci_softreset(device_t dev, int port)
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if (ata_ahci_issue_cmd(dev, 0, 0))
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return -1;
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ata_udelay(150000);
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#endif
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do {
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DELAY(1000);
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if (timeout++ > 1000) {
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device_printf(dev, "still BUSY after softreset\n");
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break;
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}
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} while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) & ATA_S_BUSY);
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if (bootverbose)
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device_printf(dev, "BUSY wait time=%dms\n", timeout);
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ata_ahci_wait_ready(dev);
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return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
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}
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@ -629,7 +662,7 @@ ata_ahci_reset(device_t dev)
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int64_t work;
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u_int32_t cmd, signature;
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u_int32_t signature;
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int offset = ch->unit << 7;
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if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
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@ -646,19 +679,11 @@ ata_ahci_reset(device_t dev)
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
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/* enable wanted port interrupts */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
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(ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
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ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
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ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
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ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
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ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
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/* activate the channel and power/spin up device */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
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(ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD));
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ata_ahci_restart(dev);
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ata_ahci_stop(dev);
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/* enable FIS based switching */
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//ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, 0x00000003);
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@ -668,13 +693,25 @@ ata_ahci_reset(device_t dev)
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device_printf(dev, "phy reset found no device\n");
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ch->devices = 0;
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/* kill off all activity on this channel */
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cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
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cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
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/* enable wanted port interrupts */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
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(ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC));
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return;
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}
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ata_ahci_start(dev);
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/* enable wanted port interrupts */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
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(ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
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ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
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ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
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ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
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ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
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/* Wait for initial TFD from device. */
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ata_ahci_wait_ready(dev);
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/* only probe for PortMultiplier if HW has support */
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM)
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signature = ata_ahci_softreset(dev, ATA_PM);
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