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Remove some unused cruft.

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This commit is contained in:
Neel Natu 2010-03-04 05:37:19 +00:00
parent 6be470c077
commit cefb7b77f8
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=204690
1 changed files with 0 additions and 47 deletions
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47
sys/mips/include/cpuinfo.h
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@ -71,53 +71,6 @@ struct mips_cpuinfo {
extern struct mips_cpuinfo cpuinfo;
/* TODO: Merge above structure with NetBSD's below. */
struct cpu_info {
#ifdef notyet
struct schedstate_percpu ci_schedstate; /* scheduler state */
#endif
u_long ci_cpu_freq; /* CPU frequency */
u_long ci_cycles_per_hz; /* CPU freq / hz */
u_long ci_divisor_delay; /* for delay/DELAY */
u_long ci_divisor_recip; /* scaled reciprocal of previous;
see below */
#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
u_long ci_spin_locks; /* # of spin locks held */
u_long ci_simple_locks; /* # of simple locks held */
#endif
};
/*
* To implement a more accurate microtime using the CP0 COUNT register
* we need to divide that register by the number of cycles per MHz.
* But...
*
* DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT
* and MULTU are only 12 clocks on the same CPU.
*
* The strategy we use is to calculate the reciprical of cycles per MHz,
* scaled by 1<<32. Then we can simply issue a MULTU and pluck of the
* HI register and have the results of the division.
*/
#define MIPS_SET_CI_RECIPRICAL(cpu) \
do { \
KASSERT((cpu)->ci_divisor_delay != 0, ("divisor delay")); \
(cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \
} while (0)
#define MIPS_COUNT_TO_MHZ(cpu, count, res) \
__asm __volatile ("multu %1,%2 ; mfhi %0" \
: "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip))
extern struct cpu_info cpu_info_store;
#if 0
#define curcpu() (&cpu_info_store)
#define cpu_number() (0)
#endif
#endif /* !LOCORE */
#endif /* _KERNEL */
#endif /* _CPUINFO_H_ */