Begin the initial support for the mips1004kc core.
* add build option; * add initial coherence manager config register bits; * use the right hazard instruction (ehb); * add page attributes. Tested: * MT7621A SoC (not yet in-tree) Submitted by: Stanislav Galabov <sgalabov@gmail.com>
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=292692
@ -31,6 +31,7 @@
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CPU_MIPS4KC opt_global.h
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CPU_MIPS24KC opt_global.h
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CPU_MIPS74KC opt_global.h
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CPU_MIPS1004KC opt_global.h
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CPU_MIPS32 opt_global.h
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CPU_MIPS64 opt_global.h
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CPU_SENTRY5 opt_global.h
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@ -248,7 +248,7 @@ MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
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#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
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MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
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#endif
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#ifdef CPU_NLM
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#if defined(CPU_NLM) || defined(CPU_MIPS1004KC)
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MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
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#endif
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MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
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@ -259,6 +259,7 @@ MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
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MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
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#endif
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MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
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MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
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/* XXX: Some of these registers are specific to MIPS32. */
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#if !defined(__mips_n64)
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@ -154,6 +154,11 @@
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#define MIPS_CCA_CACHED 0x03
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#endif
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#if defined(CPU_MIPS1004KC)
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#define MIPS_CCA_UNCACHED 0x02
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#define MIPS_CCA_CACHED 0x05
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#endif
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#ifndef MIPS_CCA_UNCACHED
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#define MIPS_CCA_UNCACHED MIPS_CCA_UC
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#endif
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@ -209,7 +214,7 @@
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#define COP0_SYNC .word 0xc0 /* ehb */
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#elif defined(CPU_SB1)
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#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
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#elif defined(CPU_MIPS74KC)
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#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC)
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#define COP0_SYNC .word 0xc0 /* ehb */
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#else
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/*
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@ -557,6 +562,8 @@
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#define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */
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#define MIPS_CONFIG2_SS_MASK 0xf
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#define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */
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#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
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#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
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#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
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@ -634,4 +641,8 @@
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#define MIPS_OPCODE_SHIFT 26
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#define MIPS_OPCODE_C1 0x11
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/* Coherence manager constants */
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#define MIPS_CMGCRB_BASE 11
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#define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1))
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#endif /* _MIPS_CPUREGS_H_ */
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