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Begin the initial support for the mips1004kc core.

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* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.

Tested:

* MT7621A SoC (not yet in-tree)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
This commit is contained in:
Adrian Chadd 2015-12-24 15:52:21 +00:00
parent 4b1859c0e9
commit d06ccd84b3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=292692
3 changed files with 15 additions and 2 deletions
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1
sys/conf/options.mips
View File

@ -31,6 +31,7 @@
CPU_MIPS4KC opt_global.h
CPU_MIPS24KC opt_global.h
CPU_MIPS74KC opt_global.h
CPU_MIPS1004KC opt_global.h
CPU_MIPS32 opt_global.h
CPU_MIPS64 opt_global.h
CPU_SENTRY5 opt_global.h

3
sys/mips/include/cpufunc.h
View File

@ -248,7 +248,7 @@ MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
#endif
#ifdef CPU_NLM
#if defined(CPU_NLM) || defined(CPU_MIPS1004KC)
MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
#endif
MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
@ -259,6 +259,7 @@ MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
#endif
MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
/* XXX: Some of these registers are specific to MIPS32. */
#if !defined(__mips_n64)

13
sys/mips/include/cpuregs.h
View File

@ -154,6 +154,11 @@
#define MIPS_CCA_CACHED 0x03
#endif
#if defined(CPU_MIPS1004KC)
#define MIPS_CCA_UNCACHED 0x02
#define MIPS_CCA_CACHED 0x05
#endif
#ifndef MIPS_CCA_UNCACHED
#define MIPS_CCA_UNCACHED MIPS_CCA_UC
#endif
@ -209,7 +214,7 @@
#define COP0_SYNC .word 0xc0 /* ehb */
#elif defined(CPU_SB1)
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
#elif defined(CPU_MIPS74KC)
#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC)
#define COP0_SYNC .word 0xc0 /* ehb */
#else
/*
@ -557,6 +562,8 @@
#define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */
#define MIPS_CONFIG2_SS_MASK 0xf
#define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */
#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
@ -634,4 +641,8 @@
#define MIPS_OPCODE_SHIFT 26
#define MIPS_OPCODE_C1 0x11
/* Coherence manager constants */
#define MIPS_CMGCRB_BASE 11
#define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1))
#endif /* _MIPS_CPUREGS_H_ */