x86_msr_op: extend the KPI to allow MSR read and single-CPU operations
Reivewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D31386
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@ -261,8 +261,8 @@ iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
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if ((cpu_stdext_feature3 & CPUID_STDEXT3_TSXFA) != 0 &&
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!pmc_tsx_force_abort_set) {
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pmc_tsx_force_abort_set = true;
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x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS |
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MSR_OP_WRITE, 1);
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x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS_ALL |
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MSR_OP_WRITE, 1, NULL);
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}
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flags = 0;
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@ -403,8 +403,8 @@ iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
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MPASS(pmc_alloc_refs > 0);
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if (pmc_alloc_refs-- == 1 && pmc_tsx_force_abort_set) {
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pmc_tsx_force_abort_set = false;
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x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS |
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MSR_OP_WRITE, 0);
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x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS_ALL |
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MSR_OP_WRITE, 0, NULL);
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}
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return (0);
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@ -154,12 +154,24 @@ int user_dbreg_trap(register_t dr6);
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int minidumpsys(struct dumperinfo *);
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struct pcb *get_pcb_td(struct thread *td);
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/*
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* MSR ops for x86_msr_op()
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*/
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#define MSR_OP_ANDNOT 0x00000001
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#define MSR_OP_OR 0x00000002
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#define MSR_OP_WRITE 0x00000003
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#define MSR_OP_READ 0x00000004
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/*
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* Where and which execution mode
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*/
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#define MSR_OP_LOCAL 0x10000000
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#define MSR_OP_SCHED 0x20000000
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#define MSR_OP_RENDEZVOUS 0x30000000
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void x86_msr_op(u_int msr, u_int op, uint64_t arg1);
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#define MSR_OP_SCHED_ALL 0x20000000
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#define MSR_OP_SCHED_ONE 0x30000000
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#define MSR_OP_RENDEZVOUS_ALL 0x40000000
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#define MSR_OP_RENDEZVOUS_ONE 0x50000000
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#define MSR_OP_CPUID(id) ((id) << 8)
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void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res);
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#endif
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@ -119,6 +119,7 @@ struct msr_op_arg {
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u_int msr;
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int op;
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uint64_t arg1;
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uint64_t *res;
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};
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static void
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@ -142,33 +143,41 @@ x86_msr_op_one(void *argp)
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case MSR_OP_WRITE:
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wrmsr(a->msr, a->arg1);
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break;
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case MSR_OP_READ:
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v = rdmsr(a->msr);
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*a->res = v;
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break;
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}
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}
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#define MSR_OP_EXMODE_MASK 0xf0000000
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#define MSR_OP_OP_MASK 0x000000ff
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#define MSR_OP_GET_CPUID(x) (((x) & ~MSR_OP_EXMODE_MASK) >> 8)
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void
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x86_msr_op(u_int msr, u_int op, uint64_t arg1)
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x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res)
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{
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struct thread *td;
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struct msr_op_arg a;
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cpuset_t set;
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u_int exmode;
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int bound_cpu, i, is_bound;
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int bound_cpu, cpu, i, is_bound;
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a.op = op & MSR_OP_OP_MASK;
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MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR ||
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a.op == MSR_OP_WRITE);
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a.op == MSR_OP_WRITE || a.op == MSR_OP_READ);
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exmode = op & MSR_OP_EXMODE_MASK;
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MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED ||
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exmode == MSR_OP_RENDEZVOUS);
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MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED_ALL ||
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exmode == MSR_OP_SCHED_ONE || exmode == MSR_OP_RENDEZVOUS_ALL ||
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exmode == MSR_OP_RENDEZVOUS_ONE);
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a.msr = msr;
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a.arg1 = arg1;
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a.res = res;
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switch (exmode) {
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case MSR_OP_LOCAL:
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x86_msr_op_one(&a);
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break;
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case MSR_OP_SCHED:
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case MSR_OP_SCHED_ALL:
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td = curthread;
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thread_lock(td);
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is_bound = sched_is_bound(td);
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@ -183,8 +192,32 @@ x86_msr_op(u_int msr, u_int op, uint64_t arg1)
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sched_unbind(td);
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thread_unlock(td);
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break;
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case MSR_OP_RENDEZVOUS:
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smp_rendezvous(NULL, x86_msr_op_one, NULL, &a);
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case MSR_OP_SCHED_ONE:
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td = curthread;
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cpu = MSR_OP_GET_CPUID(op);
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thread_lock(td);
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is_bound = sched_is_bound(td);
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bound_cpu = td->td_oncpu;
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if (!is_bound || bound_cpu != cpu)
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sched_bind(td, cpu);
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x86_msr_op_one(&a);
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if (is_bound) {
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if (bound_cpu != cpu)
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sched_bind(td, bound_cpu);
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} else {
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sched_unbind(td);
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}
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thread_unlock(td);
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break;
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case MSR_OP_RENDEZVOUS_ALL:
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smp_rendezvous(smp_no_rendezvous_barrier, x86_msr_op_one,
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smp_no_rendezvous_barrier, &a);
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break;
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case MSR_OP_RENDEZVOUS_ONE:
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cpu = MSR_OP_GET_CPUID(op);
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CPU_SETOF(cpu, &set);
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smp_rendezvous_cpus(set, smp_no_rendezvous_barrier,
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x86_msr_op_one, smp_no_rendezvous_barrier, &a);
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break;
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}
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}
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@ -872,9 +905,9 @@ hw_ibrs_recalculate(bool for_all_cpus)
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{
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if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
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x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ?
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MSR_OP_RENDEZVOUS : MSR_OP_LOCAL) |
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MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL) |
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(hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR),
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IA32_SPEC_CTRL_IBRS);
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IA32_SPEC_CTRL_IBRS, NULL);
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hw_ibrs_active = hw_ibrs_disable == 0;
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hw_ibrs_ibpb_active = 0;
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} else {
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@ -930,7 +963,8 @@ hw_ssb_set(bool enable, bool for_all_cpus)
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hw_ssb_active = enable;
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x86_msr_op(MSR_IA32_SPEC_CTRL,
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(enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
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(for_all_cpus ? MSR_OP_SCHED : MSR_OP_LOCAL), IA32_SPEC_CTRL_SSBD);
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(for_all_cpus ? MSR_OP_SCHED_ALL : MSR_OP_LOCAL),
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IA32_SPEC_CTRL_SSBD, NULL);
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}
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void
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@ -1221,8 +1255,9 @@ taa_set(bool enable, bool all)
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x86_msr_op(MSR_IA32_TSX_CTRL,
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(enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
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(all ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL),
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IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR);
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(all ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
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IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR,
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NULL);
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}
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void
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@ -1386,8 +1421,8 @@ x86_rngds_mitg_recalculate(bool all_cpus)
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return;
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x86_msr_op(MSR_IA32_MCU_OPT_CTRL,
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(x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
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(all_cpus ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL),
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IA32_RNGDS_MITG_DIS);
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(all_cpus ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
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IA32_RNGDS_MITG_DIS, NULL);
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}
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static int
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