Make Marvell Armada watchdog driver more generic
Store platform dependent functions and constants in mv_wdt_config structure and select proper configuration on runtime based on compatible string provided in FDT. Marvell Armada38X and ArmadaXP non-repetitive registers are moved to generic part of code. To support armv5 as well, use proper compatible string: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/watchdog/orion_wdt.c?h=v4.13-rc3#n456 Submitted by: Rafal Kozik <rk@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14740
This commit is contained in:
Marcin Wojtas
parent
5d7ae54a5d
commit
d100eecfc4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=331960
@ -53,22 +53,54 @@ __FBSDID("$FreeBSD$");
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#define INITIAL_TIMECOUNTER (0xffffffff)
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#define MAX_WATCHDOG_TICKS (0xffffffff)
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#define WD_RST_OUT_EN 0x00000002
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
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#else
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#define MV_CLOCK_SRC get_tclk()
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#endif
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#define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
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#if defined(SOC_MV_ARMADA38X)
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#define WATCHDOG_TIMER 4
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#else
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#define WATCHDOG_TIMER 2
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#endif
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struct mv_wdt_config {
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enum soc_family wdt_soc;
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uint32_t wdt_timer;
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void (*wdt_enable)(void);
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void (*wdt_disable)(void);
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unsigned int wdt_clock_src;
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};
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static void mv_wdt_enable_armv5(void);
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static void mv_wdt_enable_armada_38x(void);
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static void mv_wdt_enable_armada_xp(void);
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static void mv_wdt_disable_armv5(void);
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static void mv_wdt_disable_armada_38x(void);
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static void mv_wdt_disable_armada_xp(void);
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static struct mv_wdt_config mv_wdt_armada_38x_config = {
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.wdt_soc = MV_SOC_ARMADA_38X,
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.wdt_timer = 4,
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.wdt_enable = &mv_wdt_enable_armada_38x,
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.wdt_disable = &mv_wdt_disable_armada_38x,
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.wdt_clock_src = MV_CLOCK_SRC_ARMV7,
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};
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static struct mv_wdt_config mv_wdt_armada_xp_config = {
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.wdt_soc = MV_SOC_ARMADA_XP,
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.wdt_timer = 2,
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.wdt_enable = &mv_wdt_enable_armada_xp,
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.wdt_disable = &mv_wdt_disable_armada_xp,
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.wdt_clock_src = MV_CLOCK_SRC_ARMV7,
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};
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static struct mv_wdt_config mv_wdt_armv5_config = {
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.wdt_soc = MV_SOC_ARMV5,
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.wdt_timer = 2,
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.wdt_enable = &mv_wdt_enable_armv5,
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.wdt_disable = &mv_wdt_disable_armv5,
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.wdt_clock_src = 0,
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};
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struct mv_wdt_softc {
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struct resource * wdt_res;
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struct mtx wdt_mtx;
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struct mv_wdt_config * wdt_config;
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};
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static struct resource_spec mv_wdt_spec[] = {
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@ -77,8 +109,10 @@ static struct resource_spec mv_wdt_spec[] = {
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};
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static struct ofw_compat_data mv_wdt_compat[] = {
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{"marvell,armada-380-wdt", true},
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{NULL, false}
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{"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config},
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{"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config},
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{"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config},
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{NULL, (uintptr_t)NULL}
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};
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static struct mv_wdt_softc *wdt_softc = NULL;
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@ -91,8 +125,6 @@ static uint32_t mv_get_timer_control(void);
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static void mv_set_timer_control(uint32_t);
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static void mv_set_timer(uint32_t, uint32_t);
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static void mv_watchdog_enable(void);
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static void mv_watchdog_disable(void);
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static void mv_watchdog_event(void *, unsigned int, int *);
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static device_method_t mv_wdt_methods[] = {
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@ -145,7 +177,14 @@ mv_wdt_attach(device_t dev)
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mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
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mv_watchdog_disable();
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sc->wdt_config = (struct mv_wdt_config *)
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ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data;
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if (sc->wdt_config->wdt_clock_src == 0)
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sc->wdt_config->wdt_clock_src = get_tclk();
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
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return (0);
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@ -171,28 +210,15 @@ mv_set_timer(uint32_t timer, uint32_t val)
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bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);
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}
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static void
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mv_watchdog_enable(void)
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mv_wdt_enable_armv5(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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uint32_t irq_mask;
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#endif
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uint32_t val, irq_cause, irq_mask;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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#else
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER_WD_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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@ -200,44 +226,63 @@ mv_watchdog_enable(void)
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val |= WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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#endif
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val = mv_get_timer_control();
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#if defined(SOC_MV_ARMADA38X)
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val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
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#elif defined(SOC_MV_ARMADAXP)
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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#else
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
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#endif
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mv_set_timer_control(val);
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}
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static inline void
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mv_wdt_enable_armada_38x_xp_helper()
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{
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uint32_t val, irq_cause;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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}
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static void
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mv_wdt_enable_armada_38x(void)
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{
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uint32_t val;
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mv_wdt_enable_armada_38x_xp_helper();
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val = mv_get_timer_control();
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val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_disable(void)
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mv_wdt_enable_armada_xp(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
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uint32_t irq_mask;
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#endif
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uint32_t val;
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mv_wdt_enable_armada_38x_xp_helper();
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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mv_set_timer_control(val);
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}
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static void
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mv_wdt_disable_armv5(void)
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{
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uint32_t val, irq_cause, irq_mask;
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val = mv_get_timer_control();
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#if defined(SOC_MV_ARMADA38X)
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val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
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#else
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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#endif
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mv_set_timer_control(val);
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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#else
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val &= ~WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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@ -245,13 +290,50 @@ mv_watchdog_disable(void)
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask &= ~(IRQ_TIMER_WD_MASK);
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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#endif
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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}
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static __inline void
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mv_wdt_disable_armada_38x_xp_helper(void)
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{
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uint32_t val;
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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}
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static void
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mv_wdt_disable_armada_38x(void)
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{
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uint32_t val;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
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mv_set_timer_control(val);
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mv_wdt_disable_armada_38x_xp_helper();
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}
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static void
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mv_wdt_disable_armada_xp(void)
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{
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uint32_t val;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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mv_wdt_disable_armada_38x_xp_helper();
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}
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/*
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* Watchdog event handler.
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*/
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@ -264,20 +346,24 @@ mv_watchdog_event(void *arg, unsigned int cmd, int *error)
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sc = arg;
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mtx_lock(&sc->wdt_mtx);
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if (cmd == 0)
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mv_watchdog_disable();
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else {
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if (cmd == 0) {
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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} else {
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/*
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* Watchdog timeout is in nanosecs, calculation according to
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* watchdog(9)
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*/
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ns = (uint64_t)1 << (cmd & WD_INTERVAL);
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ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS)
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mv_watchdog_disable();
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ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS) {
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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}
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else {
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mv_set_timer(WATCHDOG_TIMER, ticks);
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mv_watchdog_enable();
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mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks);
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if (wdt_softc->wdt_config->wdt_enable != NULL)
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wdt_softc->wdt_config->wdt_enable();
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*error = 0;
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}
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}
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@ -105,20 +105,20 @@
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*/
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#define RSTOUTn_MASK 0x60
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#define RSTOUTn_MASK_WD 0x400
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#define SYSTEM_SOFT_RESET 0x64
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#define WD_RSTOUTn_MASK 0x4
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#define WD_GLOBAL_MASK 0x00000100
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#define WD_CPU0_MASK 0x00000001
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#define SOFT_RST_OUT_EN 0x00000001
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#define SYS_SOFT_RST 0x00000001
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#else
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#define RSTOUTn_MASK 0x8
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#define WD_RST_OUT_EN 0x00000002
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#define SOFT_RST_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET 0xc
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#define SYS_SOFT_RST 0x00000001
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#endif
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#define RSTOUTn_MASK_WD 0x400
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#define WD_RSTOUTn_MASK 0x4
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#define WD_GLOBAL_MASK 0x00000100
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#define WD_CPU0_MASK 0x00000001
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#define WD_RST_OUT_EN 0x00000002
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/*
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* Power Control
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