Begin promoting the AMD-originated feature flags to first class flags, now
that newer Intel cpu hardware implements them too. This includes things like the NX (pte no-execute) flag for execute protection. We'll need to reference this for implementing no-exec in pmap.c at some point. Some feature flags are duplicated in both the Intel-orignated bits and the AMD bits. Suppress the the duplicates correctly - the old code assumed they were a 1:1 mapping which is not correct. We can't just mask off the bits present in cpu_feature. Converge with amd64 where this originated from. Intel cpu's that implement any AMD features will report them in dmesg now. Approved by: re
This commit is contained in:
Peter Wemm
parent
8b7475ed75
commit
d14b395392
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=147691
@ -74,9 +74,6 @@ void enable_K6_2_wt_alloc(void);
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void panicifcpuunsupported(void);
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static void identifycyrix(void);
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#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
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static void print_AMD_features(void);
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#endif
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static void print_AMD_info(void);
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static void print_AMD_assoc(int i);
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static void print_transmeta_info(void);
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@ -175,6 +172,14 @@ printcpuinfo(void)
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}
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}
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/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
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if (cpu_exthigh >= 0x80000001 &&
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(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0)) {
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do_cpuid(0x80000001, regs);
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amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
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}
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if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
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if ((cpu_id & 0xf00) > 0x300) {
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u_int brand_index;
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@ -688,42 +693,80 @@ printcpuinfo(void)
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"\040PBE" /* Pending Break Enable */
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);
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if (cpu_feature2 != 0)
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printf("\n Features2=0x%b", cpu_feature2,
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"\020"
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"\001SSE3" /* SSE3 */
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"\002<b1>"
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"\003RSVD2" /* "Reserved" bit 2 */
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"\004MON" /* MONITOR/MWAIT Instructions */
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"\005DS_CPL" /* CPL Qualified Debug Store */
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"\006<b5>" /* Machine specific registers */
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"\007<b6>" /* Physical address extension */
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"\010EST" /* Enhanced SpeedStep */
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"\011TM2" /* Thermal Monitor 2 */
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"\012<b9>"
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"\013CNTX-ID" /* L1 context ID available */
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"\014<b11>"
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"\015<b12>"
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"\016CX16" /* CMPXCHG16B Instruction */
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"\017<b14>"
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"\020<b15>"
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"\021<b16>"
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\030<b23>"
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"\031<b24>"
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036<b29>"
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"\037<b30>"
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"\040<b31>"
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);
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if (cpu_feature2 != 0) {
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printf("\n Features2=0x%b", cpu_feature2,
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"\020"
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"\001SSE3" /* SSE3 */
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"\002<b1>"
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"\003RSVD2" /* "Reserved" bit 2 */
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"\004MON" /* MONITOR/MWAIT Instructions */
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"\005DS_CPL" /* CPL Qualified Debug Store */
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"\006<b5>" /* Machine specific registers */
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"\007<b6>" /* Physical address extension */
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"\010EST" /* Enhanced SpeedStep */
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"\011TM2" /* Thermal Monitor 2 */
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"\012<b9>"
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"\013CNTX-ID" /* L1 context ID available */
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"\014<b11>"
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"\015<b12>"
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"\016CX16" /* CMPXCHG16B Instruction */
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"\017<b14>"
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"\020<b15>"
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"\021<b16>"
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\030<b23>"
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"\031<b24>"
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036<b29>"
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"\037<b30>"
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"\040<b31>"
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);
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}
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if (amd_feature != 0) {
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printf("\n AMD Features=0x%b", amd_feature,
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"\020" /* in hex */
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"\001<s0>" /* Same */
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"\002<s1>" /* Same */
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"\003<s2>" /* Same */
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"\004<s3>" /* Same */
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"\005<s4>" /* Same */
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"\006<s5>" /* Same */
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"\007<s6>" /* Same */
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"\010<s7>" /* Same */
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"\011<s8>" /* Same */
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"\012<s9>" /* Same */
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"\013<b10>" /* Undefined */
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"\014SYSCALL" /* Have SYSCALL/SYSRET */
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"\015<s12>" /* Same */
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"\016<s13>" /* Same */
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"\017<s14>" /* Same */
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"\020<s15>" /* Same */
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"\021<s16>" /* Same */
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"\022<s17>" /* Same */
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"\023<b18>" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX */
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"\026<b21>" /* Undefined */
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"\027MMX+" /* AMD MMX Extensions */
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"\030<s23>" /* Same */
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"\031<s24>" /* Same */
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"\032<b25>" /* Undefined */
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"\033<b26>" /* Undefined */
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"\034<b27>" /* Undefined */
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"\035<b28>" /* Undefined */
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"\036LM" /* 64 bit long mode */
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"\0373DNow+" /* AMD 3DNow! Extensions */
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"\0403DNow" /* AMD 3DNow! */
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);
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}
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/*
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* If this CPU supports hyperthreading then mention
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@ -734,9 +777,6 @@ printcpuinfo(void)
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printf("\n Hyperthreading: %d logical CPUs",
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(cpu_procinfo & CPUID_HTT_CORES) >> 16);
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}
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if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
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cpu_exthigh >= 0x80000001)
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print_AMD_features();
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} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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printf(" DIR=0x%04x", cyrix_did);
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printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
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@ -1101,55 +1141,6 @@ print_AMD_info(void)
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}
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}
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#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
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static void
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print_AMD_features(void)
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{
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u_int regs[4];
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
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*/
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do_cpuid(0x80000001, regs);
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printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
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"\020" /* in hex */
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"\001FPU" /* Integral FPU */
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"\002VME" /* Extended VM86 mode support */
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"\003DE" /* Debug extensions */
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"\004PSE" /* 4MByte page tables */
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"\005TSC" /* Timestamp counter */
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"\006MSR" /* Machine specific registers */
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"\007PAE" /* Physical address extension */
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"\010MCE" /* Machine Check support */
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"\011CX8" /* CMPEXCH8 instruction */
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"\012APIC" /* SMP local APIC */
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"\013<b10>"
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"\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
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"\015MTRR" /* Memory Type Range Registers */
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"\016PGE" /* PG_G (global bit) support */
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"\017MCA" /* Machine Check Architecture */
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"\020ICMOV" /* CMOV instruction */
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"\021PAT" /* Page attributes table */
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"\022PGE36" /* 36 bit address space support */
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"\023RSVD" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX (no execute pte bit) */
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"\026<b21>"
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"\027AMIE" /* AMD MMX Instruction Extensions */
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"\030MMX"
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"\031FXSAVE" /* FXSAVE/FXRSTOR */
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036LM" /* Long mode */
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"\037DSP" /* AMD 3DNow! Instruction Extensions */
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"\0403DNow!" /* AMD 3DNow! Instructions */
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);
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}
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#endif
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static void
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print_transmeta_info()
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{
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@ -80,6 +80,7 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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int cpu = 0; /* Are we 386, 386sx, 486, etc? */
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u_int cpu_feature = 0; /* Feature flags */
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u_int cpu_feature2 = 0; /* Feature flags */
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u_int amd_feature = 0; /* Feature flags */
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u_int cpu_high = 0; /* Highest arg to CPUID */
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u_int cpu_id = 0; /* Stepping ID */
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u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
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@ -45,7 +45,9 @@ extern long Maxmem;
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extern u_int basemem; /* PA of original top of base memory */
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extern int busdma_swi_pending;
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extern u_int cpu_exthigh;
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extern u_int cpu_feature, cpu_feature2;
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extern u_int cpu_feature;
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extern u_int cpu_feature2;
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extern u_int amd_feature;
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extern u_int cpu_fxsr;
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extern u_int cpu_high;
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extern u_int cpu_id;
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