powerpc: Add support for additional FSCR-managed facilities
Add support to enable, save, and restore the following facilities: * Target Address Register (bctar) -- seemingly just another register to branch to. * Event-based branching -- an interrupt-like userspace event handler subsystem. * Load-monitored facility -- A facility that allows monitoring a range of physical memory, and triggering an event on access. Targeted to garbage collection software features.
This commit is contained in:
Justin Hibbits
parent
3eb5d5dd25
commit
d1d73b0e27
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=346796
@ -48,6 +48,7 @@ struct pcb {
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register_t pcb_lr; /* link register */
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register_t pcb_dscr; /* dscr value */
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register_t pcb_fscr;
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register_t pcb_tar;
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struct pmap *pcb_pm; /* pmap of our vmspace */
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jmp_buf *pcb_onfault; /* For use during
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copyin/copyout */
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@ -81,6 +82,17 @@ struct pcb {
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uint64_t texasr;
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uint64_t tfiar;
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} pcb_htm;
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struct ebb {
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uint64_t ebbhr;
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uint64_t ebbrr;
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uint64_t bescr;
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} pcb_ebb;
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struct lmon {
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uint64_t lmrr;
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uint64_t lmser;
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} pcb_lm;
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union {
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struct {
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@ -135,13 +135,14 @@
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#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
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#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
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#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
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#define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */
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#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
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#define FSCR_SCV 0x0000000000001000ULL /* scv instruction available */
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#define FSCR_LM 0x0000000000000800ULL /* Load monitored facilities available */
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#define FSCR_MSGP 0x0000000000000400ULL /* msgsndp and SPRs available */
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#define FSCR_TAR 0x0000000000000100ULL /* TAR register available */
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#define FSCR_EBB 0x0000000000000080ULL /* Event-based branch available */
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#define FSCR_DSCR 0x0000000000000004ULL /* DSCR available in PR state */
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#define FSCR_SCV 0x0000000000001000 /* scv instruction available */
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#define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */
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#define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */
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#define FSCR_TAR 0x0000000000000100 /* TAR register available */
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#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
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#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */
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#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */
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#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
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#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
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@ -197,6 +197,7 @@ ASSYM(PCB_CONTEXT, offsetof(struct pcb, pcb_context));
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ASSYM(PCB_CR, offsetof(struct pcb, pcb_cr));
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ASSYM(PCB_DSCR, offsetof(struct pcb, pcb_dscr));
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ASSYM(PCB_FSCR, offsetof(struct pcb, pcb_fscr));
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ASSYM(PCB_TAR, offsetof(struct pcb, pcb_tar));
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ASSYM(PCB_SP, offsetof(struct pcb, pcb_sp));
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ASSYM(PCB_TOC, offsetof(struct pcb, pcb_toc));
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ASSYM(PCB_LR, offsetof(struct pcb, pcb_lr));
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@ -212,6 +213,13 @@ ASSYM(PCB_BOOKE_DBCR0, offsetof(struct pcb, pcb_cpu.booke.dbcr0));
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ASSYM(PCB_VSCR, offsetof(struct pcb, pcb_vec.vscr));
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ASSYM(PCB_EBB_EBBHR, offsetof(struct pcb, pcb_ebb.ebbhr));
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ASSYM(PCB_EBB_EBBRR, offsetof(struct pcb, pcb_ebb.ebbrr));
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ASSYM(PCB_EBB_BESCR, offsetof(struct pcb, pcb_ebb.bescr));
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ASSYM(PCB_LMON_LMRR, offsetof(struct pcb, pcb_lm.lmrr));
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ASSYM(PCB_LMON_LMSER, offsetof(struct pcb, pcb_lm.lmser));
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ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
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ASSYM(TD_PROC, offsetof(struct thread, td_proc));
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ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
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@ -134,6 +134,27 @@ ENTRY(cpu_switch)
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beq 1f
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mfspr %r6, SPR_FSCR
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std %r6, PCB_FSCR(%r17)
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save_ebb:
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andi. %r0, %r6, FSCR_EBB
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beq save_lm
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mfspr %r7, SPR_EBBHR
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std %r7, PCB_EBB_EBBHR(%r17)
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mfspr %r7, SPR_EBBRR
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std %r7, PCB_EBB_EBBRR(%r17)
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mfspr %r7, SPR_BESCR
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std %r7, PCB_EBB_BESCR(%r17)
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save_lm:
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andi. %r0, %r6, FSCR_LM
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beq save_tar
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mfspr %r7, SPR_LMRR
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std %r7, PCB_LMON_LMRR(%r17)
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mfspr %r7, SPR_LMSER
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std %r7, PCB_LMON_LMSER(%r17)
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save_tar:
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andi. %r0, %r6, FSCR_TAR
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beq 1f
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mfspr %r7, SPR_TAR
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std %r7, PCB_TAR(%r17)
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1:
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andi. %r7, %r18, PCB_CDSCR
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beq .L0
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@ -223,6 +244,27 @@ blocked_loop:
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beq .L4
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ld %r7, PCB_FSCR(%r17) /* Load the FSCR register*/
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mtspr SPR_FSCR, %r7
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restore_ebb:
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andi. %r0, %r7, FSCR_EBB
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beq restore_lm
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ld %r6, PCB_EBB_EBBHR(%r17)
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mtspr SPR_EBBHR, %r6
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ld %r6, PCB_EBB_EBBRR(%r17)
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mtspr SPR_EBBRR, %r6
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ld %r6, PCB_EBB_BESCR(%r17)
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mtspr SPR_BESCR, %r6
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restore_lm:
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andi. %r0, %r7, FSCR_LM
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beq restore_tar
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ld %r6, PCB_LMON_LMRR(%r17)
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mtspr SPR_LMRR, %r6
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ld %r6, PCB_LMON_LMSER(%r17)
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mtspr SPR_LMSER, %r6
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restore_tar:
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andi. %r0, %r7, FSCR_TAR
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beq .L4
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ld %r6, PCB_TAR(%r17)
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mtspr SPR_TAR, %r6
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/* thread to restore is in r3 */
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.L4:
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@ -305,17 +305,41 @@ trap(struct trapframe *frame)
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case EXC_FAC:
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fscr = mfspr(SPR_FSCR);
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if ((fscr & FSCR_IC_MASK) == FSCR_IC_HTM) {
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CTR0(KTR_TRAP, "Hardware Transactional Memory subsystem disabled");
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} else if ((fscr & FSCR_IC_MASK) == FSCR_IC_DSCR) {
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switch (fscr & FSCR_IC_MASK) {
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case FSCR_IC_HTM:
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CTR0(KTR_TRAP,
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"Hardware Transactional Memory subsystem disabled");
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sig = SIGILL;
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ucode = ILL_ILLOPC;
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break;
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case FSCR_IC_DSCR:
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td->td_pcb->pcb_flags |= PCB_CFSCR | PCB_CDSCR;
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fscr &= ~FSCR_IC_MASK;
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mtspr(SPR_FSCR, fscr | FSCR_DSCR);
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fscr |= FSCR_DSCR;
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mtspr(SPR_DSCR, 0);
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break;
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case FSCR_IC_EBB:
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td->td_pcb->pcb_flags |= PCB_CFSCR;
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fscr |= FSCR_EBB;
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mtspr(SPR_EBBHR, 0);
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mtspr(SPR_EBBRR, 0);
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mtspr(SPR_BESCR, 0);
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break;
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case FSCR_IC_TAR:
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td->td_pcb->pcb_flags |= PCB_CFSCR;
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fscr |= FSCR_TAR;
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mtspr(SPR_TAR, 0);
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break;
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case FSCR_IC_LM:
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td->td_pcb->pcb_flags |= PCB_CFSCR;
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fscr |= FSCR_LM;
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mtspr(SPR_LMRR, 0);
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mtspr(SPR_LMSER, 0);
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break;
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default:
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sig = SIGILL;
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ucode = ILL_ILLOPC;
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}
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sig = SIGILL;
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ucode = ILL_ILLOPC;
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mtspr(SPR_FSCR, fscr & ~FSCR_IC_MASK);
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break;
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case EXC_HEA:
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sig = SIGILL;
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