Tekram supplied driver for their DC390 and DC390T controllers.
These controllers are based on the AMD 53c974, and the driver does only support those two cards, since it checks for a Tekram specific configuration EEPROM. This deficiency (TM) will be fixed soon ... :) This code is: (C)Copyright 1995-1996 Tekram Technology Co., Ltd. Obtained from: Tekram
This commit is contained in:
Stefan Eßer
parent
0df291ee25
commit
d26d022d05
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/cvs2svn/branches/TEKRAM/; revision=20537
1493
sys/pci/scsiiom.c
Normal file
1493
sys/pci/scsiiom.c
Normal file
File diff suppressed because it is too large
Load Diff
1679
sys/pci/tek390.c
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1679
sys/pci/tek390.c
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File diff suppressed because it is too large
Load Diff
667
sys/pci/tek390.h
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667
sys/pci/tek390.h
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@ -0,0 +1,667 @@
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/***********************************************************************
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;* File Name : TEK390.H *
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;* TEKRAM DC-390 PCI SCSI Bus Master Host Adapter *
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;* Device Driver *
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;***********************************************************************/
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#ifndef TEK390_H
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#define TEK390_H
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typedef unsigned char UCHAR;
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typedef unsigned short USHORT;
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typedef unsigned long ULONG;
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typedef unsigned int UINT;
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typedef UCHAR *PUCHAR;
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typedef USHORT *PUSHORT;
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typedef ULONG *PULONG;
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typedef struct scsi_link *PSCLINK, SCSILINK;
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typedef struct scsi_xfer *PSCSICMD, SCSICMD;
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typedef void *PVOID;
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/*;-----------------------------------------------------------------------*/
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typedef struct _SyncMsg
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{
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UCHAR ExtendMsg;
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UCHAR ExtMsgLen;
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UCHAR SyncXferReq;
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UCHAR Period;
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UCHAR ReqOffset;
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} SyncMsg;
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/*;-----------------------------------------------------------------------*/
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typedef struct _Capacity
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{
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ULONG BlockCount;
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ULONG BlockLength;
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} Capacity;
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/*;-----------------------------------------------------------------------*/
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typedef struct _SGentry
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{
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ULONG SGXLen;
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ULONG SGXPtr;
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} SGentry, *PSEG;
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typedef struct _SGentry1
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{
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ULONG SGXPtr1;
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ULONG SGXLen1;
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} SGentry1, *PSEG1;
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#define MAX_ADAPTER_NUM 4
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#define MAX_SCSI_ID 8
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#define MAX_SG_ENTRY 33
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#define MAX_DEVICES 10
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#define MAX_CMD_QUEUE 20
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#define MAX_CMD_PER_LUN 6
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#define MAX_SRB_CNT MAX_CMD_PER_LUN*4
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#define PAGELEN 4096
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/*
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;-----------------------------------------------------------------------
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; SCSI Request Block
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;-----------------------------------------------------------------------
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*/
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struct _SRB
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{
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UCHAR CmdBlock[12];
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struct _SRB *pNextSRB;
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struct _DCB *pSRBDCB;
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PSCSICMD pcmd;
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PSEG pSegmentList;
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ULONG PhysSRB;
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ULONG TotalXferredLen;
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ULONG SGPhysAddr; /*;a segment starting address */
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ULONG SGToBeXferLen; /*; to be xfer length */
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ULONG Segment0[2];
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ULONG Segment1[2];
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SGentry SGsegment[MAX_SG_ENTRY];
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SGentry Segmentx; /* make a one entry of S/G list table */
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PUCHAR pMsgPtr;
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USHORT SRBState;
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USHORT Revxx2; /* ??? */
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UCHAR MsgInBuf[6];
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UCHAR MsgOutBuf[6];
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UCHAR AdaptStatus;
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UCHAR TargetStatus;
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UCHAR MsgCnt;
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UCHAR EndMessage;
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UCHAR TagNumber;
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UCHAR SGcount;
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UCHAR SGIndex;
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UCHAR IORBFlag; /*;81h-Reset, 2-retry */
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UCHAR SRBStatus;
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UCHAR RetryCnt;
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UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */
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/*; b4-settimeout,b5-Residual valid */
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UCHAR ScsiCmdLen;
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UCHAR ScsiPhase;
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UCHAR Reserved3[3]; /*;for dword alignment */
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};
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typedef struct _SRB DC390_SRB, *PSRB;
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/*
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;-----------------------------------------------------------------------
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; Device Control Block
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;-----------------------------------------------------------------------
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*/
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struct _DCB
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{
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struct _DCB *pNextDCB;
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struct _ACB *pDCBACB;
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PSRB pWaitingSRB;
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PSRB pWaitLast;
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PSRB pGoingSRB;
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PSRB pGoingLast;
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PSRB pActiveSRB;
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USHORT GoingSRBCnt;
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USHORT WaitSRBCnt; /* ??? */
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ULONG TagMask;
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USHORT MaxCommand;
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USHORT AdaptIndex; /*; UnitInfo struc start */
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USHORT UnitIndex; /*; nth Unit on this card */
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UCHAR UnitSCSIID; /*; SCSI Target ID (SCSI Only) */
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UCHAR UnitSCSILUN; /*; SCSI Log. Unit (SCSI Only) */
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UCHAR IdentifyMsg;
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UCHAR CtrlR1;
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UCHAR CtrlR3;
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UCHAR CtrlR4;
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UCHAR InqDataBuf[8];
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UCHAR CapacityBuf[8];
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UCHAR DevMode;
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UCHAR AdpMode;
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UCHAR SyncMode; /*; 0:async mode */
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UCHAR NegoPeriod; /*;for nego. */
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UCHAR SyncPeriod; /*;for reg. */
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UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */
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UCHAR UnitCtrlFlag;
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UCHAR DCBFlag;
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UCHAR DevType;
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UCHAR Reserved2[3]; /*;for dword alignment */
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};
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typedef struct _DCB DC390_DCB, *PDCB;
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/*
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;-----------------------------------------------------------------------
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; Adapter Control Block
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;-----------------------------------------------------------------------
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*/
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struct _ACB
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{
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ULONG PhysACB;
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struct _ACB *pNextACB;
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USHORT IOPortBase;
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USHORT Revxx1; /* ??? */
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PDCB pLinkDCB;
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PDCB pDCBRunRobin;
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PDCB pActiveDCB;
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PDCB pDCB_free;
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PSRB pFreeSRB;
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PSRB pTmpSRB;
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USHORT SRBCount;
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USHORT AdapterIndex; /*; nth Adapter this driver */
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USHORT max_id;
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USHORT max_lun;
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SCSILINK ScsiLink;
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UCHAR msgin123[4];
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UCHAR status;
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UCHAR AdaptSCSIID; /*; Adapter SCSI Target ID */
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UCHAR AdaptSCSILUN; /*; Adapter SCSI LUN */
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UCHAR DeviceCnt;
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UCHAR IRQLevel;
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UCHAR TagMaxNum;
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UCHAR ACBFlag;
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UCHAR Gmode2;
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UCHAR LUNchk;
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UCHAR scan_devices;
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UCHAR HostID_Bit;
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UCHAR Reserved1[1]; /*;for dword alignment */
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UCHAR DCBmap[MAX_SCSI_ID];
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DC390_DCB DCB_array[MAX_DEVICES]; /* +74h, Len=3E8 */
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DC390_SRB SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */
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DC390_SRB TmpSRB;
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};
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typedef struct _ACB DC390_ACB, *PACB;
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/*;-----------------------------------------------------------------------*/
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#define BIT31 0x80000000
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#define BIT30 0x40000000
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#define BIT29 0x20000000
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#define BIT28 0x10000000
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#define BIT27 0x08000000
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#define BIT26 0x04000000
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#define BIT25 0x02000000
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#define BIT24 0x01000000
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#define BIT23 0x00800000
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#define BIT22 0x00400000
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#define BIT21 0x00200000
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#define BIT20 0x00100000
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#define BIT19 0x00080000
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#define BIT18 0x00040000
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#define BIT17 0x00020000
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#define BIT16 0x00010000
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#define BIT15 0x00008000
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#define BIT14 0x00004000
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#define BIT13 0x00002000
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#define BIT12 0x00001000
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#define BIT11 0x00000800
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#define BIT10 0x00000400
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#define BIT9 0x00000200
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#define BIT8 0x00000100
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#define BIT7 0x00000080
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#define BIT6 0x00000040
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#define BIT5 0x00000020
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#define BIT4 0x00000010
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#define BIT3 0x00000008
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#define BIT2 0x00000004
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#define BIT1 0x00000002
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#define BIT0 0x00000001
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/*;---UnitCtrlFlag */
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#define UNIT_ALLOCATED BIT0
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#define UNIT_INFO_CHANGED BIT1
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#define FORMATING_MEDIA BIT2
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#define UNIT_RETRY BIT3
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/*;---UnitFlags */
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#define DASD_SUPPORT BIT0
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#define SCSI_SUPPORT BIT1
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#define ASPI_SUPPORT BIT2
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/*;----SRBState machine definition */
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#define SRB_FREE 0
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#define SRB_WAIT BIT0
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#define SRB_READY BIT1
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#define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
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#define SRB_MSGIN BIT3
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#define SRB_MSGIN_MULTI BIT4
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#define SRB_COMMAND BIT5
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#define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
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#define SRB_DISCONNECT BIT7
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#define SRB_DATA_XFER BIT8
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#define SRB_XFERPAD BIT9
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#define SRB_STATUS BIT10
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#define SRB_COMPLETED BIT11
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#define SRB_ABORT_SENT BIT12
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#define DO_SYNC_NEGO BIT13
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#define SRB_UNEXPECT_RESEL BIT14
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/*;---ACBFlag */
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#define RESET_DEV BIT0
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#define RESET_DETECT BIT1
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#define RESET_DONE BIT2
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/*;---DCBFlag */
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#define ABORT_DEV_ BIT0
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/*;---SRBstatus */
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#define SRB_OK BIT0
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#define ABORTION BIT1
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#define OVER_RUN BIT2
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#define UNDER_RUN BIT3
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#define PARITY_ERROR BIT4
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#define SRB_ERROR BIT5
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/*;---SRBFlag */
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#define DATAOUT BIT7
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#define DATAIN BIT6
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#define RESIDUAL_VALID BIT5
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#define ENABLE_TIMER BIT4
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#define RESET_DEV0 BIT2
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#define ABORT_DEV BIT1
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#define AUTO_REQSENSE BIT0
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/*;---Adapter status */
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#define H_STATUS_GOOD 0
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#define H_SEL_TIMEOUT 0x11
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#define H_OVER_UNDER_RUN 0x12
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#define H_UNEXP_BUS_FREE 0x13
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#define H_TARGET_PHASE_F 0x14
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#define H_INVALID_CCB_OP 0x16
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#define H_LINK_CCB_BAD 0x17
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#define H_BAD_TARGET_DIR 0x18
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#define H_DUPLICATE_CCB 0x19
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#define H_BAD_CCB_OR_SG 0x1A
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#define H_ABORT 0x0FF
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/*; SCSI Status byte codes*/
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#define SCSI_STAT_GOOD 0x0 /*; Good status */
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#define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */
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#define SCSI_STAT_CONDMET 0x04 /*; Condition Met */
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#define SCSI_STAT_BUSY 0x08 /*; Target busy status */
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#define SCSI_STAT_INTER 0x10 /*; Intermediate status */
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#define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */
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#define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */
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#define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */
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#define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */
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#define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
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#define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
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#define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
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/*;---Sync_Mode */
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#define SYNC_DISABLE 0
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#define SYNC_ENABLE BIT0
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#define SYNC_NEGO_DONE BIT1
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#define WIDE_ENABLE BIT2
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#define WIDE_NEGO_DONE BIT3
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#define EN_TAG_QUEUING BIT4
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#define EN_ATN_STOP BIT5
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#define SYNC_NEGO_OFFSET 15
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/*;---SCSI bus phase*/
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#define SCSI_DATA_OUT_ 0
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#define SCSI_DATA_IN_ 1
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#define SCSI_COMMAND 2
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#define SCSI_STATUS_ 3
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#define SCSI_NOP0 4
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#define SCSI_NOP1 5
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#define SCSI_MSG_OUT 6
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#define SCSI_MSG_IN 7
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/*;----SCSI MSG BYTE*/
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#define MSG_COMPLETE 0x00
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#define MSG_EXTENDED 0x01
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#define MSG_SAVE_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INITIATOR_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT_ 0x07
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#define MSG_NOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_LINK_CMD_COMPL 0x0A
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#define MSG_LINK_CMD_COMPL_FLG 0x0B
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#define MSG_BUS_RESET 0x0C
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#define MSG_ABORT_TAG 0x0D
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#define MSG_SIMPLE_QTAG 0x20
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#define MSG_HEAD_QTAG 0x21
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#define MSG_ORDER_QTAG 0x22
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#define MSG_IDENTIFY 0x80
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#define MSG_HOST_ID 0x0C0
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/*;----SCSI STATUS BYTE*/
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#define STATUS_GOOD 0x00
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#define CHECK_CONDITION_ 0x02
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#define STATUS_BUSY 0x08
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#define STATUS_INTERMEDIATE 0x10
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#define RESERVE_CONFLICT 0x18
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/* cmd->result */
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#define STATUS_MASK_ 0xFF
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#define MSG_MASK 0xFF00
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#define RETURN_MASK 0xFF0000
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/*
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** Inquiry Data format
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*/
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typedef struct _SCSIInqData { /* INQ */
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UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/
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UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */
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UCHAR Vers; /* ISO, ECMA, & ANSI versions */
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UCHAR RDF; /* AEN, TRMIOP, & response data format*/
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UCHAR AddLen; /* length of additional data */
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UCHAR Res1; /* reserved */
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UCHAR Res2; /* reserved */
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UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
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UCHAR VendorID[8]; /* Vendor Identification */
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UCHAR ProductID[16]; /* Product Identification */
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UCHAR ProductRev[4]; /* Product Revision */
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} SCSI_INQDATA, *PSCSI_INQDATA;
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||||
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/* Inquiry byte 0 masks */
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||||
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#define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
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#define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
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||||
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/* Inquiry byte 1 mask */
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#define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
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||||
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||||
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/* Peripheral Device Type definitions */
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||||
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||||
#define SCSI_DASD 0x00 /* Direct-access Device */
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#define SCSI_SEQACESS 0x01 /* Sequential-access device */
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#define SCSI_PRINTER 0x02 /* Printer device */
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#define SCSI_PROCESSOR 0x03 /* Processor device */
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#define SCSI_WRITEONCE 0x04 /* Write-once device */
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#define SCSI_CDROM 0x05 /* CD-ROM device */
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||||
#define SCSI_SCANNER 0x06 /* Scanner device */
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||||
#define SCSI_OPTICAL 0x07 /* Optical memory device */
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#define SCSI_MEDCHGR 0x08 /* Medium changer device */
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||||
#define SCSI_COMM 0x09 /* Communications device */
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||||
#define SCSI_NODEV 0x1F /* Unknown or no device type */
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||||
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||||
/*
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** Inquiry flag definitions (Inq data byte 7)
|
||||
*/
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||||
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||||
#define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
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#define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
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#define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
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#define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
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#define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
|
||||
#define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
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||||
#define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
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/*
|
||||
;==========================================================
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||||
; EEPROM byte offset
|
||||
;==========================================================
|
||||
*/
|
||||
typedef struct _EEprom
|
||||
{
|
||||
UCHAR EE_MODE1;
|
||||
UCHAR EE_SPEED;
|
||||
UCHAR xx1;
|
||||
UCHAR xx2;
|
||||
} EEprom, *PEEprom;
|
||||
|
||||
#define EE_ADAPT_SCSI_ID 64
|
||||
#define EE_MODE2 65
|
||||
#define EE_DELAY 66
|
||||
#define EE_TAG_CMD_NUM 67
|
||||
|
||||
/*; EE_MODE1 bits definition*/
|
||||
#define PARITY_CHK_ BIT0
|
||||
#define SYNC_NEGO_ BIT1
|
||||
#define EN_DISCONNECT_ BIT2
|
||||
#define SEND_START_ BIT3
|
||||
#define TAG_QUEUING_ BIT4
|
||||
|
||||
/*; EE_MODE2 bits definition*/
|
||||
#define MORE2_DRV BIT0
|
||||
#define GREATER_1G BIT1
|
||||
#define RST_SCSI_BUS BIT2
|
||||
#define ACTIVE_NEGATION BIT3
|
||||
#define NO_SEEK BIT4
|
||||
#define LUN_CHECK BIT5
|
||||
|
||||
#define ENABLE_CE 1
|
||||
#define DISABLE_CE 0
|
||||
#define EEPROM_READ 0x80
|
||||
|
||||
/*
|
||||
;==========================================================
|
||||
; AMD 53C974 Registers bit Definition
|
||||
;==========================================================
|
||||
*/
|
||||
/*
|
||||
;====================
|
||||
; SCSI Register
|
||||
;====================
|
||||
*/
|
||||
|
||||
/*; Command Reg.(+0CH) */
|
||||
#define DMA_COMMAND BIT7
|
||||
#define NOP_CMD 0
|
||||
#define CLEAR_FIFO_CMD 1
|
||||
#define RST_DEVICE_CMD 2
|
||||
#define RST_SCSI_BUS_CMD 3
|
||||
#define INFO_XFER_CMD 0x10
|
||||
#define INITIATOR_CMD_CMPLTE 0x11
|
||||
#define MSG_ACCEPTED_CMD 0x12
|
||||
#define XFER_PAD_BYTE 0x18
|
||||
#define SET_ATN_CMD 0x1A
|
||||
#define RESET_ATN_CMD 0x1B
|
||||
#define SELECT_W_ATN 0x42
|
||||
#define SEL_W_ATN_STOP 0x43
|
||||
#define EN_SEL_RESEL 0x44
|
||||
#define SEL_W_ATN2 0x46
|
||||
#define DATA_XFER_CMD INFO_XFER_CMD
|
||||
|
||||
|
||||
/*; SCSI Status Reg.(+10H) */
|
||||
#define INTERRUPT BIT7
|
||||
#define ILLEGAL_OP_ERR BIT6
|
||||
#define PARITY_ERR BIT5
|
||||
#define COUNT_2_ZERO BIT4
|
||||
#define GROUP_CODE_VALID BIT3
|
||||
#define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
|
||||
|
||||
/*; Interrupt Status Reg.(+14H) */
|
||||
#define SCSI_RESET_ BIT7
|
||||
#define INVALID_CMD BIT6
|
||||
#define DISCONNECTED BIT5
|
||||
#define SERVICE_REQUEST BIT4
|
||||
#define SUCCESSFUL_OP BIT3
|
||||
#define RESELECTED BIT2
|
||||
#define SEL_ATTENTION BIT1
|
||||
#define SELECTED BIT0
|
||||
|
||||
/*; Internal State Reg.(+18H) */
|
||||
#define SYNC_OFFSET_FLAG BIT3
|
||||
#define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
|
||||
|
||||
/*; Clock Factor Reg.(+24H) */
|
||||
#define CLK_FREQ_40MHZ 0
|
||||
#define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
|
||||
#define CLK_FREQ_30MHZ (BIT2+BIT1)
|
||||
#define CLK_FREQ_25MHZ (BIT2+BIT0)
|
||||
#define CLK_FREQ_20MHZ BIT2
|
||||
#define CLK_FREQ_15MHZ (BIT1+BIT0)
|
||||
#define CLK_FREQ_10MHZ BIT1
|
||||
|
||||
/*; Control Reg. 1(+20H) */
|
||||
#define EXTENDED_TIMING BIT7
|
||||
#define DIS_INT_ON_SCSI_RST BIT6
|
||||
#define PARITY_ERR_REPO BIT4
|
||||
#define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0)
|
||||
|
||||
/*; Control Reg. 2(+2CH) */
|
||||
#define EN_FEATURE BIT6
|
||||
#define EN_SCSI2_CMD BIT3
|
||||
|
||||
/*; Control Reg. 3(+30H) */
|
||||
#define ID_MSG_CHECK BIT7
|
||||
#define EN_QTAG_MSG BIT6
|
||||
#define EN_GRP2_CMD BIT5
|
||||
#define FAST_SCSI BIT4 /* ;10MB/SEC */
|
||||
#define FAST_CLK BIT3 /* ;25 - 40 MHZ */
|
||||
|
||||
/*; Control Reg. 4(+34H) */
|
||||
#define EATER_12NS 0
|
||||
#define EATER_25NS BIT7
|
||||
#define EATER_35NS BIT6
|
||||
#define EATER_0NS (BIT7+BIT6)
|
||||
#define NEGATE_REQACKDATA BIT2
|
||||
#define NEGATE_REQACK BIT3
|
||||
/*
|
||||
;====================
|
||||
; DMA Register
|
||||
;====================
|
||||
*/
|
||||
/*; DMA Command Reg.(+40H) */
|
||||
#define READ_DIRECTION BIT7
|
||||
#define WRITE_DIRECTION 0
|
||||
#define EN_DMA_INT BIT6
|
||||
#define MAP_TO_MDL BIT5
|
||||
#define DIAGNOSTIC BIT4
|
||||
#define DMA_IDLE_CMD 0
|
||||
#define DMA_BLAST_CMD BIT0
|
||||
#define DMA_ABORT_CMD BIT1
|
||||
#define DMA_START_CMD (BIT1+BIT0)
|
||||
|
||||
/*; DMA Status Reg.(+54H) */
|
||||
#define PCI_MS_ABORT BIT6
|
||||
#define BLAST_COMPLETE BIT5
|
||||
#define SCSI_INTERRUPT BIT4
|
||||
#define DMA_XFER_DONE BIT3
|
||||
#define DMA_XFER_ABORT BIT2
|
||||
#define DMA_XFER_ERROR BIT1
|
||||
#define POWER_DOWN BIT0
|
||||
|
||||
/*
|
||||
; DMA SCSI Bus and Ctrl.(+70H)
|
||||
;EN_INT_ON_PCI_ABORT
|
||||
*/
|
||||
|
||||
/*
|
||||
;==========================================================
|
||||
; SCSI Chip register address offset
|
||||
;==========================================================
|
||||
*/
|
||||
#define CtcReg_Low 0x00
|
||||
#define CtcReg_Mid 0x04
|
||||
#define ScsiFifo 0x08
|
||||
#define ScsiCmd 0x0C
|
||||
#define Scsi_Status 0x10
|
||||
#define INT_Status 0x14
|
||||
#define Sync_Period 0x18
|
||||
#define Sync_Offset 0x1C
|
||||
#define CtrlReg1 0x20
|
||||
#define Clk_Factor 0x24
|
||||
#define CtrlReg2 0x2C
|
||||
#define CtrlReg3 0x30
|
||||
#define CtrlReg4 0x34
|
||||
#define CtcReg_High 0x38
|
||||
#define DMA_Cmd 0x40
|
||||
#define DMA_XferCnt 0x44
|
||||
#define DMA_XferAddr 0x48
|
||||
#define DMA_Wk_ByteCntr 0x4C
|
||||
#define DMA_Wk_AddrCntr 0x50
|
||||
#define DMA_Status 0x54
|
||||
#define DMA_MDL_Addr 0x58
|
||||
#define DMA_Wk_MDL_Cntr 0x5C
|
||||
#define DMA_ScsiBusCtrl 0x70
|
||||
|
||||
#define StcReg_Low CtcReg_Low
|
||||
#define StcReg_Mid CtcReg_Mid
|
||||
#define Scsi_Dest_ID Scsi_Status
|
||||
#define Scsi_TimeOut INT_Status
|
||||
#define Intern_State Sync_Period
|
||||
#define Current_Fifo Sync_Offset
|
||||
#define StcReg_High CtcReg_High
|
||||
|
||||
#define am_target Scsi_Status
|
||||
#define am_timeout INT_Status
|
||||
#define am_seq_step Sync_Period
|
||||
#define am_fifo_count Sync_Offset
|
||||
|
||||
|
||||
#define DC390_read8(address) \
|
||||
inb(DC390_ioport + (address)))
|
||||
|
||||
#define DC390_read16(address) \
|
||||
inw(DC390_ioport + (address)))
|
||||
|
||||
#define DC390_read32(address) \
|
||||
inl(DC390_ioport + (address)))
|
||||
|
||||
#define DC390_write8(address,value) \
|
||||
outb((value), DC390_ioport + (address)))
|
||||
|
||||
#define DC390_write16(address,value) \
|
||||
outw((value), DC390_ioport + (address)))
|
||||
|
||||
#define DC390_write32(address,value) \
|
||||
outl((value), DC390_ioport + (address)))
|
||||
|
||||
|
||||
/* Configuration method #1 */
|
||||
#define PCI_CFG1_ADDRESS_REG 0xcf8
|
||||
#define PCI_CFG1_DATA_REG 0xcfc
|
||||
#define PCI_CFG1_ENABLE 0x80000000
|
||||
#define PCI_CFG1_TUPPLE(bus, device, function, register) \
|
||||
(PCI_CFG1_ENABLE | (((bus) << 16) & 0xff0000) | \
|
||||
(((device) << 11) & 0xf800) | (((function) << 8) & 0x700)| \
|
||||
(((register) << 2) & 0xfc))
|
||||
|
||||
/* Configuration method #2 */
|
||||
#define PCI_CFG2_ENABLE_REG 0xcf8
|
||||
#define PCI_CFG2_FORWARD_REG 0xcfa
|
||||
#define PCI_CFG2_ENABLE 0x0f0
|
||||
#define PCI_CFG2_TUPPLE(function) \
|
||||
(PCI_CFG2_ENABLE | (((function) << 1) & 0xe))
|
||||
|
||||
|
||||
#endif /* TEK390_H */
|
||||
Loading…
Reference in New Issue
Block a user