Extend the support for PCI-e memory mapped configuration space access:
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the rest of the kernel. It now also accepts parameters via function arguments rather than global variables. - Add a notion of minimum and maximum bus numbers and reject requests for an out of range bus. - Add more range checks on slot/func/reg/bytes parameters to the cfg reg read/write routines. Don't panic on any invalid parameters, just fail the request (writes do nothing, reads return -1). This matches the behavior of the other cfg mechanisms. - Port the memory mapped configuration space access to amd64. On amd64 we simply use the direct map (via pmap_mapdev()) for the memory mapped window. - During acpi_attach() just after loading the ACPI tables, check for a MCFG table. If it exists, call pciereg_cfgopen() on each subtable (memory mapped window). For now we only support windows for domain 0 that start with bus 0. This removes the need for more chipset-specific quirks in the MD code. - Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets since these machines should all have MCFG tables via ACPI. - Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen() earlier. MFC after: 2 weeks
This commit is contained in:
John Baldwin
parent
643cd4ffe7
commit
d320e05ca5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=181987
@ -37,6 +37,7 @@
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#define CONF1_ENABLE_MSK1 0x80000001ul
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#define CONF1_ENABLE_RES1 0x80000000ul
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int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
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int pci_cfgregopen(void);
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u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
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void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
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@ -36,11 +36,26 @@ __FBSDID("$FreeBSD$");
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#include <sys/mutex.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pci_cfgreg.h>
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enum {
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CFGMECH_NONE = 0,
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CFGMECH_1,
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CFGMECH_PCIE,
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};
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static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
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unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
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unsigned reg, int data, unsigned bytes);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int cfgmech;
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static vm_offset_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static struct mtx pcicfg_mtx;
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/*
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@ -49,12 +64,42 @@ static struct mtx pcicfg_mtx;
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int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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uint64_t pciebar;
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uint16_t did, vid;
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if (opened)
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if (cfgmech != CFGMECH_NONE)
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return (1);
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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opened = 1;
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cfgmech = CFGMECH_1;
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/*
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* Grope around in the PCI config space to see if this is a
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* chipset that is capable of doing memory-mapped config cycles.
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* This also implies that it can do PCIe extended config cycles.
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*/
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/* Check for supported chipsets */
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vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
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did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
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switch (vid) {
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case 0x8086:
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switch (did) {
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case 0x3590:
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case 0x3592:
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/* Intel 7520 or 7320 */
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pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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case 0x2580:
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case 0x2584:
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case 0x2590:
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/* Intel 915, 925, or 915GM */
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pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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}
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}
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return (1);
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}
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@ -130,6 +175,11 @@ pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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int data = -1;
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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data = pciereg_cfgread(bus, slot, func, reg, bytes);
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return (data);
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -155,6 +205,11 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -173,3 +228,82 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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{
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if (minbus != 0)
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return (0);
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if (bootverbose)
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printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
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base);
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/* XXX: We should make sure this really fits into the direct map. */
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pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
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pcie_minbus = minbus;
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pcie_maxbus = maxbus;
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cfgmech = CFGMECH_PCIE;
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return (1);
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}
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#define PCIE_VADDR(base, reg, bus, slot, func) \
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((base) + \
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((((bus) & 0xff) << 20) | \
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(((slot) & 0x1f) << 15) | \
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(((func) & 0x7) << 12) | \
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((reg) & 0xfff)))
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static int
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pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
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unsigned bytes)
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{
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volatile vm_offset_t va;
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int data = -1;
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
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func > PCI_FUNCMAX || reg >= 0x1000)
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return (-1);
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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switch (bytes) {
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case 4:
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data = *(volatile uint32_t *)(va);
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break;
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case 2:
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data = *(volatile uint16_t *)(va);
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break;
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case 1:
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data = *(volatile uint8_t *)(va);
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break;
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}
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return (data);
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}
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static void
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pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
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unsigned bytes)
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{
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volatile vm_offset_t va;
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
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func > PCI_FUNCMAX || reg >= 0x1000)
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return;
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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switch (bytes) {
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case 4:
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*(volatile uint32_t *)(va) = data;
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break;
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case 2:
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*(volatile uint16_t *)(va) = data;
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break;
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case 1:
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*(volatile uint8_t *)(va) = data;
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break;
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}
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}
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@ -48,6 +48,9 @@ __FBSDID("$FreeBSD$");
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#include <sys/sbuf.h>
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#include <sys/smp.h>
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#if defined(__i386__) || defined(__amd64__)
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#include <machine/pci_cfgreg.h>
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#endif
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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@ -152,6 +155,9 @@ static int acpi_child_location_str_method(device_t acdev, device_t child,
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char *buf, size_t buflen);
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static int acpi_child_pnpinfo_str_method(device_t acdev, device_t child,
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char *buf, size_t buflen);
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#if defined(__i386__) || defined(__amd64__)
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static void acpi_enable_pcie(void);
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#endif
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static device_method_t acpi_methods[] = {
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/* Device interface */
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@ -448,6 +454,11 @@ acpi_attach(device_t dev)
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goto out;
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}
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#if defined(__i386__) || defined(__amd64__)
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/* Handle MCFG table if present. */
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acpi_enable_pcie();
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#endif
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/* Install the default address space handlers. */
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status = AcpiInstallAddressSpaceHandler(ACPI_ROOT_OBJECT,
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ACPI_ADR_SPACE_SYSTEM_MEMORY, ACPI_DEFAULT_HANDLER, NULL, NULL);
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@ -1466,6 +1477,36 @@ acpi_isa_pnp_probe(device_t bus, device_t child, struct isa_pnp_id *ids)
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return_VALUE (result);
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}
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#if defined(__i386__) || defined(__amd64__)
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/*
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* Look for a MCFG table. If it is present, use the settings for
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* domain (segment) 0 to setup PCI config space access via the memory
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* map.
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*/
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static void
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acpi_enable_pcie(void)
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{
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ACPI_TABLE_HEADER *hdr;
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ACPI_MCFG_ALLOCATION *alloc, *end;
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ACPI_STATUS status;
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status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
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if (ACPI_FAILURE(status))
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return;
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end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
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alloc = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
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while (alloc < end) {
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if (alloc->PciSegment == 0) {
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pcie_cfgregopen(alloc->Address, alloc->StartBusNumber,
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alloc->EndBusNumber);
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return;
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}
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alloc++;
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}
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}
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#endif
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/*
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* Scan all of the ACPI namespace and attach child devices.
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*
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@ -43,6 +43,7 @@
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#define CONF2_ENABLE_CHK 0x0e
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#define CONF2_ENABLE_RES 0x0e
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int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
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int pci_cfgregopen(void);
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u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
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void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
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@ -75,7 +75,8 @@ enum {
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};
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static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
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static uint64_t pciebar;
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static uint64_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static int cfgmech;
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static int devmax;
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static struct mtx pcicfg_mtx;
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@ -84,13 +85,11 @@ static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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#ifndef XEN
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static int pcireg_cfgopen(void);
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static int pciereg_cfgopen(void);
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#endif
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static int pciereg_cfgread(int bus, int slot, int func, int reg,
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int bytes);
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static void pciereg_cfgwrite(int bus, int slot, int func, int reg,
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int data, int bytes);
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static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
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unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
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unsigned reg, int data, unsigned bytes);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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@ -140,14 +139,15 @@ pci_cfgregopen(void)
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return (0);
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#else
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static int opened = 0;
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uint64_t pciebar;
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u_int16_t vid, did;
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u_int16_t v;
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if (opened)
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return(1);
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return (1);
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if (pcireg_cfgopen() == 0)
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return(0);
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if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0)
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return (0);
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v = pcibios_get_version();
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if (v > 0)
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@ -160,6 +160,9 @@ pci_cfgregopen(void)
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if (v >= 0x0210)
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pci_pir_open();
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if (cfgmech == CFGMECH_PCIE)
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return (1);
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/*
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* Grope around in the PCI config space to see if this is a
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* chipset that is capable of doing memory-mapped config cycles.
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@ -176,22 +179,15 @@ pci_cfgregopen(void)
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case 0x3592:
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/* Intel 7520 or 7320 */
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pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
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pciereg_cfgopen();
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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case 0x2580:
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case 0x2584:
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case 0x2590:
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/* Intel 915, 925, or 915GM */
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pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
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pciereg_cfgopen();
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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case 0x25d0:
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case 0x25d4:
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case 0x25d8:
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/* Intel 5000Z/V/P */
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pciebar = pci_cfgregread(0, 16, 0, 0x64, 4) << 16;
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pciereg_cfgopen();
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break;
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}
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}
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@ -504,8 +500,8 @@ pcireg_cfgopen(void)
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return (cfgmech);
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}
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static int
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pciereg_cfgopen(void)
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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{
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struct pcie_cfg_list *pcielist;
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struct pcie_cfg_elem *pcie_array, *elem;
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@ -515,20 +511,22 @@ pciereg_cfgopen(void)
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vm_offset_t va;
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int i;
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if (minbus != 0)
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return (0);
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#ifndef PAE
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if (pciebar >= 0x100000000) {
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if (base >= 0x100000000) {
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if (bootverbose)
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printf(
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"PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
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(uintmax_t)pciebar);
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pciebar = 0;
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(uintmax_t)base);
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return (0);
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}
|
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#endif
|
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|
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if (bootverbose)
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printf("Setting up PCIe mappings for BAR 0x%jx\n",
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(uintmax_t)pciebar);
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printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
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(uintmax_t)base);
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#ifdef SMP
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SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
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@ -560,7 +558,9 @@ pciereg_cfgopen(void)
|
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}
|
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}
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|
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pcie_base = base;
|
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pcie_minbus = minbus;
|
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pcie_maxbus = maxbus;
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cfgmech = CFGMECH_PCIE;
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devmax = 32;
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return (1);
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@ -610,15 +610,20 @@ pciereg_findelem(vm_paddr_t papage)
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}
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static int
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pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
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pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
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unsigned bytes)
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{
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struct pcie_cfg_elem *elem;
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volatile vm_offset_t va;
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vm_paddr_t pa, papage;
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int data;
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int data = -1;
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
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func > PCI_FUNCMAX || reg >= 0x1000 || bytes > 4 || bytes == 3)
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return (-1);
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|
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critical_enter();
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pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
|
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pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
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papage = pa & ~PAGE_MASK;
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elem = pciereg_findelem(papage);
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va = elem->vapage | (pa & PAGE_MASK);
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@ -633,8 +638,6 @@ pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
|
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case 1:
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data = *(volatile uint8_t *)(va);
|
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break;
|
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default:
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panic("pciereg_cfgread: invalid width");
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}
|
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|
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critical_exit();
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@ -642,14 +645,19 @@ pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
|
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}
|
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|
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static void
|
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pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
|
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pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
|
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unsigned bytes)
|
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{
|
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struct pcie_cfg_elem *elem;
|
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volatile vm_offset_t va;
|
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vm_paddr_t pa, papage;
|
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|
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
|
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func > PCI_FUNCMAX || reg >= 0x1000)
|
||||
return;
|
||||
|
||||
critical_enter();
|
||||
pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
|
||||
pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
|
||||
papage = pa & ~PAGE_MASK;
|
||||
elem = pciereg_findelem(papage);
|
||||
va = elem->vapage | (pa & PAGE_MASK);
|
||||
@ -664,8 +672,6 @@ pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
|
||||
case 1:
|
||||
*(volatile uint8_t *)(va) = data;
|
||||
break;
|
||||
default:
|
||||
panic("pciereg_cfgwrite: invalid width");
|
||||
}
|
||||
|
||||
critical_exit();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user