AHCI: Fix AHCI driver for ARM.
On ARM, we must ensure proper interdevice write ordering. The AHCI interrupt status register must be updated in HW before registers in interrupt controller. Unfortunately, only way how we can do it is readback. Discussed with: mav Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D4240
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=291444
@ -483,6 +483,7 @@ ahci_intr(void *data)
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/* AHCI declares level triggered IS. */
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if (!(ctlr->quirks & AHCI_Q_EDGEIS))
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ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
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ATA_RBL(ctlr->r_mem, AHCI_IS);
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}
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/*
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@ -501,6 +502,7 @@ ahci_intr_one(void *data)
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ctlr->interrupt[unit].function(arg);
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/* AHCI declares level triggered IS. */
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ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
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ATA_RBL(ctlr->r_mem, AHCI_IS);
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}
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static void
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@ -516,6 +518,7 @@ ahci_intr_one_edge(void *data)
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ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
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if ((arg = ctlr->interrupt[unit].argument))
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ctlr->interrupt[unit].function(arg);
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ATA_RBL(ctlr->r_mem, AHCI_IS);
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}
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struct resource *
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@ -562,6 +562,20 @@ enum ahci_err_type {
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#define ATA_OUTSL_STRM(res, offset, addr, count) \
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bus_write_multi_stream_4((res), (offset), (addr), (count))
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/*
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* On some platforms, we must ensure proper interdevice write ordering.
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* The AHCI interrupt status register must be updated in HW before
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* registers in interrupt controller.
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* Unfortunately, only way how we can do it is readback.
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*
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* Currently, only ARM is known to have this issue.
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*/
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#if defined(__arm__)
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#define ATA_RBL(res, offset) \
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bus_read_4((res), (offset))
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#else
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#define ATA_RBL(res, offset)
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#endif
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#define AHCI_Q_NOFORCE 0x00000001
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#define AHCI_Q_NOPMP 0x00000002
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