dts: Update the Device Tree Sources to Linux 4.13
This commit is contained in:
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2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=324818 svn path=/vendor/device-tree/4.13/; revision=324819; tag=vendor/device-tree/4.13
4
.gitignore
vendored
4
.gitignore
vendored
@ -1,4 +0,0 @@
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.*
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!.gitignore
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*.dtb
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39
Bindings/arm/actions.txt
Normal file
39
Bindings/arm/actions.txt
Normal file
@ -0,0 +1,39 @@
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Actions Semi platforms device tree bindings
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-------------------------------------------
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S500 SoC
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========
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Required root node properties:
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- compatible : must contain "actions,s500"
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Modules:
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Root node property compatible must contain, depending on module:
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- LeMaker Guitar: "lemaker,guitar"
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Boards:
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Root node property compatible must contain, depending on board:
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- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
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S900 SoC
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========
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Required root node properties:
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- compatible : must contain "actions,s900"
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Boards:
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Root node property compatible must contain, depending on board:
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- uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"
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@ -29,26 +29,35 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,s912", "amlogic,meson-gxm";
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Board compatible values:
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Board compatible values (alphabetically, grouped by SoC):
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- "geniatech,atv1200" (Meson6)
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- "minix,neo-x8" (Meson8)
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- "tronfy,mxq" (Meson8b)
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- "hardkernel,odroid-c1" (Meson8b)
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- "tronfy,mxq" (Meson8b)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "friendlyarm,nanopi-k2" (Meson gxbb)
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
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- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "wetek,hub" (Meson gxbb)
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- "wetek,play2" (Meson gxbb)
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- "amlogic,p212" (Meson gxl s905x)
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- "hwacom,amazetv" (Meson gxl s905x)
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- "khadas,vim" (Meson gxl s905x)
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- "libretech,cc" (Meson gxl s905x)
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- "amlogic,p230" (Meson gxl s905d)
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- "amlogic,p231" (Meson gxl s905d)
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- "hwacom,amazetv" (Meson gxl s905x)
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- "amlogic,q200" (Meson gxm s912)
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- "amlogic,q201" (Meson gxm s912)
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- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
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- "kingnovel,r-box-pro" (Meson gxm S912)
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- "nexbox,a1" (Meson gxm s912)
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@ -41,6 +41,36 @@ compatible: must be one of:
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- "atmel,sama5d43"
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- "atmel,sama5d44"
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* "atmel,samv7" for MCUs using a Cortex-M7, shall be extended with the specific
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SoC family:
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o "atmel,sams70" shall be extended with the specific MCU compatible:
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- "atmel,sams70j19"
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- "atmel,sams70j20"
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- "atmel,sams70j21"
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- "atmel,sams70n19"
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- "atmel,sams70n20"
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- "atmel,sams70n21"
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- "atmel,sams70q19"
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- "atmel,sams70q20"
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- "atmel,sams70q21"
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o "atmel,samv70" shall be extended with the specific MCU compatible:
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- "atmel,samv70j19"
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- "atmel,samv70j20"
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- "atmel,samv70n19"
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- "atmel,samv70n20"
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- "atmel,samv70q19"
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- "atmel,samv70q20"
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o "atmel,samv71" shall be extended with the specific MCU compatible:
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- "atmel,samv71j19"
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- "atmel,samv71j20"
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- "atmel,samv71j21"
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- "atmel,samv71n19"
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- "atmel,samv71n20"
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- "atmel,samv71n21"
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- "atmel,samv71q19"
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- "atmel,samv71q20"
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- "atmel,samv71q21"
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Chipid required properties:
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- compatible: Should be "atmel,sama5d2-chipid"
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- reg : Should contain registers location and length
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12
Bindings/arm/bcm/brcm,stingray.txt
Normal file
12
Bindings/arm/bcm/brcm,stingray.txt
Normal file
@ -0,0 +1,12 @@
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Broadcom Stingray device tree bindings
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------------------------------------------------
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Boards with Stingray shall have the following properties:
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Required root node property:
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Stingray Combo SVK board
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compatible = "brcm,bcm958742k", "brcm,stingray";
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Stingray SST100 board
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compatible = "brcm,bcm958742t", "brcm,stingray";
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@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register
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space and multiple sets of interface control registers, one per slave
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interface.
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Bindings for the CCI node follow the ePAPR standard, available from:
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www.power.org/documentation/epapr-version-1-1/
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with the addition of the bindings described in this document which are
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specific to ARM.
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* CCI interconnect node
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Description: Describes a CCI cache coherent Interconnect component
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@ -50,10 +43,10 @@ specific to ARM.
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as a tuple of cells, containing child address,
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parent address and the size of the region in the
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child address space.
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Definition: A standard property. Follow rules in the ePAPR for
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hierarchical bus addressing. CCI interfaces
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addresses refer to the parent node addressing
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scheme to declare their register bases.
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Definition: A standard property. Follow rules in the Devicetree
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Specification for hierarchical bus addressing. CCI
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interfaces addresses refer to the parent node
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addressing scheme to declare their register bases.
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CCI interconnect node can define the following child nodes:
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@ -3,6 +3,7 @@
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Required properties:
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- compatible: (standard compatible string) should be one of:
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"arm,ccn-502"
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"arm,ccn-504"
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"arm,ccn-508"
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49
Bindings/arm/coresight-cpu-debug.txt
Normal file
49
Bindings/arm/coresight-cpu-debug.txt
Normal file
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* CoreSight CPU Debug Component:
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CoreSight CPU debug component are compliant with the ARMv8 architecture
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reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
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external debug module is mainly used for two modes: self-hosted debug and
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external debug, and it can be accessed from mmio region from Coresight
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and eventually the debug module connects with CPU for debugging. And the
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debug module provides sample-based profiling extension, which can be used
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to sample CPU program counter, secure state and exception level, etc;
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usually every CPU has one dedicated debug module to be connected.
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Required properties:
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- compatible : should be "arm,coresight-cpu-debug"; supplemented with
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"arm,primecell" since this driver is using the AMBA bus
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interface.
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- reg : physical base address and length of the register set.
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- clocks : the clock associated to this component.
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- clock-names : the name of the clock referenced by the code. Since we are
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using the AMBA framework, the name of the clock providing
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the interconnect should be "apb_pclk" and the clock is
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mandatory. The interface between the debug logic and the
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processor core is clocked by the internal CPU clock, so it
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is enabled with CPU clock by default.
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- cpu : the CPU phandle the debug module is affined to. When omitted
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the module is considered to belong to CPU0.
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Optional properties:
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- power-domains: a phandle to the debug power domain. We use "power-domains"
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binding to turn on the debug logic if it has own dedicated
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power domain and if necessary to use "cpuidle.off=1" or
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"nohlt" in the kernel command line or sysfs node to
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constrain idle states to ensure registers in the CPU power
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domain are accessible.
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Example:
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debug@f6590000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0 0xf6590000 0 0x1000>;
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clocks = <&sys_ctrl HI6220_DAPB_CLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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};
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@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
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Bindings for CPU nodes follow the Devicetree Specification, available from:
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https://www.power.org/documentation/epapr-version-1-1/
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https://www.devicetree.org/specifications/
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with updates for 32-bit and 64-bit ARM systems provided in this document.
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@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in this document.
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Convention used in this document
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================================
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This document follows the conventions described in the ePAPR v1.1, with
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the addition:
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This document follows the conventions described in the Devicetree
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Specification, with the addition:
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- square brackets define bitfields, eg reg[7:0] value of the bitfield in
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the reg property contained in bits 7 down to 0
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@ -26,8 +26,9 @@ the addition:
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cpus and cpu node bindings definition
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=====================================
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The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
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nodes to be present and contain the properties described below.
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The ARM architecture, in accordance with the Devicetree Specification,
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requires the cpus and cpu nodes to be present and contain the properties
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described below.
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- cpus node
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@ -193,6 +194,7 @@ nodes to be present and contain the properties described below.
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"spin-table"
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# On ARM 32-bit systems this property is optional and
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can be one of:
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"actions,s500-smp"
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"arm,realview-smp"
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@ -249,7 +251,7 @@ nodes to be present and contain the properties described below.
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Usage: Optional
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Value type: <u32>
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Definition:
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# u32 value representing CPU capacity [3] in
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# u32 value representing CPU capacity [4] in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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@ -476,5 +478,5 @@ cpus {
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[2] arm/msm/qcom,kpss-acc.txt
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[3] ARM Linux kernel documentation - idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.txt
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[3] ARM Linux kernel documentation - cpu capacity bindings
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[4] ARM Linux kernel documentation - cpu capacity bindings
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Documentation/devicetree/bindings/arm/cpu-capacity.txt
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@ -24,6 +24,19 @@ Required nodes:
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global control registers, with the compatible string
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"cortina,gemini-syscon", "syscon";
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Required properties on the syscon:
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- reg: syscon register location and size.
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- #clock-cells: should be set to <1> - the system controller is also a
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clock provider.
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- #reset-cells: should be set to <1> - the system controller is also a
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reset line provider.
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The clock sources have shorthand defines in the include file:
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<dt-bindings/clock/cortina,gemini-clock.h>
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The reset lines have shorthand defines in the include file:
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<dt-bindings/reset/cortina,gemini-reset.h>
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- timer: the soc bus node must have a timer node pointing to the SoC timer
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block, with the compatible string "cortina,gemini-timer"
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See: clocksource/cortina,gemini-timer.txt
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@ -56,12 +69,15 @@ Example:
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon", "syscon";
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reg = <0x40000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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clock-frequency = <48000000>;
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resets = <&syscon GEMINI_RESET_UART>;
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clocks = <&syscon GEMINI_CLK_UART>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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};
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@ -73,12 +89,18 @@ Example:
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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resets = <&syscon GEMINI_RESET_TIMER>;
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/* APB clock or RTC clock */
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clocks = <&syscon GEMINI_CLK_APB>,
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<&syscon GEMINI_CLK_RTC>;
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clock-names = "PCLK", "EXTCLK";
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syscon = <&syscon>;
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};
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intcon: interrupt-controller@48000000 {
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compatible = "cortina,gemini-interrupt-controller";
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reg = <0x48000000 0x1000>;
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resets = <&syscon GEMINI_RESET_INTCON0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -4,6 +4,10 @@ Hi3660 SoC
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Required root node properties:
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- compatible = "hisilicon,hi3660";
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HiKey960 Board
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Required root node properties:
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- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
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Hi3798cv200 SoC
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Required root node properties:
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- compatible = "hisilicon,hi3798cv200";
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|
@ -695,5 +695,5 @@ cpus {
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[4] ARM Architecture Reference Manuals
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http://infocenter.arm.com/help/index.jsp
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[5] ePAPR standard
|
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https://www.power.org/documentation/epapr-version-1-1/
|
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[5] Devicetree Specification
|
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https://www.devicetree.org/specifications/
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|
@ -37,3 +37,6 @@ Boards:
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||||
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||||
- K2G EVM
|
||||
compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
|
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||||
- K2G Industrial Communication Engine EVM
|
||||
compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone"
|
||||
|
@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
|
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PL310 and variants) based level 2 cache controller. All these various implementations
|
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of the L2 cache controller have compatible programming models (Note 1).
|
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Some of the properties that are just prefixed "cache-*" are taken from section
|
||||
3.7.3 of the ePAPR v1.1 specification which can be found at:
|
||||
https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
|
||||
3.7.3 of the Devicetree Specification which can be found at:
|
||||
https://www.devicetree.org/specifications/
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||||
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||||
The ARM L2 cache representation in the device tree should be done as follows:
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||||
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||||
|
@ -7,6 +7,14 @@ registers giving access to numerous features: clocks, pin-muxing and
|
||||
many other SoC configuration items. This DT binding allows to describe
|
||||
this system controller.
|
||||
|
||||
For the top level node:
|
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- compatible: must be: "syscon", "simple-mfd";
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||||
- reg: register area of the AP806 system controller
|
||||
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Clocks:
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||||
-------
|
||||
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||||
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||||
The Device Tree node representing the AP806 system controller provides
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||||
a number of clocks:
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||||
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||||
@ -17,19 +25,76 @@ a number of clocks:
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||||
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Required properties:
|
||||
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- compatible: must be:
|
||||
"marvell,ap806-system-controller", "syscon"
|
||||
- reg: register area of the AP806 system controller
|
||||
- compatible: must be: "marvell,ap806-clock"
|
||||
- #clock-cells: must be set to 1
|
||||
- clock-output-names: must be defined to:
|
||||
"ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
|
||||
|
||||
Pinctrl:
|
||||
--------
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible must be "marvell,ap806-pinctrl",
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, sdio(clk), spi0(clk)
|
||||
mpp1 1 gpio, sdio(cmd), spi0(miso)
|
||||
mpp2 2 gpio, sdio(d0), spi0(mosi)
|
||||
mpp3 3 gpio, sdio(d1), spi0(cs0n)
|
||||
mpp4 4 gpio, sdio(d2), i2c0(sda)
|
||||
mpp5 5 gpio, sdio(d3), i2c0(sdk)
|
||||
mpp6 6 gpio, sdio(ds)
|
||||
mpp7 7 gpio, sdio(d4), uart1(rxd)
|
||||
mpp8 8 gpio, sdio(d5), uart1(txd)
|
||||
mpp9 9 gpio, sdio(d6), spi0(cs1n)
|
||||
mpp10 10 gpio, sdio(d7)
|
||||
mpp11 11 gpio, uart0(txd)
|
||||
mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
|
||||
mpp13 13 gpio
|
||||
mpp14 14 gpio
|
||||
mpp15 15 gpio
|
||||
mpp16 16 gpio
|
||||
mpp17 17 gpio
|
||||
mpp18 18 gpio
|
||||
mpp19 19 gpio, uart0(rxd), sdio(pw_off)
|
||||
|
||||
GPIO:
|
||||
-----
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-8k-gpio"
|
||||
|
||||
- offset: offset address inside the syscon block
|
||||
|
||||
Example:
|
||||
ap_syscon: system-controller@6f4000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f4000 0x1000>;
|
||||
|
||||
syscon: system-controller@6f4000 {
|
||||
compatible = "marvell,ap806-system-controller", "syscon";
|
||||
ap_clk: clock {
|
||||
compatible = "marvell,ap806-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
|
||||
"ap-fixed", "ap-mss";
|
||||
reg = <0x6f4000 0x1000>;
|
||||
};
|
||||
|
||||
ap_pinctrl: pinctrl {
|
||||
compatible = "marvell,ap806-pinctrl";
|
||||
};
|
||||
|
||||
ap_gpio: gpio {
|
||||
compatible = "marvell,armada-8k-gpio";
|
||||
offset = <0x1040>;
|
||||
ngpios = <19>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&ap_pinctrl 0 0 19>;
|
||||
};
|
||||
};
|
||||
|
@ -7,6 +7,13 @@ Controller 0 and System Controller 1. This Device Tree binding allows
|
||||
to describe the first system controller, which provides registers to
|
||||
configure various aspects of the SoC.
|
||||
|
||||
For the top level node:
|
||||
- compatible: must be: "syscon", "simple-mfd";
|
||||
- reg: register area of the CP110 system controller 0
|
||||
|
||||
Clocks:
|
||||
-------
|
||||
|
||||
The Device Tree node representing this System Controller 0 provides a
|
||||
number of clocks:
|
||||
|
||||
@ -27,6 +34,7 @@ The following clocks are available:
|
||||
- 0 2 EIP
|
||||
- 0 3 Core
|
||||
- 0 4 NAND core
|
||||
- 0 5 SDIO core
|
||||
- Gatable clocks
|
||||
- 1 0 Audio
|
||||
- 1 1 Comm Unit
|
||||
@ -56,28 +64,126 @@ The following clocks are available:
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"marvell,cp110-system-controller0", "syscon";
|
||||
- reg: register area of the CP110 system controller 0
|
||||
"marvell,cp110-clock"
|
||||
- #clock-cells: must be set to 2
|
||||
- core-clock-output-names must be set to:
|
||||
"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
|
||||
- gate-clock-output-names must be set to:
|
||||
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
|
||||
Pinctrl:
|
||||
--------
|
||||
|
||||
For common binding part and usage, refer to the file
|
||||
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-7k-pinctrl",
|
||||
"marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
|
||||
depending on the specific variant of the SoC being used.
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
|
||||
mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
|
||||
mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
|
||||
mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio)
|
||||
mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
|
||||
mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
|
||||
mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
|
||||
mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
|
||||
mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
|
||||
mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
|
||||
mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act)
|
||||
mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act)
|
||||
mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
|
||||
mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso)
|
||||
mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
|
||||
mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
|
||||
mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk)
|
||||
mpp17 17 gpio, dev(ad5), ge0(txd3)
|
||||
mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
|
||||
mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
|
||||
mpp20 20 gpio, dev(ad2), ge0(txd0)
|
||||
mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
|
||||
mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
|
||||
mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
|
||||
mpp24 24 gpio, dev(a0), au(i2slrclk)
|
||||
mpp25 25 gpio, dev(oen), au(i2sdo_spdifo)
|
||||
mpp26 26 gpio, dev(wen0), au(i2sbclk)
|
||||
mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
|
||||
mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
|
||||
mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
|
||||
mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk)
|
||||
mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
|
||||
mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
|
||||
mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
|
||||
mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2
|
||||
mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3
|
||||
mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
|
||||
mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp)
|
||||
mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp)
|
||||
mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0
|
||||
mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1
|
||||
mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp)
|
||||
mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4
|
||||
mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp)
|
||||
mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp)
|
||||
mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn)
|
||||
mpp46 46 gpio, ge1(txd1), uart1(rts)
|
||||
mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc)
|
||||
mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp)
|
||||
mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp)
|
||||
mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11)
|
||||
mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
|
||||
mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
|
||||
mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
|
||||
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
|
||||
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
|
||||
mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
|
||||
mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
|
||||
mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)
|
||||
mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1)
|
||||
mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2)
|
||||
mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
|
||||
mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)
|
||||
|
||||
GPIO:
|
||||
-----
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-8k-gpio"
|
||||
|
||||
- offset: offset address inside the syscon block
|
||||
|
||||
Example:
|
||||
|
||||
cpm_syscon0: system-controller@440000 {
|
||||
compatible = "marvell,cp110-system-controller0", "syscon";
|
||||
reg = <0x440000 0x1000>;
|
||||
cpm_syscon0: system-controller@440000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x440000 0x1000>;
|
||||
|
||||
cpm_clk: clock {
|
||||
compatible = "marvell,cp110-clock";
|
||||
#clock-cells = <2>;
|
||||
core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
|
||||
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
};
|
||||
|
||||
cpm_pinctrl: pinctrl {
|
||||
compatible = "marvell,armada-8k-cpm-pinctrl";
|
||||
};
|
||||
|
||||
cpm_gpio1: gpio@100 {
|
||||
compatible = "marvell,armada-8k-gpio";
|
||||
offset = <0x100>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&cpm_pinctrl 0 0 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
@ -12,6 +12,8 @@ compatible: Must contain one of
|
||||
"mediatek,mt6592"
|
||||
"mediatek,mt6755"
|
||||
"mediatek,mt6795"
|
||||
"mediatek,mt6797"
|
||||
"mediatek,mt7622"
|
||||
"mediatek,mt7623"
|
||||
"mediatek,mt8127"
|
||||
"mediatek,mt8135"
|
||||
@ -38,6 +40,12 @@ Supported boards:
|
||||
- Evaluation board for MT6795(Helio X10):
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
|
||||
- Evaluation board for MT6797(Helio X20):
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
|
||||
- Reference board variant 1 for MT7622:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
|
||||
- Evaluation board for MT7623:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
||||
|
20
Bindings/arm/realtek.txt
Normal file
20
Bindings/arm/realtek.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Realtek platforms device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
|
||||
RTD1295 SoC
|
||||
===========
|
||||
|
||||
Required root node properties:
|
||||
|
||||
- compatible : must contain "realtek,rtd1295"
|
||||
|
||||
|
||||
Root node property compatible must contain, depending on board:
|
||||
|
||||
- Zidoo X9S: "zidoo,x9s"
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "zidoo,x9s", "realtek,rtd1295";
|
@ -42,6 +42,10 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
|
||||
|
||||
- Firefly Firefly-RK3399 board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
|
||||
|
||||
- ChipSPARK PopMetal-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
|
||||
@ -138,9 +142,9 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
|
||||
|
||||
- Rockchip RK1108 Evaluation board
|
||||
- Rockchip RV1108 Evaluation board
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
|
||||
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
|
@ -55,12 +55,19 @@ Boards:
|
||||
compatible = "renesas,bockw", "renesas,r8a7778"
|
||||
- Genmai (RTK772100BC00000BR)
|
||||
compatible = "renesas,genmai", "renesas,r7s72100"
|
||||
- GR-Peach (X28A-M01-E/F)
|
||||
compatible = "renesas,gr-peach", "renesas,r7s72100"
|
||||
- Gose (RTP0RC7793SEB00010S)
|
||||
compatible = "renesas,gose", "renesas,r8a7793"
|
||||
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
|
||||
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
|
||||
H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
|
||||
compatible = "renesas,h3ulcb", "renesas,r8a7795";
|
||||
- Henninger
|
||||
compatible = "renesas,henninger", "renesas,r8a7791"
|
||||
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
|
||||
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
compatible = "iwave,g20m", "renesas,r8a7743"
|
||||
- Koelsch (RTP0RC7791SEB00010S)
|
||||
compatible = "renesas,koelsch", "renesas,r8a7791"
|
||||
- Kyoto Microcomputer Co. KZM-A9-Dual
|
||||
@ -69,7 +76,7 @@ Boards:
|
||||
compatible = "renesas,kzm9g", "renesas,sh73a0"
|
||||
- Lager (RTP0RC7790SEB00010S)
|
||||
compatible = "renesas,lager", "renesas,r8a7790"
|
||||
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
|
||||
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
|
||||
compatible = "renesas,m3ulcb", "renesas,r8a7796";
|
||||
- Marzen (R0P7779A00010S)
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
@ -81,6 +88,8 @@ Boards:
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7795";
|
||||
- Salvator-X (RTP0RC7796SIPB0011S)
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7796";
|
||||
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
|
||||
compatible = "renesas,salvator-xs", "renesas,r8a7795";
|
||||
- SILK (RTP0RC7794LCB00011S)
|
||||
compatible = "renesas,silk", "renesas,r8a7794"
|
||||
- SK-RZG1E (YR8A77450S000BE)
|
||||
|
@ -29,7 +29,6 @@ board-specific compatible values:
|
||||
nvidia,harmony
|
||||
nvidia,seaboard
|
||||
nvidia,ventana
|
||||
nvidia,whistler
|
||||
toradex,apalis_t30
|
||||
toradex,apalis_t30-eval
|
||||
toradex,apalis-tk1
|
||||
|
@ -29,9 +29,9 @@ corresponding to the system hierarchy; syntactically they are defined as device
|
||||
tree nodes.
|
||||
|
||||
The remainder of this document provides the topology bindings for ARM, based
|
||||
on the ePAPR standard, available from:
|
||||
on the Devicetree Specification, available from:
|
||||
|
||||
http://www.power.org/documentation/epapr-version-1-1/
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
If not stated otherwise, whenever a reference to a cpu node phandle is made its
|
||||
value must point to a cpu node compliant with the cpu node bindings as
|
||||
|
@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
|
||||
Required properties:
|
||||
- reg: Physical base address and size of the controller's register area.
|
||||
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
|
||||
chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
|
||||
chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- interrupts: Interrupt specifier. Refer to interrupt binding.
|
||||
|
||||
|
55
Bindings/ata/cortina,gemini-sata-bridge.txt
Normal file
55
Bindings/ata/cortina,gemini-sata-bridge.txt
Normal file
@ -0,0 +1,55 @@
|
||||
* Cortina Systems Gemini SATA Bridge
|
||||
|
||||
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
|
||||
takes two Faraday Technology FTIDE010 PATA controllers and bridges
|
||||
them in different configurations to two SATA ports.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be
|
||||
"cortina,gemini-sata-bridge"
|
||||
- reg: registers and size for the block
|
||||
- resets: phandles to the reset lines for both SATA bridges
|
||||
- reset-names: must be "sata0", "sata1"
|
||||
- clocks: phandles to the compulsory peripheral clocks
|
||||
- clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
|
||||
- syscon: a phandle to the global Gemini system controller
|
||||
- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for
|
||||
the ATA controller and SATA bridges. Values 0..3:
|
||||
Mode 0: ata0 master <-> sata0
|
||||
ata1 master <-> sata1
|
||||
ata0 slave interface brought out on IDE pads
|
||||
Mode 1: ata0 master <-> sata0
|
||||
ata1 master <-> sata1
|
||||
ata1 slave interface brought out on IDE pads
|
||||
Mode 2: ata1 master <-> sata1
|
||||
ata1 slave <-> sata0
|
||||
ata0 master and slave interfaces brought out
|
||||
on IDE pads
|
||||
Mode 3: ata0 master <-> sata0
|
||||
ata0 slave <-> sata1
|
||||
ata1 master and slave interfaces brought out
|
||||
on IDE pads
|
||||
|
||||
Optional boolean properties:
|
||||
- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection.
|
||||
The muxmode setting decides whether ATA0 or ATA1 is brought out,
|
||||
and whether master, slave or both interfaces get brought out.
|
||||
- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge
|
||||
inside the Gemnini SoC. The Muxmode decides what PATA blocks will
|
||||
be muxed out and how.
|
||||
|
||||
Example:
|
||||
|
||||
sata: sata@46000000 {
|
||||
compatible = "cortina,gemini-sata-bridge";
|
||||
reg = <0x46000000 0x100>;
|
||||
resets = <&rcon 26>, <&rcon 27>;
|
||||
reset-names = "sata0", "sata1";
|
||||
clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
|
||||
<&gcc GEMINI_CLK_GATE_SATA1>;
|
||||
clock-names = "SATA0_PCLK", "SATA1_PCLK";
|
||||
syscon = <&syscon>;
|
||||
cortina,gemini-ata-muxmode = <3>;
|
||||
cortina,gemini-enable-ide-pins;
|
||||
cortina,gemini-enable-sata-bridge;
|
||||
};
|
38
Bindings/ata/faraday,ftide010.txt
Normal file
38
Bindings/ata/faraday,ftide010.txt
Normal file
@ -0,0 +1,38 @@
|
||||
* Faraday Technology FTIDE010 PATA controller
|
||||
|
||||
This controller is the first Faraday IDE interface block, used in the
|
||||
StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini
|
||||
platform. The controller can do PIO modes 0 through 4, Multi-word DMA
|
||||
(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6.
|
||||
|
||||
On the Gemini platform, this PATA block is accompanied by a PATA to
|
||||
SATA bridge in order to support SATA. This is why a phandle to that
|
||||
controller is compulsory on that platform.
|
||||
|
||||
The timing properties are unique per-SoC, not per-board.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
"cortina,gemini-pata", "faraday,ftide010"
|
||||
"faraday,ftide010"
|
||||
- interrupts: interrupt for the block
|
||||
- reg: registers and size for the block
|
||||
|
||||
Optional properties:
|
||||
- clocks: a SoC clock running the peripheral.
|
||||
- clock-names: should be set to "PCLK" for the peripheral clock.
|
||||
|
||||
Required properties for "cortina,gemini-pata" compatible:
|
||||
- sata: a phande to the Gemini PATA to SATA bridge, see
|
||||
cortina,gemini-sata-bridge.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
ata@63000000 {
|
||||
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
||||
reg = <0x63000000 0x100>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&gcc GEMINI_CLK_GATE_IDE>;
|
||||
clock-names = "PCLK";
|
||||
sata = <&sata>;
|
||||
};
|
@ -1,14 +1,22 @@
|
||||
* Renesas R-Car SATA
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of the following:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
("renesas,rcar-sata" is deprecated)
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
- "renesas,sata-r8a7791" for R-Car M2-W
|
||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
must list the SoC-specific version corresponding
|
||||
to the platform first followed by the generic
|
||||
version.
|
||||
|
||||
- reg : address and length of the SATA registers;
|
||||
- interrupts : must consist of one interrupt specifier.
|
||||
- clocks : must contain a reference to the functional clock.
|
||||
@ -16,7 +24,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
sata0: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7791";
|
||||
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -3,7 +3,8 @@ Broadcom GISB bus Arbiter controller
|
||||
Required properties:
|
||||
|
||||
- compatible:
|
||||
"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
|
||||
"brcm,bcm7278-gisb-arb" for V7 28nm chips
|
||||
"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
|
||||
"brcm,bcm7435-gisb-arb" for newer 40nm chips
|
||||
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
|
||||
"brcm,bcm7038-gisb-arb" for 130nm chips
|
||||
|
@ -10,7 +10,7 @@ enabled for child devices connected to the bus (either on-SoC or externally)
|
||||
to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
|
||||
in ePAPR, it is not an extension of "simple-bus".
|
||||
in the Devicetree Specification, it is not an extension of "simple-bus".
|
||||
|
||||
|
||||
Required properties:
|
||||
|
@ -10,7 +10,8 @@ stdout-path property
|
||||
--------------------
|
||||
|
||||
Device trees may specify the device to be used for boot console output
|
||||
with a stdout-path property under /chosen, as described in ePAPR, e.g.
|
||||
with a stdout-path property under /chosen, as described in the Devicetree
|
||||
Specification, e.g.
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
|
@ -1,11 +1,14 @@
|
||||
* Amlogic Meson8b Clock and Reset Unit
|
||||
* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
|
||||
|
||||
The Amlogic Meson8b clock controller generates and supplies clock to various
|
||||
controllers within the SoC.
|
||||
The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
|
||||
supplies clock to various controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,meson8b-clkc"
|
||||
- compatible: must be one of:
|
||||
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
|
||||
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
|
||||
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
|
||||
- reg: it must be composed by two tuples:
|
||||
0) physical base address of the xtal register and length of memory
|
||||
mapped region.
|
||||
|
@ -219,3 +219,79 @@ BCM63138
|
||||
--------
|
||||
PLL and leaf clock compatible strings for BCM63138 are:
|
||||
"brcm,bcm63138-armpll"
|
||||
|
||||
Stingray
|
||||
-----------
|
||||
PLL and leaf clock compatible strings for Stingray are:
|
||||
"brcm,sr-genpll0"
|
||||
"brcm,sr-genpll1"
|
||||
"brcm,sr-genpll2"
|
||||
"brcm,sr-genpll3"
|
||||
"brcm,sr-genpll4"
|
||||
"brcm,sr-genpll5"
|
||||
"brcm,sr-genpll6"
|
||||
|
||||
"brcm,sr-lcpll0"
|
||||
"brcm,sr-lcpll1"
|
||||
"brcm,sr-lcpll-pcie"
|
||||
|
||||
|
||||
The following table defines the set of PLL/clock index and ID for Stingray.
|
||||
These clock IDs are defined in:
|
||||
"include/dt-bindings/clock/bcm-sr.h"
|
||||
|
||||
Clock Source Index ID
|
||||
--- ----- ----- ---------
|
||||
crystal N/A N/A N/A
|
||||
crmu_ref25m crystal N/A N/A
|
||||
|
||||
genpll0 crystal 0 BCM_SR_GENPLL0
|
||||
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
|
||||
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
|
||||
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
|
||||
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
|
||||
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
|
||||
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
|
||||
|
||||
genpll1 crystal 0 BCM_SR_GENPLL1
|
||||
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
|
||||
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
|
||||
|
||||
genpll2 crystal 0 BCM_SR_GENPLL2
|
||||
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
|
||||
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
|
||||
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
|
||||
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
|
||||
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
|
||||
|
||||
genpll3 crystal 0 BCM_SR_GENPLL3
|
||||
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
|
||||
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
|
||||
|
||||
genpll4 crystal 0 BCM_SR_GENPLL4
|
||||
ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
|
||||
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
|
||||
noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
|
||||
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
|
||||
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
|
||||
|
||||
|
||||
genpll5 crystal 0 BCM_SR_GENPLL5
|
||||
fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
|
||||
crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
|
||||
raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
|
||||
|
||||
genpll6 crystal 0 BCM_SR_GENPLL6
|
||||
48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
|
||||
|
||||
lcpll0 crystal 0 BCM_SR_LCPLL0
|
||||
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
|
||||
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
|
||||
clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
|
||||
sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
|
||||
|
||||
lcpll1 crystal 0 BCM_SR_LCPLL1
|
||||
wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
|
||||
|
||||
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
|
||||
pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
|
||||
|
@ -11,6 +11,7 @@ Required Properties:
|
||||
- compatible: the compatible should be one of the following strings to
|
||||
indicate the clock controller functionality.
|
||||
|
||||
- "hisilicon,hi6220-acpu-sctrl"
|
||||
- "hisilicon,hi6220-aoctrl"
|
||||
- "hisilicon,hi6220-sysctrl"
|
||||
- "hisilicon,hi6220-mediactrl"
|
||||
|
31
Bindings/clock/img,boston-clock.txt
Normal file
31
Bindings/clock/img,boston-clock.txt
Normal file
@ -0,0 +1,31 @@
|
||||
Binding for Imagination Technologies MIPS Boston clock sources.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The device node must be a child node of the syscon node corresponding to the
|
||||
Boston system's platform registers.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "img,boston-clock".
|
||||
- #clock-cells : Should be set to 1.
|
||||
Values available for clock consumers can be found in the header file:
|
||||
<dt-bindings/clock/boston-clock.h>
|
||||
|
||||
Example:
|
||||
|
||||
system-controller@17ffd000 {
|
||||
compatible = "img,boston-platform-regs", "syscon";
|
||||
reg = <0x17ffd000 0x1000>;
|
||||
|
||||
clk_boston: clock {
|
||||
compatible = "img,boston-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@17ffe000 {
|
||||
/* ... */
|
||||
clocks = <&clk_boston BOSTON_CLK_SYS>;
|
||||
};
|
@ -8,6 +8,7 @@ Required properties :
|
||||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-ipq4019"
|
||||
"qcom,gcc-ipq8074"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8916"
|
||||
"qcom,gcc-msm8960"
|
||||
|
@ -57,6 +57,11 @@ Optional properties:
|
||||
- clocks: If clock-frequency is not specified, sysclk may be provided
|
||||
as an input clock. Either clock-frequency or clocks must be
|
||||
provided.
|
||||
A second input clock, called "coreclk", may be provided if
|
||||
core PLLs are based on a different input clock from the
|
||||
platform PLL.
|
||||
- clock-names: Required if a coreclk is present. Valid names are
|
||||
"sysclk" and "coreclk".
|
||||
|
||||
2. Clock Provider
|
||||
|
||||
@ -73,6 +78,7 @@ second cell is the clock index for the specified type.
|
||||
2 hwaccel index (n in CLKCGnHWACSR)
|
||||
3 fman 0 for fm1, 1 for fm2
|
||||
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
|
||||
5 coreclk must be 0
|
||||
|
||||
3. Example
|
||||
|
||||
|
@ -15,6 +15,11 @@ Required Properties:
|
||||
- compatible: Must be one of:
|
||||
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
|
||||
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
|
||||
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
|
||||
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
|
||||
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
|
||||
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
|
||||
@ -24,9 +29,10 @@ Required Properties:
|
||||
- clocks: References to external parent clocks, one entry for each entry in
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
|
||||
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
|
||||
r8a7795, r8a7796)
|
||||
- "extalr" (r8a7795, r8a7796)
|
||||
- "usb_extal" (r8a7743, r8a7745)
|
||||
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
|
56
Bindings/clock/rockchip,rk3128-cru.txt
Normal file
56
Bindings/clock/rockchip,rk3128-cru.txt
Normal file
@ -0,0 +1,56 @@
|
||||
* Rockchip RK3128 Clock and Reset Unit
|
||||
|
||||
The RK3128 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3128-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3128-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart2: serial@20068000 {
|
||||
compatible = "rockchip,serial";
|
||||
reg = <0x20068000 0x100>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "sclk_uart", "pclk_uart";
|
||||
};
|
31
Bindings/clock/sun8i-de2.txt
Normal file
31
Bindings/clock/sun8i-de2.txt
Normal file
@ -0,0 +1,31 @@
|
||||
Allwinner Display Engine 2.0 Clock Control Binding
|
||||
--------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
- "allwinner,sun8i-a83t-de2-clk"
|
||||
- "allwinner,sun8i-v3s-de2-clk"
|
||||
- "allwinner,sun50i-h5-de2-clk"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the clocks feeding the display engine subsystem.
|
||||
Three are needed:
|
||||
- "mod": the display engine module clock
|
||||
- "bus": the bus clock for the whole display engine subsystem
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- resets: phandle to the reset control for the display engine subsystem.
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
Example:
|
||||
de2_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-a83t-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
"mod";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
@ -6,6 +6,8 @@ Required properties :
|
||||
- "allwinner,sun6i-a31-ccu"
|
||||
- "allwinner,sun8i-a23-ccu"
|
||||
- "allwinner,sun8i-a33-ccu"
|
||||
- "allwinner,sun8i-a83t-ccu"
|
||||
- "allwinner,sun8i-a83t-r-ccu"
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
- "allwinner,sun8i-h3-r-ccu"
|
||||
- "allwinner,sun8i-v3s-ccu"
|
||||
@ -18,11 +20,12 @@ Required properties :
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
- "hosc": the high frequency oscillator (usually at 24MHz)
|
||||
- "losc": the low frequency oscillator (usually at 32kHz)
|
||||
On the A83T, this is the internal 16MHz oscillator divided by 512
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
For the PRCM CCUs on H3/A64, two more clocks are needed:
|
||||
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
|
||||
- "pll-periph": the SoC's peripheral PLL from the main CCU
|
||||
- "iosc": the SoC's internal frequency oscillator
|
||||
|
||||
|
37
Bindings/clock/ti,sci-clk.txt
Normal file
37
Bindings/clock/ti,sci-clk.txt
Normal file
@ -0,0 +1,37 @@
|
||||
Texas Instruments TI-SCI Clocks
|
||||
===============================
|
||||
|
||||
All clocks on Texas Instruments' SoCs that contain a System Controller,
|
||||
are only controlled by this entity. Communication between a host processor
|
||||
running an OS and the System Controller happens through a protocol known
|
||||
as TI-SCI[1]. This clock implementation plugs into the common clock
|
||||
framework and makes use of the TI-SCI protocol on clock API requests.
|
||||
|
||||
[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- compatible: Must be "ti,k2g-sci-clk"
|
||||
- #clock-cells: Shall be 2.
|
||||
In clock consumers, this cell represents the device ID and clock ID
|
||||
exposed by the PM firmware. The assignments can be found in the header
|
||||
files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
|
||||
<dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
|
||||
is the SoC involved, for example 'k2g'.
|
||||
|
||||
Examples:
|
||||
--------
|
||||
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
|
||||
k2g_clks: clocks {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@2530c00 {
|
||||
compatible = "ns16550a";
|
||||
clocks = <&k2g_clks 0x2c 0>;
|
||||
};
|
56
Bindings/clock/ti-clkctrl.txt
Normal file
56
Bindings/clock/ti-clkctrl.txt
Normal file
@ -0,0 +1,56 @@
|
||||
Texas Instruments clkctrl clock binding
|
||||
|
||||
Texas Instruments SoCs can have a clkctrl clock controller for each
|
||||
interconnect target module. The clkctrl clock controller manages functional
|
||||
and interface clocks for each module. Each clkctrl controller can also
|
||||
gate one or more optional functional clocks for a module, and can have one
|
||||
or more clock muxes. There is a clkctrl clock controller typically for each
|
||||
interconnect target module on omap4 and later variants.
|
||||
|
||||
The clock consumers can specify the index of the clkctrl clock using
|
||||
the hardware offset from the clkctrl instance register space. The optional
|
||||
clocks can be specified by clkctrl hardware offset and the index of the
|
||||
optional clock.
|
||||
|
||||
For more information, please see the Linux clock framework binding at
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||
|
||||
Required properties :
|
||||
- compatible : shall be "ti,clkctrl"
|
||||
- #clock-cells : shall contain 2 with the first entry being the instance
|
||||
offset from the clock domain base and the second being the
|
||||
clock index
|
||||
|
||||
Example: Clock controller node on omap 4430:
|
||||
|
||||
&cm2 {
|
||||
l4per: cm@1400 {
|
||||
cm_l4per@0 {
|
||||
cm_l4per_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x1b0>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
|
||||
|
||||
#define OMAP4_CLKCTRL_OFFSET 0x20
|
||||
#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
|
||||
#define MODULEMODE_HWCTRL 1
|
||||
#define MODULEMODE_SWCTRL 2
|
||||
|
||||
#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
|
||||
...
|
||||
#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
|
||||
|
||||
Example: Clock consumer node for GPIO2:
|
||||
|
||||
&gpio2 {
|
||||
clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
|
||||
&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
|
||||
};
|
@ -1,6 +1,6 @@
|
||||
Common properties
|
||||
|
||||
The ePAPR specification does not define any properties related to hardware
|
||||
The Devicetree Specification does not define any properties related to hardware
|
||||
byteswapping, but endianness issues show up frequently in porting Linux to
|
||||
different machine types. This document attempts to provide a consistent
|
||||
way of handling byteswapping across drivers.
|
||||
|
@ -63,64 +63,64 @@ cpu0_opp_table: opp-table {
|
||||
* because they can not be enabled simultaneously on a
|
||||
* single SoC.
|
||||
*/
|
||||
opp50@300000000 {
|
||||
opp50-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <950000 931000 969000>;
|
||||
opp-supported-hw = <0x06 0x0010>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@275000000 {
|
||||
opp100-275000000 {
|
||||
opp-hz = /bits/ 64 <275000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x01 0x00FF>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@300000000 {
|
||||
opp100-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x06 0x0020>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@500000000 {
|
||||
opp100-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
opp100@600000000 {
|
||||
opp100-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x06 0x0040>;
|
||||
};
|
||||
|
||||
opp120@600000000 {
|
||||
opp120-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1200000 1176000 1224000>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
opp120@720000000 {
|
||||
opp120-720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
opp-microvolt = <1200000 1176000 1224000>;
|
||||
opp-supported-hw = <0x06 0x0080>;
|
||||
};
|
||||
|
||||
oppturbo@720000000 {
|
||||
oppturbo-720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
opp-microvolt = <1260000 1234800 1285200>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
oppturbo@800000000 {
|
||||
oppturbo-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1260000 1234800 1285200>;
|
||||
opp-supported-hw = <0x06 0x0100>;
|
||||
};
|
||||
|
||||
oppnitro@1000000000 {
|
||||
oppnitro-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1325000 1298500 1351500>;
|
||||
opp-supported-hw = <0x04 0x0200>;
|
||||
|
@ -118,8 +118,8 @@ PROPERTIES
|
||||
Definition: A list of clock name strings in the same order as the
|
||||
clocks property.
|
||||
|
||||
Note: All other standard properties (see the ePAPR) are allowed
|
||||
but are optional.
|
||||
Note: All other standard properties (see the Devicetree Specification)
|
||||
are allowed but are optional.
|
||||
|
||||
|
||||
EXAMPLE
|
||||
|
@ -55,8 +55,8 @@ PROPERTIES
|
||||
triplet that includes the child address, parent address, &
|
||||
length.
|
||||
|
||||
Note: All other standard properties (see the ePAPR) are allowed
|
||||
but are optional.
|
||||
Note: All other standard properties (see the Devicetree Specification)
|
||||
are allowed but are optional.
|
||||
|
||||
EXAMPLE
|
||||
crypto@a0000 {
|
||||
|
27
Bindings/crypto/inside-secure-safexcel.txt
Normal file
27
Bindings/crypto/inside-secure-safexcel.txt
Normal file
@ -0,0 +1,27 @@
|
||||
Inside Secure SafeXcel cryptographic engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "inside-secure,safexcel-eip197".
|
||||
- reg: Base physical address of the engine and length of memory mapped region.
|
||||
- interrupts: Interrupt numbers for the rings and engine.
|
||||
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
|
||||
|
||||
Optional properties:
|
||||
- clocks: Reference to the crypto engine clock.
|
||||
|
||||
Example:
|
||||
|
||||
crypto: crypto@800000 {
|
||||
compatible = "inside-secure,safexcel-eip197";
|
||||
reg = <0x800000 0x200000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||
"eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
status = "disabled";
|
||||
};
|
@ -6,8 +6,7 @@ Required properties:
|
||||
- interrupts: Should contain the five crypto engines interrupts in numeric
|
||||
order. These are global system and four descriptor rings.
|
||||
- clocks: the clock used by the core
|
||||
- clock-names: the names of the clock listed in the clocks property. These are
|
||||
"ethif", "cryp"
|
||||
- clock-names: Must contain "cryp".
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
|
||||
|
||||
@ -20,8 +19,7 @@ Example:
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||
<ðsys CLK_ETHSYS_CRYPTO>;
|
||||
clock-names = "ethif","cryp";
|
||||
clocks = <ðsys CLK_ETHSYS_CRYPTO>;
|
||||
clock-names = "cryp";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
};
|
||||
|
@ -5,7 +5,7 @@ with HDMI output and the HVS (Hardware Video Scaler) for compositing
|
||||
display planes.
|
||||
|
||||
Required properties for VC4:
|
||||
- compatible: Should be "brcm,bcm2835-vc4"
|
||||
- compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
|
||||
|
||||
Required properties for Pixel Valve:
|
||||
- compatible: Should be one of "brcm,bcm2835-pixelvalve0",
|
||||
@ -54,11 +54,14 @@ Required properties for VEC:
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
Required properties for V3D:
|
||||
- compatible: Should be "brcm,bcm2835-v3d"
|
||||
- compatible: Should be "brcm,bcm2835-v3d" or "brcm,cygnus-v3d"
|
||||
- reg: Physical base address and length of the V3D's registers
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
Optional properties for V3D:
|
||||
- clocks: The clock the unit runs on
|
||||
|
||||
Required properties for DSI:
|
||||
- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
|
||||
- reg: Physical base address and length of the DSI block's registers
|
||||
|
@ -78,6 +78,7 @@ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
remote endpoint phandle should be a reference to a valid mipi_dsi_host device
|
||||
node.
|
||||
- Video port 1 for the HDMI output
|
||||
- Audio port 2 for the HDMI audio input
|
||||
|
||||
|
||||
Example
|
||||
@ -112,5 +113,12 @@ Example
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
codec_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s0_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -25,7 +25,8 @@ Required properties:
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
|
||||
corresponding to the video input of the controller and one port numbered 1
|
||||
corresponding to its HDMI output. Each port shall have a single endpoint.
|
||||
corresponding to its HDMI output, and one port numbered 2 corresponding to
|
||||
sound input of the controller. Each port shall have a single endpoint.
|
||||
|
||||
Optional properties:
|
||||
|
||||
@ -59,6 +60,12 @@ Example:
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
rcar_dw_hdmi0_sound_in: endpoint {
|
||||
remote-endpoint = <&hdmi_sound_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -8,12 +8,13 @@ Required properties:
|
||||
- compatible: value should be one of:
|
||||
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
|
||||
- reg: physical base address and length of the DECON registers set.
|
||||
- interrupts: should contain a list of all DECON IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier format
|
||||
depends on the interrupt controller used.
|
||||
- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
|
||||
in the same order as they were listed in the interrupts
|
||||
property.
|
||||
- interrupt-names: should contain the interrupt names depending on mode of work:
|
||||
video mode: "vsync",
|
||||
command mode: "lcd_sys",
|
||||
command mode with software trigger: "lcd_sys", "te".
|
||||
- interrupts or interrupts-extended: list of interrupt specifiers corresponding
|
||||
to names privided in interrupt-names, as described in
|
||||
interrupt-controller/interrupts.txt
|
||||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
- clock-names: list of clock names sorted in the same order as the clocks
|
||||
|
8
Bindings/display/panel/auo,p320hvn03.txt
Normal file
8
Bindings/display/panel/auo,p320hvn03.txt
Normal file
@ -0,0 +1,8 @@
|
||||
AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "auo,p320hvn03"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
@ -57,11 +57,11 @@ can be specified.
|
||||
The parameters are defined as:
|
||||
|
||||
+----------+-------------------------------------+----------+-------+
|
||||
| | ↑ | | |
|
||||
| | ^ | | |
|
||||
| | |vback_porch | | |
|
||||
| | ↓ | | |
|
||||
| | v | | |
|
||||
+----------#######################################----------+-------+
|
||||
| # ↑ # | |
|
||||
| # ^ # | |
|
||||
| # | # | |
|
||||
| hback # | # hfront | hsync |
|
||||
| porch # | hactive # porch | len |
|
||||
@ -69,15 +69,15 @@ The parameters are defined as:
|
||||
| # | # | |
|
||||
| # |vactive # | |
|
||||
| # | # | |
|
||||
| # ↓ # | |
|
||||
| # v # | |
|
||||
+----------#######################################----------+-------+
|
||||
| | ↑ | | |
|
||||
| | ^ | | |
|
||||
| | |vfront_porch | | |
|
||||
| | ↓ | | |
|
||||
| | v | | |
|
||||
+----------+-------------------------------------+----------+-------+
|
||||
| | ↑ | | |
|
||||
| | ^ | | |
|
||||
| | |vsync_len | | |
|
||||
| | ↓ | | |
|
||||
| | v | | |
|
||||
+----------+-------------------------------------+----------+-------+
|
||||
|
||||
Example:
|
||||
|
23
Bindings/display/panel/innolux,p079zca.txt
Normal file
23
Bindings/display/panel/innolux,p079zca.txt
Normal file
@ -0,0 +1,23 @@
|
||||
Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,p079zca"
|
||||
- reg: DSI virtual channel of the peripheral
|
||||
- power-supply: phandle of the regulator that provides the supply voltage
|
||||
- enable-gpios: panel enable gpio
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Example:
|
||||
|
||||
&mipi_dsi {
|
||||
panel {
|
||||
compatible = "innolux,p079zca";
|
||||
reg = <0>;
|
||||
power-supply = <...>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
8
Bindings/display/panel/nec,nl12880b20-05.txt
Normal file
8
Bindings/display/panel/nec,nl12880b20-05.txt
Normal file
@ -0,0 +1,8 @@
|
||||
NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nec,nl12880bc20-05"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
8
Bindings/display/panel/nlt,nl192108ac18-02d.txt
Normal file
8
Bindings/display/panel/nlt,nl192108ac18-02d.txt
Normal file
@ -0,0 +1,8 @@
|
||||
NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nlt,nl192108ac18-02d"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
@ -1,7 +1,10 @@
|
||||
Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel
|
||||
Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel
|
||||
|
||||
Required properties:
|
||||
- compatible: "samsung,s6e3ha2"
|
||||
- compatible: should be one of:
|
||||
"samsung,s6e3ha2",
|
||||
"samsung,s6e3hf2".
|
||||
- reg: the virtual channel number of a DSI peripheral
|
||||
- vdd3-supply: I/O voltage supply
|
||||
- vci-supply: voltage supply for analog circuits
|
||||
|
36
Bindings/display/st,stm32-ltdc.txt
Normal file
36
Bindings/display/st,stm32-ltdc.txt
Normal file
@ -0,0 +1,36 @@
|
||||
* STMicroelectronics STM32 lcd-tft display controller
|
||||
|
||||
- ltdc: lcd-tft display controller host
|
||||
must be a sub-node of st-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stm32-ltdc"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For ltdc it should contain:
|
||||
- "lcd" for the clock feeding the output pixel clock & IP clock.
|
||||
- resets: reset to be used by the device (defined by use of RCC macro).
|
||||
Required nodes:
|
||||
- Video port for RGB output.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
soc {
|
||||
...
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
|
||||
port {
|
||||
ltdc_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@ -4,6 +4,44 @@ Allwinner A10 Display Pipeline
|
||||
The Allwinner A10 Display pipeline is composed of several components
|
||||
that are going to be documented below:
|
||||
|
||||
For the input port of all components up to the TCON in the display
|
||||
pipeline, if there are multiple components, the local endpoint IDs
|
||||
must correspond to the index of the upstream block. For example, if
|
||||
the remote endpoint is Frontend 1, then the local endpoint ID must
|
||||
be 1.
|
||||
|
||||
Conversely, for the output ports of the same group, the remote endpoint
|
||||
ID must be the index of the local hardware block. If the local backend
|
||||
is backend 1, then the remote endpoint ID must be 1.
|
||||
|
||||
HDMI Encoder
|
||||
------------
|
||||
|
||||
The HDMI Encoder supports the HDMI video and audio outputs, and does
|
||||
CEC. It is one end of the pipeline.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a10s-hdmi
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the HDMI encoder
|
||||
* ahb: the HDMI interface clock
|
||||
* mod: the HDMI module clock
|
||||
* pll-0: the first video PLL
|
||||
* pll-1: the second video PLL
|
||||
- clock-names: the clock names mentioned above
|
||||
- dmas: phandles to the DMA channels used by the HDMI encoder
|
||||
* ddc-tx: The channel for DDC transmission
|
||||
* ddc-rx: The channel for DDC reception
|
||||
* audio-tx: The channel used for audio transmission
|
||||
- dma-names: the channel names mentioned above
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint. The second should be the
|
||||
output, usually to an HDMI connector.
|
||||
|
||||
TV Encoder
|
||||
----------
|
||||
|
||||
@ -31,6 +69,7 @@ Required properties:
|
||||
* allwinner,sun6i-a31-tcon
|
||||
* allwinner,sun6i-a31s-tcon
|
||||
* allwinner,sun8i-a33-tcon
|
||||
* allwinner,sun8i-v3s-tcon
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the TCON. Three are needed:
|
||||
@ -47,12 +86,15 @@ Required properties:
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint, the second one the output
|
||||
|
||||
The output should have two endpoints. The first is the block
|
||||
connected to the TCON channel 0 (usually a panel or a bridge), the
|
||||
second the block connected to the TCON channel 1 (usually the TV
|
||||
encoder)
|
||||
The output may have multiple endpoints. The TCON has two channels,
|
||||
usually with the first channel being used for the panels interfaces
|
||||
(RGB, LVDS, etc.), and the second being used for the outputs that
|
||||
require another controller (TV Encoder, HDMI, etc.). The endpoints
|
||||
will take an extra property, allwinner,tcon-channel, to specify the
|
||||
channel the endpoint is associated to. If that property is not
|
||||
present, the endpoint number will be used as the channel number.
|
||||
|
||||
On SoCs other than the A33, there is one more clock required:
|
||||
On SoCs other than the A33 and V3s, there is one more clock required:
|
||||
- 'tcon-ch1': The clock driving the TCON channel 1
|
||||
|
||||
DRC
|
||||
@ -138,6 +180,26 @@ Required properties:
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the outputs
|
||||
|
||||
Display Engine 2.0 Mixer
|
||||
------------------------
|
||||
|
||||
The DE2 mixer have many functionalities, currently only layer blending is
|
||||
supported.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun8i-v3s-de2-mixer
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- clocks: phandles to the clocks feeding the mixer
|
||||
* bus: the mixer interface clock
|
||||
* mod: the mixer module clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandles to the reset controllers driving the mixer
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the output
|
||||
|
||||
|
||||
Display Engine Pipeline
|
||||
-----------------------
|
||||
@ -148,13 +210,15 @@ extra node.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a10s-display-engine
|
||||
* allwinner,sun5i-a13-display-engine
|
||||
* allwinner,sun6i-a31-display-engine
|
||||
* allwinner,sun6i-a31s-display-engine
|
||||
* allwinner,sun8i-a33-display-engine
|
||||
* allwinner,sun8i-v3s-display-engine
|
||||
|
||||
- allwinner,pipelines: list of phandle to the display engine
|
||||
frontends available.
|
||||
frontends (DE 1.0) or mixers (DE 2.0) available.
|
||||
|
||||
Example:
|
||||
|
||||
@ -173,6 +237,57 @@ panel: panel {
|
||||
};
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi@01c16000 {
|
||||
compatible = "allwinner,sun5i-a10s-hdmi";
|
||||
reg = <0x01c16000 0x1000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
|
||||
<&ccu CLK_PLL_VIDEO0_2X>,
|
||||
<&ccu CLK_PLL_VIDEO1_2X>;
|
||||
clock-names = "ahb", "mod", "pll-0", "pll-1";
|
||||
dmas = <&dma SUN4I_DMA_NORMAL 16>,
|
||||
<&dma SUN4I_DMA_NORMAL 16>,
|
||||
<&dma SUN4I_DMA_DEDICATED 24>;
|
||||
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
hdmi_in_tcon0: endpoint {
|
||||
remote-endpoint = <&tcon0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tve0: tv-encoder@01c0a000 {
|
||||
compatible = "allwinner,sun4i-a10-tv-encoder";
|
||||
reg = <0x01c0a000 0x1000>;
|
||||
|
@ -58,6 +58,18 @@ Required properties:
|
||||
integer cells. The first cell is the offset of SYSCTRL register used
|
||||
to control TV Encoder DAC power, and the second cell is the bit mask.
|
||||
|
||||
* VGA output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-vga"
|
||||
- reg: Physical base address and length of the VGA device IO region
|
||||
- interrupts : VGA interrupt number to CPU
|
||||
- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
|
||||
- clock-names: Must be "i2c_wclk".
|
||||
- zte,vga-power-control: the phandle to SYSCTRL block followed by two
|
||||
integer cells. The first cell is the offset of SYSCTRL register used
|
||||
to control VGA DAC power, and the second cell is the bit mask.
|
||||
|
||||
Example:
|
||||
|
||||
vou: vou@1440000 {
|
||||
@ -81,6 +93,15 @@ vou: vou@1440000 {
|
||||
"main_wclk", "aux_wclk";
|
||||
};
|
||||
|
||||
vga: vga@8000 {
|
||||
compatible = "zte,zx296718-vga";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topcrm VGA_I2C_WCLK>;
|
||||
clock-names = "i2c_wclk";
|
||||
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
|
||||
};
|
||||
|
||||
hdmi: hdmi@c000 {
|
||||
compatible = "zte,zx296718-hdmi";
|
||||
reg = <0xc000 0x4000>;
|
||||
|
@ -3,6 +3,11 @@
|
||||
Required properties:
|
||||
- compatible: "arm,pl080", "arm,primecell";
|
||||
"arm,pl081", "arm,primecell";
|
||||
"faraday,ftdmac020", "arm,primecell"
|
||||
- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
|
||||
in the hardware and must be specified here as <0x0003b080>. This number
|
||||
follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
|
||||
for Faraday Technology.
|
||||
- reg: Address range of the PL08x registers
|
||||
- interrupt: The PL08x interrupt number
|
||||
- clocks: The clock running the IP core clock
|
||||
@ -20,8 +25,8 @@ Optional properties:
|
||||
- dma-requests: contains the total number of DMA requests supported by the DMAC
|
||||
- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
|
||||
64, 128 or 256 bytes are legal values
|
||||
- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
|
||||
values
|
||||
- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
|
||||
values, the Faraday FTDMAC020 can also accept 64 bits
|
||||
|
||||
Clients
|
||||
Required properties:
|
||||
|
29
Bindings/dma/brcm,iproc-sba.txt
Normal file
29
Bindings/dma/brcm,iproc-sba.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* Broadcom SBA RAID engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following
|
||||
"brcm,iproc-sba"
|
||||
"brcm,iproc-sba-v2"
|
||||
The "brcm,iproc-sba" has support for only 6 PQ coefficients
|
||||
The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients
|
||||
- mboxes: List of phandle and mailbox channel specifiers
|
||||
|
||||
Example:
|
||||
|
||||
raid_mbox: mbox@67400000 {
|
||||
...
|
||||
#mbox-cells = <3>;
|
||||
...
|
||||
};
|
||||
|
||||
raid0 {
|
||||
compatible = "brcm,iproc-sba-v2";
|
||||
mboxes = <&raid_mbox 0 0x1 0xffff>,
|
||||
<&raid_mbox 1 0x1 0xffff>,
|
||||
<&raid_mbox 2 0x1 0xffff>,
|
||||
<&raid_mbox 3 0x1 0xffff>,
|
||||
<&raid_mbox 4 0x1 0xffff>,
|
||||
<&raid_mbox 5 0x1 0xffff>,
|
||||
<&raid_mbox 6 0x1 0xffff>,
|
||||
<&raid_mbox 7 0x1 0xffff>;
|
||||
};
|
@ -30,8 +30,9 @@ Required Properties:
|
||||
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry per channel, named "ch%u", where %u is the
|
||||
channel number ranging from zero to the number of channels minus one.
|
||||
- interrupt-names: one entry for the error interrupt, named "error", plus one
|
||||
entry per channel, named "ch%u", where %u is the channel number ranging from
|
||||
zero to the number of channels minus one.
|
||||
|
||||
- clock-names: "fck" for the functional clock
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
|
@ -1,6 +1,6 @@
|
||||
* SHDMA Device Tree bindings
|
||||
|
||||
Sh-/r-mobile and r-car systems often have multiple identical DMA controller
|
||||
Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
|
||||
instances, capable of serving any of a common set of DMA slave devices, using
|
||||
the same configuration. To describe this topology we require all compatible
|
||||
SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
|
||||
|
24
Bindings/fsi/fsi-master-gpio.txt
Normal file
24
Bindings/fsi/fsi-master-gpio.txt
Normal file
@ -0,0 +1,24 @@
|
||||
Device-tree bindings for gpio-based FSI master driver
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible = "fsi-master-gpio";
|
||||
- clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
|
||||
- data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios = <gpio-descriptor>; : GPIO for enable signal
|
||||
- trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
|
||||
- mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
|
||||
functions (eg, external FSI masters)
|
||||
|
||||
Examples:
|
||||
|
||||
fsi-master {
|
||||
compatible = "fsi-master-gpio", "fsi-master";
|
||||
clock-gpios = <&gpio 0>;
|
||||
data-gpios = <&gpio 1>;
|
||||
enable-gpios = <&gpio 2>;
|
||||
trans-gpios = <&gpio 3>;
|
||||
mux-gpios = <&gpio 4>;
|
||||
}
|
5
Bindings/gpio/gpio-exar.txt
Normal file
5
Bindings/gpio/gpio-exar.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Exportable MPIO interface of Exar UART chips
|
||||
|
||||
Required properties of the device:
|
||||
- exar,first-pin: first exportable pins (0..15)
|
||||
- ngpios: number of exportable pins (1..16)
|
@ -2,17 +2,27 @@
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
|
||||
or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
|
||||
Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
|
||||
370. "marvell,mv78200-gpio" should be used for the Discovery
|
||||
MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
|
||||
SoCs (MV78230, MV78260, MV78460).
|
||||
- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
|
||||
"marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
|
||||
|
||||
"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
|
||||
Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
|
||||
should be used for the Discovery MV78200.
|
||||
|
||||
"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
|
||||
(MV78230, MV78260, MV78460).
|
||||
|
||||
"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
|
||||
SoCs (either from AP or CP), see
|
||||
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
|
||||
and
|
||||
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
|
||||
for specific details about the offset property.
|
||||
|
||||
- reg: Address and length of the register set for the device. Only one
|
||||
entry is expected, except for the "marvell,armadaxp-gpio" variant
|
||||
for which two entries are expected: one for the general registers,
|
||||
one for the per-cpu registers.
|
||||
one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
|
||||
|
||||
- interrupts: The list of interrupts that are used for all the pins
|
||||
managed by this GPIO bank. There can be more than one interrupt
|
||||
|
@ -74,11 +74,14 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
|
||||
Optional standard bitfield specifiers for the last cell:
|
||||
|
||||
- Bit 0: 0 means active high, 1 means active low
|
||||
- Bit 1: 1 means single-ended wiring, see:
|
||||
- Bit 1: 0 mean push-pull wiring, see:
|
||||
https://en.wikipedia.org/wiki/Push-pull_output
|
||||
1 means single-ended wiring, see:
|
||||
https://en.wikipedia.org/wiki/Single-ended_triode
|
||||
When used with active-low, this means open drain/collector, see:
|
||||
- Bit 2: 0 means open-source, 1 means open drain, see:
|
||||
https://en.wikipedia.org/wiki/Open_collector
|
||||
When used with active-high, this means open source/emitter
|
||||
- Bit 3: 0 means the output should be maintained during sleep/low-power mode
|
||||
1 means the output state can be lost during sleep/low-power mode
|
||||
|
||||
1.1) GPIO specifier best practices
|
||||
----------------------------------
|
||||
@ -282,8 +285,8 @@ Example 1:
|
||||
};
|
||||
|
||||
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
|
||||
pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
|
||||
pins 50..59.
|
||||
pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
|
||||
pins 50..69.
|
||||
|
||||
Example 2:
|
||||
|
||||
|
@ -5,9 +5,13 @@ Required properties:
|
||||
- reg: Should contain GPIO controller registers location and length
|
||||
- interrupts: Should be the port interrupt shared by all the pins.
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify optional parameters (currently
|
||||
unused).
|
||||
the second cell is used to specify optional parameters to declare if the GPIO
|
||||
is active high or low. See gpio.txt.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify irq type flags, see the two cell description
|
||||
in interrupt-controller/interrupts.txt for details.
|
||||
|
||||
optional properties:
|
||||
- #gpio-lines: Number of gpio if absent 32.
|
||||
@ -21,5 +25,7 @@ Example:
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-lines = <19>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
|
46
Bindings/gpio/ingenic,gpio.txt
Normal file
46
Bindings/gpio/ingenic,gpio.txt
Normal file
@ -0,0 +1,46 @@
|
||||
Ingenic jz47xx GPIO controller
|
||||
|
||||
That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
|
||||
driver node.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
|
||||
- compatible: Must contain one of:
|
||||
- "ingenic,jz4740-gpio"
|
||||
- "ingenic,jz4770-gpio"
|
||||
- "ingenic,jz4780-gpio"
|
||||
- reg: The GPIO bank number.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
- #interrupt-cells: Should be 2. Refer to
|
||||
../interrupt-controller/interrupts.txt for more details.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
|
||||
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
|
||||
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
|
||||
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
|
||||
'gpio.txt' in this directory for more details.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
&pinctrl {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpa: gpio@0 {
|
||||
compatible = "ingenic,jz4740-gpio";
|
||||
reg = <0>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <28>;
|
||||
};
|
||||
};
|
@ -3,6 +3,7 @@
|
||||
Required Properties:
|
||||
|
||||
- compatible: should contain one of the following.
|
||||
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
|
||||
|
86
Bindings/gpu/arm,mali-midgard.txt
Normal file
86
Bindings/gpu/arm,mali-midgard.txt
Normal file
@ -0,0 +1,86 @@
|
||||
ARM Mali Midgard GPU
|
||||
====================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible :
|
||||
* Must contain one of the following:
|
||||
+ "arm,mali-t604"
|
||||
+ "arm,mali-t624"
|
||||
+ "arm,mali-t628"
|
||||
+ "arm,mali-t720"
|
||||
+ "arm,mali-t760"
|
||||
+ "arm,mali-t820"
|
||||
+ "arm,mali-t830"
|
||||
+ "arm,mali-t860"
|
||||
+ "arm,mali-t880"
|
||||
* which must be preceded by one of the following vendor specifics:
|
||||
+ "amlogic,meson-gxm-mali"
|
||||
+ "rockchip,rk3288-mali"
|
||||
|
||||
- reg : Physical base address of the device and length of the register area.
|
||||
|
||||
- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
|
||||
|
||||
- interrupt-names : Contains the names of IRQ resources in the order they were
|
||||
provided in the interrupts property. Must contain: "job", "mmu", "gpu".
|
||||
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks : Phandle to clock for the Mali Midgard device.
|
||||
|
||||
- mali-supply : Phandle to regulator for the Mali device. Refer to
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt for details.
|
||||
|
||||
- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt
|
||||
for details.
|
||||
|
||||
|
||||
Example for a Mali-T760:
|
||||
|
||||
gpu@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||
reg = <0xffa30000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
mali-supply = <&vdd_gpu>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&power RK3288_PD_GPU>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp@533000000 {
|
||||
opp-hz = /bits/ 64 <533000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
opp@450000000 {
|
||||
opp-hz = /bits/ 64 <450000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
opp@350000000 {
|
||||
opp-hz = /bits/ 64 <350000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
};
|
||||
opp@266000000 {
|
||||
opp-hz = /bits/ 64 <266000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <912500>;
|
||||
};
|
||||
};
|
@ -34,7 +34,7 @@ remote device, an 'endpoint' child node must be provided for each link.
|
||||
If more than one port is present in a device node or there is more than one
|
||||
endpoint at a port, or a port node needs to be associated with a selected
|
||||
hardware interface, a common scheme using '#address-cells', '#size-cells'
|
||||
and 'reg' properties is used number the nodes.
|
||||
and 'reg' properties is used to number the nodes.
|
||||
|
||||
device {
|
||||
...
|
||||
@ -89,9 +89,9 @@ Links between endpoints
|
||||
|
||||
Each endpoint should contain a 'remote-endpoint' phandle property that points
|
||||
to the corresponding endpoint in the port of the remote device. In turn, the
|
||||
remote endpoint should contain a 'remote-endpoint' property. If it has one,
|
||||
it must not point to another than the local endpoint. Two endpoints with their
|
||||
'remote-endpoint' phandles pointing at each other form a link between the
|
||||
remote endpoint should contain a 'remote-endpoint' property. If it has one, it
|
||||
must not point to anything other than the local endpoint. Two endpoints with
|
||||
their 'remote-endpoint' phandles pointing at each other form a link between the
|
||||
containing ports.
|
||||
|
||||
device-1 {
|
||||
@ -110,13 +110,12 @@ device-2 {
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
|
||||
property is present in port and/or endpoint nodes the following properties
|
||||
are required in a relevant parent node:
|
||||
property present in the port and/or endpoint nodes then the following
|
||||
properties are required in a relevant parent node:
|
||||
|
||||
- #address-cells : number of cells required to define port/endpoint
|
||||
identifier, should be 1.
|
||||
|
23
Bindings/hwlock/sprd-hwspinlock.txt
Normal file
23
Bindings/hwlock/sprd-hwspinlock.txt
Normal file
@ -0,0 +1,23 @@
|
||||
SPRD Hardware Spinlock Device Binding
|
||||
-------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : should be "sprd,hwspinlock-r3p0".
|
||||
- reg : the register address of hwspinlock.
|
||||
- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
|
||||
hwlock, so the number of cells should be <1> here.
|
||||
- clock-names : Must contain "enable".
|
||||
- clocks : Must contain a phandle entry for the clock in clock-names, see the
|
||||
common clock bindings.
|
||||
|
||||
Please look at the generic hwlock binding for usage information for consumers,
|
||||
"Documentation/devicetree/bindings/hwlock/hwlock.txt"
|
||||
|
||||
Example of hwlock provider:
|
||||
hwspinlock@40500000 {
|
||||
compatible = "sprd,hwspinlock-r3p0";
|
||||
reg = <0 0x40500000 0 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
clock-names = "enable";
|
||||
clocks = <&clk_aon_apb_gates0 22>;
|
||||
};
|
48
Bindings/i2c/i2c-aspeed.txt
Normal file
48
Bindings/i2c/i2c-aspeed.txt
Normal file
@ -0,0 +1,48 @@
|
||||
Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs.
|
||||
|
||||
Required Properties:
|
||||
- #address-cells : should be 1
|
||||
- #size-cells : should be 0
|
||||
- reg : address offset and range of bus
|
||||
- compatible : should be "aspeed,ast2400-i2c-bus"
|
||||
or "aspeed,ast2500-i2c-bus"
|
||||
- clocks : root clock of bus, should reference the APB
|
||||
clock
|
||||
- interrupts : interrupt number
|
||||
- interrupt-parent : interrupt controller for bus, should reference a
|
||||
aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic
|
||||
interrupt controller
|
||||
|
||||
Optional Properties:
|
||||
- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
|
||||
specified
|
||||
- multi-master : states that there is another master active on this bus.
|
||||
|
||||
Example:
|
||||
|
||||
i2c {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1e78a000 0x1000>;
|
||||
|
||||
i2c_ic: interrupt-controller@0 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "aspeed,ast2400-i2c-ic";
|
||||
reg = <0x0 0x40>;
|
||||
interrupts = <12>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
i2c0: i2c-bus@40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40 0x40>;
|
||||
compatible = "aspeed,ast2400-i2c-bus";
|
||||
clocks = <&clk_apb>;
|
||||
bus-frequency = <100000>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&i2c_ic>;
|
||||
};
|
||||
};
|
@ -20,7 +20,7 @@ Optional properties :
|
||||
- i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
|
||||
This value which is by default 300ns is used to compute the tHIGH period.
|
||||
|
||||
Example :
|
||||
Examples :
|
||||
|
||||
i2c@f0000 {
|
||||
#address-cells = <1>;
|
||||
@ -43,3 +43,17 @@ Example :
|
||||
i2c-sda-falling-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
};
|
||||
|
||||
i2c@1120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <0>;
|
||||
|
||||
eeprom@64 {
|
||||
compatible = "linux,slave-24c02";
|
||||
reg = <0x40000064>;
|
||||
};
|
||||
};
|
||||
|
@ -4,11 +4,11 @@ The Mediatek's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be either of the following.
|
||||
(a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
|
||||
(b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
|
||||
(c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
|
||||
(d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
|
||||
(e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
|
||||
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
|
||||
"mediatek,mt6577-i2c": for i2c compatible with mt6577.
|
||||
"mediatek,mt6589-i2c": for i2c compatible with mt6589.
|
||||
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
|
||||
"mediatek,mt8173-i2c": for i2c compatible with mt8173.
|
||||
- reg: physical base address of the controller and dma base, length of memory
|
||||
mapped region.
|
||||
- interrupts: interrupt number to the cpu.
|
99
Bindings/i2c/i2c-mux-gpmux.txt
Normal file
99
Bindings/i2c/i2c-mux-gpmux.txt
Normal file
@ -0,0 +1,99 @@
|
||||
General Purpose I2C Bus Mux
|
||||
|
||||
This binding describes an I2C bus multiplexer that uses a mux controller
|
||||
from the mux subsystem to route the I2C signals.
|
||||
|
||||
.-----. .-----.
|
||||
| dev | | dev |
|
||||
.------------. '-----' '-----'
|
||||
| SoC | | |
|
||||
| | .--------+--------'
|
||||
| .------. | .------+ child bus A, on MUX value set to 0
|
||||
| | I2C |-|--| Mux |
|
||||
| '------' | '--+---+ child bus B, on MUX value set to 1
|
||||
| .------. | | '----------+--------+--------.
|
||||
| | MUX- | | | | | |
|
||||
| | Ctrl |-|-----+ .-----. .-----. .-----.
|
||||
| '------' | | dev | | dev | | dev |
|
||||
'------------' '-----' '-----' '-----'
|
||||
|
||||
Required properties:
|
||||
- compatible: i2c-mux
|
||||
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
|
||||
port is connected to.
|
||||
- mux-controls: The phandle of the mux controller to use for operating the
|
||||
mux.
|
||||
* Standard I2C mux properties. See i2c-mux.txt in this directory.
|
||||
* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
|
||||
is also the mux-controller state described in ../mux/mux-controller.txt
|
||||
|
||||
Optional properties:
|
||||
- mux-locked: If present, explicitly allow unrelated I2C transactions on the
|
||||
parent I2C adapter at these times:
|
||||
+ during setup of the multiplexer
|
||||
+ between setup of the multiplexer and the child bus I2C transaction
|
||||
+ between the child bus I2C transaction and releasing of the multiplexer
|
||||
+ during releasing of the multiplexer
|
||||
However, I2C transactions to devices behind all I2C multiplexers connected
|
||||
to the same parent adapter that this multiplexer is connected to are blocked
|
||||
for the full duration of the complete multiplexed I2C transaction (i.e.
|
||||
including the times covered by the above list).
|
||||
If mux-locked is not present, the multiplexer is assumed to be parent-locked.
|
||||
This means that no unrelated I2C transactions are allowed on the parent I2C
|
||||
adapter for the complete multiplexed I2C transaction.
|
||||
The properties of mux-locked and parent-locked multiplexers are discussed
|
||||
in more detail in Documentation/i2c/i2c-topology.
|
||||
|
||||
For each i2c child node, an I2C child bus will be created. They will
|
||||
be numbered based on their order in the device tree.
|
||||
|
||||
Whenever an access is made to a device on a child bus, the value set
|
||||
in the relevant node's reg property will be set as the state in the
|
||||
mux controller.
|
||||
|
||||
Example:
|
||||
mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
|
||||
<&pioA 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
i2c-mux {
|
||||
compatible = "i2c-mux";
|
||||
mux-locked;
|
||||
i2c-parent = <&i2c1>;
|
||||
|
||||
mux-controls = <&mux>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ssd1307: oled@3c {
|
||||
compatible = "solomon,ssd1307fb-i2c";
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7 1>;
|
||||
reset-active-low;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9555: pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
};
|
||||
};
|
29
Bindings/i2c/i2c-pca-platform.txt
Normal file
29
Bindings/i2c/i2c-pca-platform.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* NXP PCA PCA9564/PCA9665 I2C controller
|
||||
|
||||
The PCA9564/PCA9665 serves as an interface between most standard
|
||||
parallel-bus microcontrollers/microprocessors and the serial I2C-bus
|
||||
and allows the parallel bus system to communicate bi-directionally
|
||||
with the I2C-bus.
|
||||
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : one of "nxp,pca9564" or "nxp,pca9665"
|
||||
|
||||
Optional properties
|
||||
- interrupts : the interrupt number
|
||||
- interrupt-parent : the phandle for the interrupt controller.
|
||||
If an interrupt is not specified polling will be used.
|
||||
- reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
|
||||
is active low, it should be marked GPIO_ACTIVE_LOW.
|
||||
- clock-frequency : I2C bus frequency.
|
||||
|
||||
Example:
|
||||
i2c0: i2c@80000 {
|
||||
compatible = "nxp,pca9564";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80000 0x4>;
|
||||
reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
22
Bindings/i2c/i2c-zx2967.txt
Normal file
22
Bindings/i2c/i2c-zx2967.txt
Normal file
@ -0,0 +1,22 @@
|
||||
ZTE zx2967 I2C controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "zte,zx296718-i2c"
|
||||
- reg: physical address and length of the device registers
|
||||
- interrupts: a single interrupt specifier
|
||||
- clocks: clock for the device
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <0>
|
||||
- clock-frequency: the desired I2C bus clock frequency.
|
||||
|
||||
Examples:
|
||||
|
||||
i2c@112000 {
|
||||
compatible = "zte,zx296718-i2c";
|
||||
reg = <0x00112000 0x1000>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc24m>;
|
||||
#address-cells = <1>
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <1600000>;
|
||||
};
|
@ -2,6 +2,8 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: depending on the SoC this should be one of:
|
||||
- "amlogic,meson8-saradc" for Meson8
|
||||
- "amlogic,meson8b-saradc" for Meson8b
|
||||
- "amlogic,meson-gxbb-saradc" for GXBB
|
||||
- "amlogic,meson-gxl-saradc" for GXL
|
||||
- "amlogic,meson-gxm-saradc" for GXM
|
||||
|
@ -1,4 +1,4 @@
|
||||
* Renesas RCar GyroADC device driver
|
||||
* Renesas R-Car GyroADC device driver
|
||||
|
||||
The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
|
||||
which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
|
||||
@ -16,8 +16,7 @@ Required properties:
|
||||
- clocks: References to all the clocks specified in the clock-names
|
||||
property as specified in
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||
- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block
|
||||
clock, the "if" is the interface clock.
|
||||
- clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
|
||||
- power-domains: Must contain a reference to the PM domain, if available.
|
||||
- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
|
||||
except for "fujitsu,mb88101a". Should be <0> (setting for
|
||||
@ -75,8 +74,8 @@ Example:
|
||||
adc@e6e54000 {
|
||||
compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
|
||||
reg = <0 0xe6e54000 0 64>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>;
|
||||
clock-names = "fck", "if";
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
pinctrl-0 = <&adc_pins>;
|
||||
|
@ -21,11 +21,19 @@ own configurable sequence and trigger:
|
||||
Contents of a stm32 adc root node:
|
||||
-----------------------------------
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f4-adc-core".
|
||||
- compatible: Should be one of:
|
||||
"st,stm32f4-adc-core"
|
||||
"st,stm32h7-adc-core"
|
||||
- reg: Offset and length of the ADC block register set.
|
||||
- interrupts: Must contain the interrupt for ADC block.
|
||||
- clocks: Clock for the analog circuitry (common to all ADCs).
|
||||
- clock-names: Must be "adc".
|
||||
- clocks: Core can use up to two clocks, depending on part used:
|
||||
- "adc" clock: for the analog circuitry, common to all ADCs.
|
||||
It's required on stm32f4.
|
||||
It's optional on stm32h7.
|
||||
- "bus" clock: for registers access, common to all ADCs.
|
||||
It's not present on stm32f4.
|
||||
It's required on stm32h7.
|
||||
- clock-names: Must be "adc" and/or "bus" depending on part used.
|
||||
- interrupt-controller: Identifies the controller node as interrupt-parent
|
||||
- vref-supply: Phandle to the vref input analog reference voltage.
|
||||
- #interrupt-cells = <1>;
|
||||
@ -42,14 +50,18 @@ An ADC block node should contain at least one subnode, representing an
|
||||
ADC instance available on the machine.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f4-adc".
|
||||
- compatible: Should be one of:
|
||||
"st,stm32f4-adc"
|
||||
"st,stm32h7-adc"
|
||||
- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
|
||||
- clocks: Input clock private to this ADC instance.
|
||||
- clocks: Input clock private to this ADC instance. It's required only on
|
||||
stm32f4, that has per instance clock input for registers access.
|
||||
- interrupt-parent: Phandle to the parent interrupt controller.
|
||||
- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
|
||||
2 for adc@200).
|
||||
- st,adc-channels: List of single-ended channels muxed for this ADC.
|
||||
It can have up to 16 channels, numbered from 0 to 15 (resp. for in0..in15).
|
||||
It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
|
||||
from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
|
||||
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
|
||||
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
||||
|
||||
@ -58,7 +70,9 @@ Optional properties:
|
||||
See ../../dma/dma.txt for details.
|
||||
- dma-names: Must be "rx" when dmas property is being used.
|
||||
- assigned-resolution-bits: Resolution (bits) to use for conversions. Must
|
||||
match device available resolutions (e.g. can be 6, 8, 10 or 12 on stm32f4).
|
||||
match device available resolutions:
|
||||
* can be 6, 8, 10 or 12 on stm32f4
|
||||
* can be 8, 10, 12, 14 or 16 on stm32h7
|
||||
Default is maximum resolution if unset.
|
||||
|
||||
Example:
|
||||
|
19
Bindings/iio/adc/ti-adc084s021.txt
Normal file
19
Bindings/iio/adc/ti-adc084s021.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* Texas Instruments' ADC084S021
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "ti,adc084s021"
|
||||
- reg : SPI chip select number for the device
|
||||
- vref-supply : The regulator supply for ADC reference voltage
|
||||
- spi-cpol : Per spi-bus bindings
|
||||
- spi-cpha : Per spi-bus bindings
|
||||
- spi-max-frequency : Per spi-bus bindings
|
||||
|
||||
Example:
|
||||
adc@0 {
|
||||
compatible = "ti,adc084s021";
|
||||
reg = <0>;
|
||||
vref-supply = <&adc_vref>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
spi-max-frequency = <16000000>;
|
||||
};
|
18
Bindings/iio/adc/ti-adc108s102.txt
Normal file
18
Bindings/iio/adc/ti-adc108s102.txt
Normal file
@ -0,0 +1,18 @@
|
||||
* Texas Instruments' ADC108S102 and ADC128S102 ADC chip
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "ti,adc108s102"
|
||||
- reg: spi chip select number for the device
|
||||
- vref-supply: The regulator supply for ADC reference voltage
|
||||
|
||||
Recommended properties:
|
||||
- spi-max-frequency: Definition as per
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
Example:
|
||||
adc@0 {
|
||||
compatible = "ti,adc108s102";
|
||||
reg = <0>;
|
||||
vref-supply = <&vdd_supply>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
@ -13,7 +13,8 @@ Optional properties:
|
||||
"data ready" (valid values: 1 or 2).
|
||||
- interrupt-parent: should be the phandle for the interrupt controller
|
||||
- interrupts: interrupt mapping for IRQ. It should be configured with
|
||||
flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
|
||||
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
|
||||
IRQ_TYPE_EDGE_FALLING.
|
||||
|
||||
Refer to interrupt-controller/interrupts.txt for generic interrupt
|
||||
client node bindings.
|
||||
|
39
Bindings/iio/multiplexer/io-channel-mux.txt
Normal file
39
Bindings/iio/multiplexer/io-channel-mux.txt
Normal file
@ -0,0 +1,39 @@
|
||||
I/O channel multiplexer bindings
|
||||
|
||||
If a multiplexer is used to select which hardware signal is fed to
|
||||
e.g. an ADC channel, these bindings describe that situation.
|
||||
|
||||
Required properties:
|
||||
- compatible : "io-channel-mux"
|
||||
- io-channels : Channel node of the parent channel that has multiplexed
|
||||
input.
|
||||
- io-channel-names : Should be "parent".
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- mux-controls : Mux controller node to use for operating the mux
|
||||
- channels : List of strings, labeling the mux controller states.
|
||||
|
||||
For each non-empty string in the channels property, an io-channel will
|
||||
be created. The number of this io-channel is the same as the index into
|
||||
the list of strings in the channels property, and also matches the mux
|
||||
controller state. The mux controller state is described in
|
||||
../mux/mux-controller.txt
|
||||
|
||||
Example:
|
||||
mux: mux-controller {
|
||||
compatible = "mux-gpio";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
|
||||
<&pioA 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
adc-mux {
|
||||
compatible = "io-channel-mux";
|
||||
io-channels = <&adc 0>;
|
||||
io-channel-names = "parent";
|
||||
|
||||
mux-controls = <&mux>;
|
||||
|
||||
channels = "sync", "in", "system-regulator";
|
||||
};
|
@ -3,6 +3,7 @@ Austrian Microsystems AS3935 Franklin lightning sensor device driver
|
||||
Required properties:
|
||||
- compatible: must be "ams,as3935"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-max-frequency: specifies maximum SPI clock frequency
|
||||
- spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
|
||||
slave node bindings.
|
||||
- interrupt-parent : should be the phandle for the interrupt controller
|
||||
@ -21,6 +22,7 @@ Example:
|
||||
as3935@0 {
|
||||
compatible = "ams,as3935";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <400000>;
|
||||
spi-cpha;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <16 1>;
|
||||
|
21
Bindings/input/dlink,dir685-touchkeys.txt
Normal file
21
Bindings/input/dlink,dir685-touchkeys.txt
Normal file
@ -0,0 +1,21 @@
|
||||
* D-Link DIR-685 Touchkeys
|
||||
|
||||
This is a I2C one-off touchkey controller based on the Cypress Semiconductor
|
||||
CY8C214 MCU with some firmware in its internal 8KB flash. The circuit
|
||||
board inside the router is named E119921.
|
||||
|
||||
The touchkey device node should be placed inside an I2C bus node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "dlink,dir685-touchkeys"
|
||||
- reg: the I2C address of the touchkeys
|
||||
- interrupts: reference to the interrupt number
|
||||
|
||||
Example:
|
||||
|
||||
touchkeys@26 {
|
||||
compatible = "dlink,dir685-touchkeys";
|
||||
reg = <0x26>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
43
Bindings/input/touchscreen/st,stmfts.txt
Normal file
43
Bindings/input/touchscreen/st,stmfts.txt
Normal file
@ -0,0 +1,43 @@
|
||||
* ST-Microelectronics FingerTip touchscreen controller
|
||||
|
||||
The ST-Microelectronics FingerTip device provides a basic touchscreen
|
||||
functionality. Along with it the user can enable the touchkey which can work as
|
||||
a basic HOME and BACK key for phones.
|
||||
|
||||
The driver supports also hovering as an absolute single touch event with x, y, z
|
||||
coordinates.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "st,stmfts"
|
||||
- reg : I2C slave address, (e.g. 0x49)
|
||||
- interrupt-parent : the phandle to the interrupt controller which provides
|
||||
the interrupt
|
||||
- interrupts : interrupt specification
|
||||
- avdd-supply : analogic power supply
|
||||
- vdd-supply : power supply
|
||||
- touchscreen-size-x : see touchscreen.txt
|
||||
- touchscreen-size-y : see touchscreen.txt
|
||||
|
||||
Optional properties:
|
||||
- touch-key-connected : specifies whether the touchkey feature is connected
|
||||
- ledvdd-supply : power supply to the touch key leds
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
|
||||
/* ... */
|
||||
|
||||
touchscreen@49 {
|
||||
compatible = "st,stmfts";
|
||||
reg = <0x49>;
|
||||
interrupt-parent = <&gpa1>;
|
||||
interrupts = <1 IRQ_TYPE_NONE>;
|
||||
touchscreen-size-x = <1599>;
|
||||
touchscreen-size-y = <2559>;
|
||||
touch-key-connected;
|
||||
avdd-supply = <&ldo30_reg>;
|
||||
vdd-supply = <&ldo31_reg>;
|
||||
ledvdd-supply = <&ldo33_reg>;
|
||||
};
|
||||
};
|
@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
|
||||
"allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
|
||||
- compatible : should be one of the following:
|
||||
- "allwinner,sun7i-a20-sc-nmi"
|
||||
- "allwinner,sun6i-a31-sc-nmi" (deprecated)
|
||||
- "allwinner,sun6i-a31-r-intc"
|
||||
- "allwinner,sun9i-a80-nmi"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
|
25
Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
Normal file
25
Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Device tree configuration for the I2C Interrupt Controller on the AST24XX and
|
||||
AST25XX SoCs.
|
||||
|
||||
Required Properties:
|
||||
- #address-cells : should be 1
|
||||
- #size-cells : should be 1
|
||||
- #interrupt-cells : should be 1
|
||||
- compatible : should be "aspeed,ast2400-i2c-ic"
|
||||
or "aspeed,ast2500-i2c-ic"
|
||||
- reg : address start and range of controller
|
||||
- interrupts : interrupt number
|
||||
- interrupt-controller : denotes that the controller receives and fires
|
||||
new interrupts for child busses
|
||||
|
||||
Example:
|
||||
|
||||
i2c_ic: interrupt-controller@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "aspeed,ast2400-i2c-ic";
|
||||
reg = <0x0 0x40>;
|
||||
interrupts = <12>;
|
||||
interrupt-controller;
|
||||
};
|
@ -1,12 +1,13 @@
|
||||
Aspeed Vectored Interrupt Controller
|
||||
|
||||
These bindings are for the Aspeed AST2400 interrupt controller register layout.
|
||||
The SoC has an legacy register layout, but this driver does not support that
|
||||
mode of operation.
|
||||
These bindings are for the Aspeed interrupt controller. The AST2400 and
|
||||
AST2500 SoC families include a legacy register layout before a re-designed
|
||||
layout, but the bindings do not prescribe the use of one or the other.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "aspeed,ast2400-vic".
|
||||
- compatible : "aspeed,ast2400-vic"
|
||||
"aspeed,ast2500-vic"
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
|
27
Bindings/interrupt-controller/marvell,gicp.txt
Normal file
27
Bindings/interrupt-controller/marvell,gicp.txt
Normal file
@ -0,0 +1,27 @@
|
||||
Marvell GICP Controller
|
||||
-----------------------
|
||||
|
||||
GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
|
||||
interrupts by doing a memory transaction. It is used by the ICU
|
||||
located in the Marvell CP110 to turn wired interrupts inside the CP
|
||||
into GIC SPI interrupts.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "marvell,ap806-gicp"
|
||||
|
||||
- reg: Must be the address and size of the GICP SPI registers
|
||||
|
||||
- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
|
||||
for this GICP
|
||||
|
||||
- msi-controller: indicates that this is an MSI controller
|
||||
|
||||
Example:
|
||||
|
||||
gicp_spi: gicp-spi@3f0040 {
|
||||
compatible = "marvell,ap806-gicp";
|
||||
reg = <0x3f0040 0x10>;
|
||||
marvell,spi-ranges = <64 64>, <288 64>;
|
||||
msi-controller;
|
||||
};
|
51
Bindings/interrupt-controller/marvell,icu.txt
Normal file
51
Bindings/interrupt-controller/marvell,icu.txt
Normal file
@ -0,0 +1,51 @@
|
||||
Marvell ICU Interrupt Controller
|
||||
--------------------------------
|
||||
|
||||
The Marvell ICU (Interrupt Consolidation Unit) controller is
|
||||
responsible for collecting all wired-interrupt sources in the CP and
|
||||
communicating them to the GIC in the AP, the unit translates interrupt
|
||||
requests on input wires to MSG memory mapped transactions to the GIC.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,cp110-icu"
|
||||
|
||||
- reg: Should contain ICU registers location and length.
|
||||
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 3.
|
||||
|
||||
The 1st cell is the group type of the ICU interrupt. Possible group
|
||||
types are:
|
||||
|
||||
ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
|
||||
ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
|
||||
ICU_GRP_SEI (0x4) : System error interrupt
|
||||
ICU_GRP_REI (0x5) : RAM error interrupt
|
||||
|
||||
The 2nd cell is the index of the interrupt in the ICU unit.
|
||||
|
||||
The 3rd cell is the type of the interrupt. See arm,gic.txt for
|
||||
details.
|
||||
|
||||
- interrupt-controller: Identifies the node as an interrupt
|
||||
controller.
|
||||
|
||||
- msi-parent: Should point to the GICP controller, the GIC extension
|
||||
that allows to trigger interrupts using MSG memory mapped
|
||||
transactions.
|
||||
|
||||
Example:
|
||||
|
||||
icu: interrupt-controller@1e0000 {
|
||||
compatible = "marvell,cp110-icu";
|
||||
reg = <0x1e0000 0x10>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
msi-parent = <&gicp>;
|
||||
};
|
||||
|
||||
usb3h0: usb3@500000 {
|
||||
interrupt-parent = <&icu>;
|
||||
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
@ -1,21 +1,23 @@
|
||||
+Mediatek 65xx/67xx/81xx sysirq
|
||||
+Mediatek MT65xx/MT67xx/MT81xx sysirq
|
||||
|
||||
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
|
||||
interrupt.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
"mediatek,mt8173-sysirq"
|
||||
"mediatek,mt8135-sysirq"
|
||||
"mediatek,mt8127-sysirq"
|
||||
"mediatek,mt6795-sysirq"
|
||||
"mediatek,mt6755-sysirq"
|
||||
"mediatek,mt6592-sysirq"
|
||||
"mediatek,mt6589-sysirq"
|
||||
"mediatek,mt6582-sysirq"
|
||||
"mediatek,mt6580-sysirq"
|
||||
"mediatek,mt6577-sysirq"
|
||||
"mediatek,mt2701-sysirq"
|
||||
- compatible: should be
|
||||
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
|
||||
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
|
||||
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
|
||||
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
|
||||
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
|
||||
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
|
||||
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
|
||||
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
|
||||
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
|
||||
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
|
||||
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
|
||||
"mediatek,mt6577-sysirq": for MT6577
|
||||
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
|
||||
- interrupt-parent: phandle of irq parent for sysirq. The parent must
|
||||
|
@ -92,7 +92,6 @@ Example 2:
|
||||
|
||||
* References
|
||||
|
||||
[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
|
||||
Requirements (ePAPR), Version 1.0, July 2008.
|
||||
(http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
|
||||
[1] Devicetree Specification
|
||||
(https://www.devicetree.org/specifications/)
|
||||
|
||||
|
@ -26,6 +26,12 @@ the PCIe specification.
|
||||
* "priq" - PRI Queue not empty
|
||||
* "cmdq-sync" - CMD_SYNC complete
|
||||
* "gerror" - Global Error activated
|
||||
* "combined" - The combined interrupt is optional,
|
||||
and should only be provided if the
|
||||
hardware supports just a single,
|
||||
combined interrupt line.
|
||||
If provided, then the combined interrupt
|
||||
will be used in preference to any others.
|
||||
|
||||
- #iommu-cells : See the generic IOMMU binding described in
|
||||
devicetree/bindings/pci/pci-iommu.txt
|
||||
@ -49,6 +55,12 @@ the PCIe specification.
|
||||
- hisilicon,broken-prefetch-cmd
|
||||
: Avoid sending CMD_PREFETCH_* commands to the SMMU.
|
||||
|
||||
- cavium,cn9900-broken-page1-regspace
|
||||
: Replaces all page 1 offsets used for EVTQ_PROD/CONS,
|
||||
PRIQ_PROD/CONS register access with page 0 offsets.
|
||||
Set for Cavium ThunderX2 silicon that doesn't support
|
||||
SMMU page1 register space.
|
||||
|
||||
** Example
|
||||
|
||||
smmu@2b400000 {
|
||||
|
@ -1,4 +1,4 @@
|
||||
Common leds properties.
|
||||
* Common leds properties.
|
||||
|
||||
LED and flash LED devices provide the same basic functionality as current
|
||||
regulators, but extended with LED and flash LED specific features like
|
||||
@ -49,6 +49,22 @@ Optional properties for child nodes:
|
||||
- panic-indicator : This property specifies that the LED should be used,
|
||||
if at all possible, as a panic indicator.
|
||||
|
||||
- trigger-sources : List of devices which should be used as a source triggering
|
||||
this LED activity. Some LEDs can be related to a specific
|
||||
device and should somehow indicate its state. E.g. USB 2.0
|
||||
LED may react to device(s) in a USB 2.0 port(s).
|
||||
Another common example is switch or router with multiple
|
||||
Ethernet ports each of them having its own LED assigned
|
||||
(assuming they are not hardwired). In such cases this
|
||||
property should contain phandle(s) of related source
|
||||
device(s).
|
||||
In many cases LED can be related to more than one device
|
||||
(e.g. one USB LED vs. multiple USB ports). Each source
|
||||
should be represented by a node in the device tree and be
|
||||
referenced by a phandle and a set of phandle arguments. A
|
||||
length of arguments should be specified by the
|
||||
#trigger-source-cells property in the source node.
|
||||
|
||||
Required properties for flash LED child nodes:
|
||||
- flash-max-microamp : Maximum flash LED supply current in microamperes.
|
||||
- flash-max-timeout-us : Maximum timeout in microseconds after which the flash
|
||||
@ -59,7 +75,17 @@ property can be omitted.
|
||||
For controllers that have no configurable timeout the flash-max-timeout-us
|
||||
property can be omitted.
|
||||
|
||||
Examples:
|
||||
* Trigger source providers
|
||||
|
||||
Each trigger source should be represented by a device tree node. It may be e.g.
|
||||
a USB port or an Ethernet device.
|
||||
|
||||
Required properties for trigger source:
|
||||
- #trigger-source-cells : Number of cells in a source trigger. Typically 0 for
|
||||
nodes of simple trigger sources (e.g. a specific USB
|
||||
port).
|
||||
|
||||
* Examples
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
@ -69,6 +95,11 @@ gpio-leds {
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb {
|
||||
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||
trigger-sources = <&ohci_port1>, <&ehci_port1>;
|
||||
};
|
||||
};
|
||||
|
||||
max77693-led {
|
||||
|
@ -10,6 +10,7 @@ Optional properties:
|
||||
- nxp,period-scale : In some configurations, the chip blinks faster than expected.
|
||||
This parameter provides a scaling ratio (fixed point, decimal divided
|
||||
by 1000) to compensate, e.g. 1300=1.3x and 750=0.75x.
|
||||
- nxp,inverted-out: invert the polarity of the generated PWM
|
||||
|
||||
Each led is represented as a sub-node of the nxp,pca963x device.
|
||||
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user