Sort the ARM atomic functions to be in alphabetical order.
Sponsored by: ABT Systems Ltd
This commit is contained in:
Andrew Turner
parent
a8e1bc2e14
commit
d6a2102846
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=285687
@ -89,15 +89,15 @@ __swp(uint32_t val, volatile uint32_t *ptr)
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#define ARM_HAVE_ATOMIC64
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*address |= setmask);
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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atomic_set_64(volatile uint64_t *address, uint64_t setmask)
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atomic_add_64(volatile u_int64_t *p, u_int64_t val)
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{
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__with_interrupts_disabled(*address |= setmask);
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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@ -146,29 +146,6 @@ atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_in
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return (ret);
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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atomic_add_64(volatile u_int64_t *p, u_int64_t val)
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{
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p -= val);
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}
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static __inline void
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atomic_subtract_64(volatile u_int64_t *p, u_int64_t val)
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{
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__with_interrupts_disabled(*p -= val);
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}
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
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@ -205,39 +182,38 @@ atomic_load_64(volatile uint64_t *p)
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return (value);
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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__with_interrupts_disabled(*address |= setmask);
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}
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static __inline void
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atomic_set_64(volatile uint64_t *address, uint64_t setmask)
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{
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__with_interrupts_disabled(*address |= setmask);
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}
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static __inline void
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atomic_store_64(volatile uint64_t *p, uint64_t value)
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{
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__with_interrupts_disabled(*p = value);
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}
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#else /* !_KERNEL */
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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register int done, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"cmp %1, %3\n"
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"streq %4, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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"moveq %1, #1\n"
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"movne %1, #0\n"
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: "+r" (ras_start), "=r" (done)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory");
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return (done);
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__with_interrupts_disabled(*p -= val);
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}
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static __inline void
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atomic_subtract_64(volatile u_int64_t *p, u_int64_t val)
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{
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__with_interrupts_disabled(*p -= val);
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}
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#else /* !_KERNEL */
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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@ -260,52 +236,6 @@ atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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: : "memory");
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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int start, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"sub %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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: "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
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: : "memory");
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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int start, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"orr %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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: "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
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: : "memory");
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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{
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@ -329,6 +259,31 @@ atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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}
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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register int done, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"cmp %1, %3\n"
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"streq %4, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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"moveq %1, #1\n"
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"movne %1, #0\n"
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: "+r" (ras_start), "=r" (done)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory");
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return (done);
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}
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
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{
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@ -353,8 +308,53 @@ atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
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return (start);
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}
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#endif /* _KERNEL */
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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int start, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"orr %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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: "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
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: : "memory");
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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int start, ras_start = ARM_RAS_START;
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__asm __volatile("1:\n"
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"adr %1, 1b\n"
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"str %1, [%0]\n"
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"adr %1, 2f\n"
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"str %1, [%0, #4]\n"
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"ldr %1, [%2]\n"
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"sub %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"mov %1, #0xffffffff\n"
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"str %1, [%0, #4]\n"
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: "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
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: : "memory");
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}
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#endif /* _KERNEL */
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static __inline uint32_t
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atomic_readandclear_32(volatile u_int32_t *p)
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@ -61,29 +61,18 @@
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#define ARM_HAVE_ATOMIC64
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static __inline void
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__do_dmb(void)
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{
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#if __ARM_ARCH >= 7
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__asm __volatile("dmb" : : : "memory");
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#else
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__asm __volatile("mcr p15, 0, r0, c7, c10, 5" : : : "memory");
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#endif
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}
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#define ATOMIC_ACQ_REL_LONG(NAME) \
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static __inline void \
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atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \
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{ \
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atomic_##NAME##_long(p, v); \
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__do_dmb(); \
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dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \
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{ \
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__do_dmb(); \
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dmb(); \
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atomic_##NAME##_long(p, v); \
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}
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@ -92,34 +81,34 @@ static __inline void \
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atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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atomic_##NAME##_##WIDTH(p, v); \
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__do_dmb(); \
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dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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__do_dmb(); \
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dmb(); \
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atomic_##NAME##_##WIDTH(p, v); \
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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atomic_add_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"orr %0, %0, %3\n"
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"add %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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, "+r" (address), "+r" (setmask) : : "cc", "memory");
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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static __inline void
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atomic_set_64(volatile uint64_t *p, uint64_t val)
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atomic_add_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t tmp;
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uint32_t exflag;
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@ -127,8 +116,8 @@ atomic_set_64(volatile uint64_t *p, uint64_t val)
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n"
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" orr %Q[tmp], %Q[val]\n"
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" orr %R[tmp], %R[val]\n"
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" adds %Q[tmp], %Q[val]\n"
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" adc %R[tmp], %R[tmp], %R[val]\n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
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" teq %[exf], #0\n"
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" it ne \n"
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@ -141,21 +130,16 @@ atomic_set_64(volatile uint64_t *p, uint64_t val)
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}
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static __inline void
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atomic_set_long(volatile u_long *address, u_long setmask)
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atomic_add_long(volatile u_long *p, u_long val)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"orr %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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, "+r" (address), "+r" (setmask) : : "cc", "memory");
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atomic_add_32((volatile uint32_t *)p, val);
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}
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ATOMIC_ACQ_REL(add, 32)
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ATOMIC_ACQ_REL(add, 64)
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ATOMIC_ACQ_REL_LONG(add)
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t setmask)
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{
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@ -196,20 +180,16 @@ atomic_clear_64(volatile uint64_t *p, uint64_t val)
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static __inline void
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atomic_clear_long(volatile u_long *address, u_long setmask)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"bic %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (address), "+r" (setmask) : : "cc", "memory");
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atomic_clear_32((volatile uint32_t *)address, setmask);
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}
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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ATOMIC_ACQ_REL(clear, 32)
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ATOMIC_ACQ_REL(clear, 64)
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ATOMIC_ACQ_REL_LONG(clear)
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static __inline uint32_t
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atomic_cmpset_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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uint32_t ret;
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@ -260,96 +240,227 @@ atomic_cmpset_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
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}
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static __inline u_long
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atomic_cmpset_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
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atomic_cmpset_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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u_long ret;
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__asm __volatile("1: ldrex %0, [%1]\n"
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"cmp %0, %2\n"
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"itt ne\n"
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"movne %0, #0\n"
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"bne 2f\n"
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"strex %0, %3, [%1]\n"
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"cmp %0, #0\n"
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"ite eq\n"
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"moveq %0, #1\n"
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"bne 1b\n"
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"2:"
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: "=&r" (ret)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc",
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"memory");
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return (ret);
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return (atomic_cmpset_32((volatile uint32_t *)p, cmpval, newval));
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}
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static __inline u_int32_t
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atomic_cmpset_acq_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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static __inline uint32_t
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atomic_cmpset_acq_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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u_int32_t ret = atomic_cmpset_32(p, cmpval, newval);
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uint32_t ret;
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__do_dmb();
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ret = atomic_cmpset_32(p, cmpval, newval);
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dmb();
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return (ret);
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}
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static __inline uint64_t
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atomic_cmpset_acq_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval)
|
||||
atomic_cmpset_acq_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
|
||||
{
|
||||
uint64_t ret = atomic_cmpset_64(p, cmpval, newval);
|
||||
uint64_t ret;
|
||||
|
||||
__do_dmb();
|
||||
ret = atomic_cmpset_64(p, cmpval, newval);
|
||||
dmb();
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_cmpset_acq_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
|
||||
atomic_cmpset_acq_long(volatile u_long *p, u_long cmpval, u_long newval)
|
||||
{
|
||||
u_long ret = atomic_cmpset_long(p, cmpval, newval);
|
||||
u_long ret;
|
||||
|
||||
__do_dmb();
|
||||
ret = atomic_cmpset_long(p, cmpval, newval);
|
||||
dmb();
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_int32_t
|
||||
atomic_cmpset_rel_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
|
||||
static __inline uint32_t
|
||||
atomic_cmpset_rel_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
dmb();
|
||||
return (atomic_cmpset_32(p, cmpval, newval));
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_cmpset_rel_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval)
|
||||
atomic_cmpset_rel_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
dmb();
|
||||
return (atomic_cmpset_64(p, cmpval, newval));
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_cmpset_rel_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
|
||||
atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
|
||||
dmb();
|
||||
return (atomic_cmpset_long(p, cmpval, newval));
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
uint32_t tmp = 0, tmp2 = 0, ret = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"add %1, %0, %4\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "+r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
uint64_t ret, tmp;
|
||||
uint32_t exflag;
|
||||
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" adds %Q[tmp], %Q[ret], %Q[val]\n"
|
||||
" adc %R[tmp], %R[ret], %R[val]\n"
|
||||
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" teq %[exf], #0\n"
|
||||
" it ne \n"
|
||||
" bne 1b\n"
|
||||
: [ret] "=&r" (ret),
|
||||
[exf] "=&r" (exflag),
|
||||
[tmp] "=&r" (tmp)
|
||||
: [ptr] "r" (p),
|
||||
[val] "r" (val)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_fetchadd_long(volatile u_long *p, u_long val)
|
||||
{
|
||||
|
||||
return (atomic_fetchadd_32((volatile uint32_t *)p, val));
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_load_acq_32(volatile uint32_t *p)
|
||||
{
|
||||
uint32_t v;
|
||||
|
||||
v = *p;
|
||||
dmb();
|
||||
return (v);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_load_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
/*
|
||||
* The only way to atomically load 64 bits is with LDREXD which puts the
|
||||
* exclusive monitor into the exclusive state, so reset it to open state
|
||||
* with CLREX because we don't actually need to store anything.
|
||||
*/
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[ret], %R[ret], [%[ptr]]\n"
|
||||
" clrex \n"
|
||||
: [ret] "=&r" (ret)
|
||||
: [ptr] "r" (p)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_load_acq_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
ret = atomic_load_64(p);
|
||||
dmb();
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_load_acq_long(volatile u_long *p)
|
||||
{
|
||||
u_long v;
|
||||
|
||||
v = *p;
|
||||
dmb();
|
||||
return (v);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_readandclear_32(volatile uint32_t *p)
|
||||
{
|
||||
uint32_t ret, tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"mov %1, #0\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_readandclear_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret, tmp;
|
||||
uint32_t exflag;
|
||||
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[ret], %R[ret], [%[ptr]]\n"
|
||||
" mov %Q[tmp], #0\n"
|
||||
" mov %R[tmp], #0\n"
|
||||
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" teq %[exf], #0\n"
|
||||
" it ne \n"
|
||||
" bne 1b\n"
|
||||
: [ret] "=&r" (ret),
|
||||
[exf] "=&r" (exflag),
|
||||
[tmp] "=&r" (tmp)
|
||||
: [ptr] "r" (p)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_readandclear_long(volatile u_long *p)
|
||||
{
|
||||
|
||||
return (atomic_readandclear_32((volatile uint32_t *)p));
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_add_32(volatile u_int32_t *p, u_int32_t val)
|
||||
atomic_set_32(volatile uint32_t *address, uint32_t setmask)
|
||||
{
|
||||
uint32_t tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%2]\n"
|
||||
"add %0, %0, %3\n"
|
||||
"orr %0, %0, %3\n"
|
||||
"strex %1, %0, [%2]\n"
|
||||
"cmp %1, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
, "+r" (address), "+r" (setmask) : : "cc", "memory");
|
||||
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_add_64(volatile uint64_t *p, uint64_t val)
|
||||
atomic_set_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
uint64_t tmp;
|
||||
uint32_t exflag;
|
||||
@ -357,8 +468,8 @@ atomic_add_64(volatile uint64_t *p, uint64_t val)
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" adds %Q[tmp], %Q[val]\n"
|
||||
" adc %R[tmp], %R[tmp], %R[val]\n"
|
||||
" orr %Q[tmp], %Q[val]\n"
|
||||
" orr %R[tmp], %R[val]\n"
|
||||
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" teq %[exf], #0\n"
|
||||
" it ne \n"
|
||||
@ -371,22 +482,18 @@ atomic_add_64(volatile uint64_t *p, uint64_t val)
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_add_long(volatile u_long *p, u_long val)
|
||||
atomic_set_long(volatile u_long *address, u_long setmask)
|
||||
{
|
||||
u_long tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%2]\n"
|
||||
"add %0, %0, %3\n"
|
||||
"strex %1, %0, [%2]\n"
|
||||
"cmp %1, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
atomic_set_32((volatile uint32_t *)address, setmask);
|
||||
}
|
||||
|
||||
ATOMIC_ACQ_REL(set, 32)
|
||||
ATOMIC_ACQ_REL(set, 64)
|
||||
ATOMIC_ACQ_REL_LONG(set)
|
||||
|
||||
static __inline void
|
||||
atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
|
||||
atomic_subtract_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
uint32_t tmp = 0, tmp2 = 0;
|
||||
|
||||
@ -425,160 +532,13 @@ atomic_subtract_64(volatile uint64_t *p, uint64_t val)
|
||||
static __inline void
|
||||
atomic_subtract_long(volatile u_long *p, u_long val)
|
||||
{
|
||||
u_long tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%2]\n"
|
||||
"sub %0, %0, %3\n"
|
||||
"strex %1, %0, [%2]\n"
|
||||
"cmp %1, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
atomic_subtract_32((volatile uint32_t *)p, val);
|
||||
}
|
||||
|
||||
ATOMIC_ACQ_REL(clear, 32)
|
||||
ATOMIC_ACQ_REL(add, 32)
|
||||
ATOMIC_ACQ_REL(subtract, 32)
|
||||
ATOMIC_ACQ_REL(set, 32)
|
||||
ATOMIC_ACQ_REL(clear, 64)
|
||||
ATOMIC_ACQ_REL(add, 64)
|
||||
ATOMIC_ACQ_REL(subtract, 64)
|
||||
ATOMIC_ACQ_REL(set, 64)
|
||||
ATOMIC_ACQ_REL_LONG(clear)
|
||||
ATOMIC_ACQ_REL_LONG(add)
|
||||
ATOMIC_ACQ_REL_LONG(subtract)
|
||||
ATOMIC_ACQ_REL_LONG(set)
|
||||
|
||||
#undef ATOMIC_ACQ_REL
|
||||
#undef ATOMIC_ACQ_REL_LONG
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
uint32_t tmp = 0, tmp2 = 0, ret = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"add %1, %0, %4\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "+r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_readandclear_32(volatile u_int32_t *p)
|
||||
{
|
||||
uint32_t ret, tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"mov %1, #0\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_load_acq_32(volatile uint32_t *p)
|
||||
{
|
||||
uint32_t v;
|
||||
|
||||
v = *p;
|
||||
__do_dmb();
|
||||
return (v);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_32(volatile uint32_t *p, uint32_t v)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
*p = v;
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
uint64_t ret, tmp;
|
||||
uint32_t exflag;
|
||||
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" adds %Q[tmp], %Q[ret], %Q[val]\n"
|
||||
" adc %R[tmp], %R[ret], %R[val]\n"
|
||||
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" teq %[exf], #0\n"
|
||||
" it ne \n"
|
||||
" bne 1b\n"
|
||||
: [ret] "=&r" (ret),
|
||||
[exf] "=&r" (exflag),
|
||||
[tmp] "=&r" (tmp)
|
||||
: [ptr] "r" (p),
|
||||
[val] "r" (val)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_readandclear_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret, tmp;
|
||||
uint32_t exflag;
|
||||
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[ret], %R[ret], [%[ptr]]\n"
|
||||
" mov %Q[tmp], #0\n"
|
||||
" mov %R[tmp], #0\n"
|
||||
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n"
|
||||
" teq %[exf], #0\n"
|
||||
" it ne \n"
|
||||
" bne 1b\n"
|
||||
: [ret] "=&r" (ret),
|
||||
[exf] "=&r" (exflag),
|
||||
[tmp] "=&r" (tmp)
|
||||
: [ptr] "r" (p)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_load_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
/*
|
||||
* The only way to atomically load 64 bits is with LDREXD which puts the
|
||||
* exclusive monitor into the exclusive state, so reset it to open state
|
||||
* with CLREX because we don't actually need to store anything.
|
||||
*/
|
||||
__asm __volatile(
|
||||
"1: \n"
|
||||
" ldrexd %Q[ret], %R[ret], [%[ptr]]\n"
|
||||
" clrex \n"
|
||||
: [ret] "=&r" (ret)
|
||||
: [ptr] "r" (p)
|
||||
: "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_load_acq_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
ret = atomic_load_64(p);
|
||||
__do_dmb();
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_64(volatile uint64_t *p, uint64_t val)
|
||||
@ -605,62 +565,31 @@ atomic_store_64(volatile uint64_t *p, uint64_t val)
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_32(volatile uint32_t *p, uint32_t v)
|
||||
{
|
||||
|
||||
dmb();
|
||||
*p = v;
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
dmb();
|
||||
atomic_store_64(p, val);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_fetchadd_long(volatile u_long *p, u_long val)
|
||||
{
|
||||
u_long tmp = 0, tmp2 = 0, ret = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"add %1, %0, %4\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "+r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p), "+r" (val) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_readandclear_long(volatile u_long *p)
|
||||
{
|
||||
u_long ret, tmp = 0, tmp2 = 0;
|
||||
|
||||
__asm __volatile("1: ldrex %0, [%3]\n"
|
||||
"mov %1, #0\n"
|
||||
"strex %2, %1, [%3]\n"
|
||||
"cmp %2, #0\n"
|
||||
"it ne\n"
|
||||
"bne 1b\n"
|
||||
: "=r" (ret), "=&r" (tmp), "+r" (tmp2)
|
||||
,"+r" (p) : : "cc", "memory");
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline u_long
|
||||
atomic_load_acq_long(volatile u_long *p)
|
||||
{
|
||||
u_long v;
|
||||
|
||||
v = *p;
|
||||
__do_dmb();
|
||||
return (v);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_long(volatile u_long *p, u_long v)
|
||||
{
|
||||
|
||||
__do_dmb();
|
||||
dmb();
|
||||
*p = v;
|
||||
}
|
||||
|
||||
#undef ATOMIC_ACQ_REL
|
||||
#undef ATOMIC_ACQ_REL_LONG
|
||||
|
||||
#endif /* _MACHINE_ATOMIC_V6_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user