Overhaul link state change handling. Previously sis(4) blindly
configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
This commit is contained in:
Pyun YongHyeon
parent
0f7a0ebd59
commit
d7b57e79e5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=212116
@ -697,10 +697,86 @@ static void
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sis_miibus_statchg(device_t dev)
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{
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struct sis_softc *sc;
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struct mii_data *mii;
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struct ifnet *ifp;
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uint32_t reg;
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sc = device_get_softc(dev);
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SIS_LOCK_ASSERT(sc);
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sis_initl(sc);
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mii = device_get_softc(sc->sis_miibus);
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ifp = sc->sis_ifp;
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if (mii == NULL || ifp == NULL ||
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(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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sc->sis_link = 0;
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if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
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(IFM_ACTIVE | IFM_AVALID)) {
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switch (IFM_SUBTYPE(mii->mii_media_active)) {
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case IFM_10_T:
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sc->sis_link++;
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
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break;
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case IFM_100_TX:
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sc->sis_link++;
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
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break;
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default:
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break;
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}
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}
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if (sc->sis_link == 0) {
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/*
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* Stopping MACs seem to reset SIS_TX_LISTPTR and
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* SIS_RX_LISTPTR which in turn requires resetting
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* TX/RX buffers. So just don't do anything for
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* lost link.
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*/
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return;
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}
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/* Set full/half duplex mode. */
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if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
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SIS_SETBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
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SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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} else {
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SIS_CLRBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
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SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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}
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if (sc->sis_type == SIS_TYPE_83816) {
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/*
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* MPII03.D: Half Duplex Excessive Collisions.
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* Also page 49 in 83816 manual
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*/
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SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
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}
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if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
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IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
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/*
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* Short Cable Receive Errors (MP21.E)
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*/
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
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reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
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CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
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DELAY(100);
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reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
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if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
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device_printf(sc->sis_dev,
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"Applying short cable fix (reg=%x)\n", reg);
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CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
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SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
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}
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
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}
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/* Enable TX/RX MACs. */
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SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
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SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
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}
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static uint32_t
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@ -1613,23 +1689,14 @@ sis_tick(void *xsc)
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sc = xsc;
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SIS_LOCK_ASSERT(sc);
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sc->in_tick = 1;
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ifp = sc->sis_ifp;
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mii = device_get_softc(sc->sis_miibus);
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mii_tick(mii);
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sis_watchdog(sc);
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if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
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sc->sis_link++;
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if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
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sis_startl(ifp);
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}
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if (sc->sis_link == 0)
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sis_miibus_statchg(sc->sis_dev);
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callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
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sc->in_tick = 0;
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}
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#ifdef DEVICE_POLLING
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@ -1693,9 +1760,6 @@ sis_intr(void *arg)
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sc = arg;
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ifp = sc->sis_ifp;
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if (sc->sis_stopped) /* Most likely shared interrupt */
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return;
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SIS_LOCK(sc);
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#ifdef DEVICE_POLLING
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if (ifp->if_capenable & IFCAP_POLLING) {
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@ -1704,17 +1768,17 @@ sis_intr(void *arg)
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}
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#endif
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/* Reading the ISR register clears all interrupts. */
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status = CSR_READ_4(sc, SIS_ISR);
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if ((status & SIS_INTRS) == 0) {
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/* Not ours. */
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SIS_UNLOCK(sc);
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}
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/* Disable interrupts. */
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CSR_WRITE_4(sc, SIS_IER, 0);
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for (;;) {
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SIS_LOCK_ASSERT(sc);
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/* Reading the ISR register clears all interrupts. */
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status = CSR_READ_4(sc, SIS_ISR);
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if ((status & SIS_INTRS) == 0)
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break;
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for (;(status & SIS_INTRS) != 0;) {
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if (status &
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(SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
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SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
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@ -1733,7 +1797,10 @@ sis_intr(void *arg)
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if (status & SIS_ISR_SYSERR) {
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sis_reset(sc);
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sis_initl(sc);
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SIS_UNLOCK(sc);
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return;
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}
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status = CSR_READ_4(sc, SIS_ISR);
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}
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/* Re-enable interrupts. */
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@ -1908,7 +1975,6 @@ sis_initl(struct sis_softc *sc)
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* Cancel pending I/O and free all RX/TX buffers.
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*/
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sis_stop(sc);
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sc->sis_stopped = 0;
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#ifdef notyet
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if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
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@ -1972,7 +2038,6 @@ sis_initl(struct sis_softc *sc)
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
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}
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/*
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* For the NatSemi chip, we have to explicitly enable the
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* reception of ARP frames, as well as turn on the 'perfect
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@ -2030,52 +2095,11 @@ sis_initl(struct sis_softc *sc)
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/* Accept Long Packets for VLAN support */
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SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
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/* Set TX configuration */
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
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} else {
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
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}
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/* Set full/half duplex mode. */
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
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SIS_SETBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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} else {
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SIS_CLRBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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}
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if (sc->sis_type == SIS_TYPE_83816) {
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/*
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* MPII03.D: Half Duplex Excessive Collisions.
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* Also page 49 in 83816 manual
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*/
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SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
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}
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if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
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IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
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uint32_t reg;
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/*
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* Short Cable Receive Errors (MP21.E)
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*/
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
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reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
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CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
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DELAY(100);
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reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
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if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
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device_printf(sc->sis_dev,
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"Applying short cable fix (reg=%x)\n", reg);
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CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
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SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
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}
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
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}
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/*
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* Assume 100Mbps link, actual MAC configuration is done
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* after getting a valid link.
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*/
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
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/*
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* Enable interrupts.
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@ -2092,19 +2116,16 @@ sis_initl(struct sis_softc *sc)
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#endif
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CSR_WRITE_4(sc, SIS_IER, 1);
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/* Enable receiver and transmitter. */
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SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
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SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
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/* Clear MAC disable. */
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SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
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#ifdef notdef
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sc->sis_link = 0;
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mii_mediachg(mii);
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#endif
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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if (!sc->in_tick)
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callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
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callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
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}
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/*
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@ -2226,10 +2247,6 @@ sis_watchdog(struct sis_softc *sc)
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{
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SIS_LOCK_ASSERT(sc);
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if (sc->sis_stopped) {
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SIS_UNLOCK(sc);
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return;
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}
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if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
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return;
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@ -2257,9 +2274,8 @@ sis_stop(struct sis_softc *sc)
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struct sis_txdesc *txd;
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int i;
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if (sc->sis_stopped)
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return;
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SIS_LOCK_ASSERT(sc);
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ifp = sc->sis_ifp;
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sc->sis_watchdog_timer = 0;
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@ -2303,8 +2319,6 @@ sis_stop(struct sis_softc *sc)
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txd->tx_m = NULL;
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}
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}
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sc->sis_stopped = 1;
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}
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/*
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@ -471,11 +471,9 @@ struct sis_softc {
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bus_addr_t sis_tx_paddr;
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struct callout sis_stat_ch;
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int sis_watchdog_timer;
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int sis_stopped;
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#ifdef DEVICE_POLLING
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int rxcycles;
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#endif
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int in_tick;
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struct mtx sis_mtx;
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};
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