MFC 198433:
Not all Intel Core (TM) CPUs implement PMC_CLASS_IAF fixed-function counters. For such CPUs, use an alternate mapping of convenience names to events supported by PMC_CLASS_IAP programmable counters.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/stable/8/; revision=200233
@ -442,6 +442,10 @@ static struct pmc_event_alias core_aliases[] = {
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/*
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/*
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* Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
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* Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
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* and Atom (Family 6, model 1CH) PMCs.
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* and Atom (Family 6, model 1CH) PMCs.
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*
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* We map aliases to events on the fixed-function counters if these
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* are present. Note that not all CPUs in this family contain fixed-function
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* counters.
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*/
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*/
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static struct pmc_event_alias core2_aliases[] = {
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static struct pmc_event_alias core2_aliases[] = {
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@ -454,8 +458,22 @@ static struct pmc_event_alias core2_aliases[] = {
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EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
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EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
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EV_ALIAS(NULL, NULL)
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EV_ALIAS(NULL, NULL)
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};
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};
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#define atom_aliases core2_aliases
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#define corei7_aliases core2_aliases
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static struct pmc_event_alias core2_aliases_without_iaf[] = {
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EV_ALIAS("branches", "iap-br-inst-retired.any"),
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EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
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EV_ALIAS("cycles", "tsc-tsc"),
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EV_ALIAS("ic-misses", "iap-l1i-misses"),
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EV_ALIAS("instructions", "iap-inst-retired.any_p"),
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EV_ALIAS("interrupts", "iap-hw-int-rcv"),
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EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
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EV_ALIAS(NULL, NULL)
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};
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#define atom_aliases core2_aliases
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#define atom_aliases_without_iaf core2_aliases_without_iaf
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#define corei7_aliases core2_aliases
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#define corei7_aliases_without_iaf core2_aliases_without_iaf
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#define IAF_KW_OS "os"
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#define IAF_KW_OS "os"
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#define IAF_KW_USR "usr"
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#define IAF_KW_USR "usr"
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@ -2379,6 +2397,10 @@ pmc_init(void)
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uint32_t abi_version;
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uint32_t abi_version;
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struct module_stat pmc_modstat;
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struct module_stat pmc_modstat;
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struct pmc_op_getcpuinfo op_cpu_info;
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struct pmc_op_getcpuinfo op_cpu_info;
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#if defined(__amd64__) || defined(__i386__)
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int cpu_has_iaf_counters;
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unsigned int t;
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#endif
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if (pmc_syscall != -1) /* already inited */
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if (pmc_syscall != -1) /* already inited */
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return (0);
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return (0);
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@ -2420,6 +2442,8 @@ pmc_init(void)
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if (pmc_class_table == NULL)
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if (pmc_class_table == NULL)
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return (-1);
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return (-1);
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for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
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pmc_class_table[n] = NULL;
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/*
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/*
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* Fill in the class table.
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* Fill in the class table.
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@ -2427,6 +2451,14 @@ pmc_init(void)
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n = 0;
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n = 0;
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#if defined(__amd64__) || defined(__i386__)
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#if defined(__amd64__) || defined(__i386__)
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pmc_class_table[n++] = &tsc_class_table_descr;
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pmc_class_table[n++] = &tsc_class_table_descr;
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/*
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* Check if this CPU has fixed function counters.
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*/
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cpu_has_iaf_counters = 0;
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for (t = 0; t < cpu_info.pm_nclass; t++)
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if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF)
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cpu_has_iaf_counters = 1;
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#endif
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#endif
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#define PMC_MDEP_INIT(C) do { \
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#define PMC_MDEP_INIT(C) do { \
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@ -2436,6 +2468,16 @@ pmc_init(void)
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PMC_TABLE_SIZE(C##_pmc_classes); \
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PMC_TABLE_SIZE(C##_pmc_classes); \
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} while (0)
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} while (0)
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#define PMC_MDEP_INIT_INTEL_V2(C) do { \
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PMC_MDEP_INIT(C); \
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if (cpu_has_iaf_counters) \
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pmc_class_table[n++] = &iaf_class_table_descr; \
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else \
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pmc_mdep_event_aliases = \
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C##_aliases_without_iaf; \
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pmc_class_table[n] = &C##_class_table_descr; \
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} while (0)
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/* Configure the event name parser. */
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/* Configure the event name parser. */
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switch (cpu_info.pm_cputype) {
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switch (cpu_info.pm_cputype) {
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#if defined(__i386__)
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#if defined(__i386__)
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@ -2461,24 +2503,17 @@ pmc_init(void)
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pmc_class_table[n] = &k8_class_table_descr;
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pmc_class_table[n] = &k8_class_table_descr;
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break;
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break;
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM:
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PMC_MDEP_INIT(atom);
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PMC_MDEP_INIT_INTEL_V2(atom);
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pmc_class_table[n++] = &iaf_class_table_descr;
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pmc_class_table[n] = &atom_class_table_descr;
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break;
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break;
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE:
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PMC_MDEP_INIT(core);
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PMC_MDEP_INIT(core);
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pmc_class_table[n] = &core_class_table_descr;
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break;
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break;
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_CORE2EXTREME:
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PMC_MDEP_INIT(core2);
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PMC_MDEP_INIT_INTEL_V2(core2);
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pmc_class_table[n++] = &iaf_class_table_descr;
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pmc_class_table[n] = &core2_class_table_descr;
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break;
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break;
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_COREI7:
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PMC_MDEP_INIT(corei7);
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PMC_MDEP_INIT_INTEL_V2(corei7);
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pmc_class_table[n++] = &iaf_class_table_descr;
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pmc_class_table[n] = &corei7_class_table_descr;
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break;
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break;
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case PMC_CPU_INTEL_PIV:
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case PMC_CPU_INTEL_PIV:
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PMC_MDEP_INIT(p4);
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PMC_MDEP_INIT(p4);
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