arm64: allwinner: a64: Add TCON clock
The tcon clock need a mux table for it's parent, for now just list the parents twice.
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d83a581cad
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=344895
@ -640,6 +640,15 @@ NM_CLK(de_clk,
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
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/* TCON0/1 Needs mux table */
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static const char *tcon1_parents[] = {"pll_video0", "pll_video0", "pll_video1"};
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NM_CLK(tcon1_clk,
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CLK_TCON1, "tcon1", tcon1_parents,
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0x11C,
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0, 0, 1, AW_CLK_FACTOR_FIXED,
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0, 4, 0, 0,
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24, 2,
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31,
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AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
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static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
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NM_CLK(deinterlace_clk,
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@ -736,6 +745,7 @@ static struct aw_ccung_clk a64_ccu_clks[] = {
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{ .type = AW_CLK_NM, .clk.nm = &spdif_clk},
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{ .type = AW_CLK_NM, .clk.nm = &dram_clk},
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{ .type = AW_CLK_NM, .clk.nm = &de_clk},
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{ .type = AW_CLK_NM, .clk.nm = &tcon1_clk},
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{ .type = AW_CLK_NM, .clk.nm = &deinterlace_clk},
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{ .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk},
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{ .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk},
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