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Update for the Intel 10G driver, this adds support for

Browse Source 
newest hardware, adds multiqueue tx interface, infrastructure
cleanup to allow up to 32 MSIX vectors on newer Nehalem systems.
Bug fixes, etc.
This commit is contained in:
Jack F Vogel 2009-06-24 18:27:07 +00:00
parent 4a71a9f6bc
commit d8602bb9a7
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=194875
12 changed files with 1282 additions and 687 deletions
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1297
sys/dev/ixgbe/ixgbe.c
View File

File diff suppressed because it is too large Load Diff

81
sys/dev/ixgbe/ixgbe.h
View File

@ -39,6 +39,9 @@
#include <sys/param.h>
#include <sys/systm.h>
#if __FreeBSD_version >= 800000
#include <sys/buf_ring.h>
#endif
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
@ -83,10 +86,11 @@
#include <sys/endian.h>
#include <sys/taskqueue.h>
#include <sys/pcpu.h>
#include <sys/smp.h>
#include <machine/smp.h>
#ifdef IXGBE_TIMESYNC
#include <sys/ioccom.h>
#include <sys/time.h>
#ifdef IXGBE_IEEE1588
#include <sys/ieee1588.h>
#endif
#include "ixgbe_api.h"
@ -171,11 +175,10 @@
#define IXGBE_TSO_SIZE 65535
#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
#define IXGBE_RX_HDR 128
#define IXGBE_VFTA_SIZE 128
#define IXGBE_BR_SIZE 4096
#define CSUM_OFFLOAD 7 /* Bits in csum flags */
/* The number of MSIX messages the 82598 supports */
#define IXGBE_MSGS 18
/* For 6.X code compatibility */
#if !defined(ETHER_BPF_MTAP)
#define ETHER_BPF_MTAP BPF_MTAP
@ -199,9 +202,6 @@
#define IXGBE_CLEAN_PKT 2
#define IXGBE_CLEAN_ALL 3
/* Used for auto RX queue configuration */
extern int mp_ncpus;
/*
*****************************************************************************
* vendor_info_array
@ -253,7 +253,6 @@ struct tx_ring {
struct mtx tx_mtx;
u32 me;
u32 msix;
u32 eims;
u32 watchdog_timer;
union ixgbe_adv_tx_desc *tx_base;
volatile u32 tx_hwb;
@ -267,6 +266,13 @@ struct tx_ring {
u32 txd_cmd;
bus_dma_tag_t txtag;
char mtx_name[16];
#if __FreeBSD_version >= 800000
struct buf_ring *br;
#endif
/* Interrupt resources */
void *tag;
struct resource *res;
/* Soft Stats */
u32 no_tx_desc_avail;
u32 no_tx_desc_late;
@ -283,13 +289,14 @@ struct rx_ring {
struct mtx rx_mtx;
u32 me;
u32 msix;
u32 eims;
u32 payload;
struct task rx_task;
struct taskqueue *tq;
union ixgbe_adv_rx_desc *rx_base;
struct ixgbe_dma_alloc rxdma;
struct lro_ctrl lro;
bool lro_enabled;
bool hdr_split;
unsigned int last_cleaned;
unsigned int next_to_check;
struct ixgbe_rx_buf *rx_buffers;
@ -302,6 +309,10 @@ struct rx_ring {
u32 bytes; /* Used for AIM calc */
u32 eitr_setting;
/* Interrupt resources */
void *tag;
struct resource *res;
/* Soft stats */
u64 rx_irq;
u64 rx_split_packets;
@ -321,11 +332,12 @@ struct adapter {
struct resource *msix_mem;
/*
* Interrupt resources:
* Interrupt resources: this set is
* either used for legacy, or for Link
* when doing MSIX
*/
void *tag[IXGBE_MSGS];
struct resource *res[IXGBE_MSGS];
int rid[IXGBE_MSGS];
void *tag;
struct resource *res;
struct ifmedia media;
struct callout timer;
@ -334,6 +346,12 @@ struct adapter {
struct mtx core_mtx;
eventhandler_tag vlan_attach;
eventhandler_tag vlan_detach;
u32 num_vlans;
u16 num_queues;
/* Info about the board itself */
u32 part_num;
u32 optics;
@ -363,7 +381,6 @@ struct adapter {
*/
struct tx_ring *tx_rings;
int num_tx_desc;
int num_tx_queues;
/*
* Receive rings:
@ -371,14 +388,15 @@ struct adapter {
*/
struct rx_ring *rx_rings;
int num_rx_desc;
int num_rx_queues;
u32 rx_mask;
u64 rx_mask;
u32 rx_process_limit;
#ifdef IXGBE_TIMESYNC
u64 last_stamp;
u64 last_sec;
u32 last_ns;
#ifdef IXGBE_IEEE1588
/* IEEE 1588 precision time support */
struct cyclecounter cycles;
struct nettimer clock;
struct nettime_compare compare;
struct hwtstamp_ctrl hwtstamp;
#endif
/* Misc stats maintained by the driver */
@ -395,31 +413,12 @@ struct adapter {
struct ixgbe_hw_stats stats;
};
#ifdef IXGBE_TIMESYNC
/* Precision Time Sync (IEEE 1588) defines */
#define ETHERTYPE_IEEE1588 0x88F7
#define PICOSECS_PER_TICK 20833
#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
#define IXGBE_ADVTXD_TSTAMP 0x00080000
/* TIMESYNC IOCTL defines */
#define IXGBE_TIMESYNC_READTS _IOWR('i', 127, struct ixgbe_tsync_read)
#define IXGBE_TIMESTAMP 5 /* A unique return value */
/* Used in the READTS IOCTL */
struct ixgbe_tsync_read {
int read_current_time;
struct timespec system_time;
u64 network_time;
u64 rx_stamp;
u64 tx_stamp;
u16 seqid;
unsigned char srcid[6];
int rx_valid;
int tx_valid;
};
#endif /* IXGBE_TIMESYNC */
#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)

54
sys/dev/ixgbe/ixgbe_82598.c
View File

@ -69,6 +69,8 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data);
u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
/**
* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
@ -119,6 +121,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
&ixgbe_get_supported_physical_layer_82598;
mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
/* RAR, Multicast, VLAN */
mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
@ -416,7 +419,7 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
}
/* Configure pause time (2 TCs per register) */
reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
if ((packetbuf_num & 1) == 0)
reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
else
@ -675,6 +678,7 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
s32 phy_status = IXGBE_SUCCESS;
u32 ctrl;
u32 gheccr;
u32 i;
@ -722,13 +726,16 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
/* PHY ops must be identified and initialized prior to reset */
/* Init PHY and function pointers, perform SFP setup */
status = hw->phy.ops.init(hw);
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
phy_status = hw->phy.ops.init(hw);
if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
goto no_phy_reset;
hw->phy.ops.reset(hw);
}
no_phy_reset:
/*
* Prevent the PCI-E bus from from hanging by disabling PCI-E master
* access and verify no pending requests before reset
@ -777,16 +784,20 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
} else if (autoc != hw->mac.orig_autoc)
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
/* Store the permanent mac address */
hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table
*/
hw->mac.ops.init_rx_addrs(hw);
/* Store the permanent mac address */
hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
reset_hw_out:
if (phy_status != IXGBE_SUCCESS)
status = phy_status;
return status;
}
@ -1103,3 +1114,36 @@ u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
out:
return physical_layer;
}
/**
* ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
* port devices.
* @hw: pointer to the HW structure
*
* Calls common function and corrects issue with some single port devices
* that enable LAN1 but not LAN0.
**/
void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
{
struct ixgbe_bus_info *bus = &hw->bus;
u16 pci_gen, pci_ctrl2;
ixgbe_set_lan_id_multi_port_pcie(hw);
/* check if LAN0 is disabled */
hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
/* if LAN0 is completely disabled force function to 0 */
if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
!(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
!(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
bus->func = 0;
}
}
}

317
sys/dev/ixgbe/ixgbe_82599.c
View File

@ -82,6 +82,8 @@ s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps);
static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
{
@ -174,16 +176,27 @@ s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
if (ret_val != IXGBE_SUCCESS)
goto setup_sfp_out;
/* PHY config will finish before releasing the semaphore */
ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
if (ret_val != IXGBE_SUCCESS) {
ret_val = IXGBE_ERR_SWFW_SYNC;
goto setup_sfp_out;
}
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
while (data_value != 0xffff) {
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
IXGBE_WRITE_FLUSH(hw);
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
}
/* Now restart DSP */
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
IXGBE_WRITE_FLUSH(hw);
/* Now restart DSP by setting Restart_AN */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
(IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
/* Release the semaphore */
ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* Delay obtaining semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
}
setup_sfp_out:
@ -270,6 +283,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
mac->max_rx_queues = 128;
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
return ret_val;
}
@ -383,6 +397,7 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
switch (hw->device_id) {
case IXGBE_DEV_ID_82599_KX4:
case IXGBE_DEV_ID_82599_XAUI_LOM:
/* Default device ID is mezzanine card KX/KX4 */
media_type = ixgbe_media_type_backplane;
break;
@ -414,6 +429,7 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
u32 i;
s32 status = IXGBE_SUCCESS;
/* Restart link */
autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
@ -485,6 +501,7 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
u32 speedcnt = 0;
u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
u32 i = 0;
bool link_up = FALSE;
bool negotiation;
@ -495,6 +512,25 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
speed &= link_speed;
/* Set autoneg_advertised value based on input link speed */
hw->phy.autoneg_advertised = 0;
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
/*
* When the driver changes the link speeds that it can support,
* it sets autotry_restart to TRUE to indicate that we need to
* initiate a new autotry session with the link partner. To do
* so, we set the speed then disable and re-enable the tx laser, to
* alert the link partner that it also needs to restart autotry on its
* end. This is consistent with TRUE clause 37 autoneg, which also
* involves a loss of signal.
*/
/*
* Try each speed one by one, highest priority first. We do this in
* software because 10gb fiber doesn't support speed autonegotiation.
@ -511,7 +547,7 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
goto out;
/* Set hardware SDP's */
/* Set the module link speed */
esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
@ -524,15 +560,35 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
if (status != IXGBE_SUCCESS)
goto out;
msec_delay(100);
/* Flap the tx laser if it has not already been done */
if (hw->mac.autotry_restart) {
/* Disable tx laser; allow 100us to go dark per spec */
esdp_reg |= IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
usec_delay(100);
/* If we have link, just jump out */
status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
if (status != IXGBE_SUCCESS)
goto out;
/* Enable tx laser; allow 2ms to light up per spec */
esdp_reg &= ~IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
msec_delay(2);
if (link_up)
goto out;
hw->mac.autotry_restart = FALSE;
}
/* The controller may take up to 500ms at 10g to acquire link */
for (i = 0; i < 5; i++) {
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
status = ixgbe_check_link(hw, &link_speed,
&link_up, FALSE);
if (status != IXGBE_SUCCESS)
goto out;
if (link_up)
goto out;
}
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
@ -548,7 +604,7 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
goto out;
/* Set hardware SDP's */
/* Set the module link speed */
esdp_reg &= ~IXGBE_ESDP_SDP5;
esdp_reg |= IXGBE_ESDP_SDP5_DIR;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
@ -562,6 +618,22 @@ s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
if (status != IXGBE_SUCCESS)
goto out;
/* Flap the tx laser if it has not already been done */
if (hw->mac.autotry_restart) {
/* Disable tx laser; allow 100us to go dark per spec */
esdp_reg |= IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
usec_delay(100);
/* Enable tx laser; allow 2ms to light up per spec */
esdp_reg &= ~IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
msec_delay(2);
hw->mac.autotry_restart = FALSE;
}
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
@ -654,6 +726,7 @@ s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
s32 status = IXGBE_SUCCESS;
u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
u32 start_autoc = autoc;
u32 orig_autoc = 0;
u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
@ -669,16 +742,18 @@ s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
speed &= link_capabilities;
if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
status = IXGBE_ERR_LINK_SETUP;
goto out;
}
/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
if (hw->mac.orig_link_settings_stored)
orig_autoc = hw->mac.orig_autoc;
else
orig_autoc = autoc;
if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
status = IXGBE_ERR_LINK_SETUP;
} else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
/* Set KX4/KX/KR support according to speed requested */
@ -712,7 +787,8 @@ s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
}
}
if (status == IXGBE_SUCCESS) {
if (autoc != start_autoc) {
/* Restart link */
autoc |= IXGBE_AUTOC_AN_RESTART;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
@ -893,6 +969,9 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
}
}
/* Store the permanent mac address */
hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table. Also reset num_rar_entries to 128,
@ -901,8 +980,7 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
hw->mac.num_rar_entries = 128;
hw->mac.ops.init_rx_addrs(hw);
/* Store the permanent mac address */
hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
/* Store the permanent SAN mac address */
hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
@ -1076,13 +1154,14 @@ s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
u32 bitindex;
u32 bits;
u32 first_empty_slot;
u32 vt;
if (vlan > 4095)
return IXGBE_ERR_PARAM;
/*
* this is a 2 part operation - first the VFTA, then the
* VLVF and VLVFB if vind is set
* VLVF and VLVFB if VT Mode is set
*/
/* Part 1
@ -1102,14 +1181,15 @@ s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
/* Part 2
* If the vind is set
* If VT Mode is set
* Either vlan_on
* make sure the vlan is in VLVF
* set the vind bit in the matching VLVFB
* Or !vlan_on
* clear the pool bit and possibly the vind
*/
if (vind) {
vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
if (vt & IXGBE_VT_CTL_VT_ENABLE) {
/* find the vlanid or the first empty slot */
first_empty_slot = 0;
@ -1134,46 +1214,49 @@ s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
if (vlan_on) {
/* set the pool bit */
if (vind < 32) {
bits =
IXGBE_READ_REG(hw, IXGBE_VLVFB(regindex*2));
bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB(regindex*2));
bits |= (1 << vind);
IXGBE_WRITE_REG(hw,
IXGBE_VLVFB(regindex*2), bits);
IXGBE_VLVFB(regindex*2),
bits);
} else {
bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB((regindex*2)+1));
IXGBE_VLVFB((regindex*2)+1));
bits |= (1 << vind);
IXGBE_WRITE_REG(hw,
IXGBE_VLVFB((regindex*2)+1), bits);
IXGBE_VLVFB((regindex*2)+1),
bits);
}
} else {
/* clear the pool bit */
if (vind < 32) {
bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB(regindex*2));
bits &= ~(1 << vind);
IXGBE_WRITE_REG(hw,
IXGBE_VLVFB(regindex*2), bits);
bits |= IXGBE_READ_REG(hw,
IXGBE_VLVFB((regindex*2)+1));
} else {
bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB((regindex*2)+1));
IXGBE_VLVFB(regindex*2));
bits &= ~(1 << vind);
IXGBE_WRITE_REG(hw,
IXGBE_VLVFB((regindex*2)+1), bits);
IXGBE_VLVFB(regindex*2),
bits);
bits |= IXGBE_READ_REG(hw,
IXGBE_VLVFB(regindex*2));
IXGBE_VLVFB((regindex*2)+1));
} else {
bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB((regindex*2)+1));
bits &= ~(1 << vind);
IXGBE_WRITE_REG(hw,
IXGBE_VLVFB((regindex*2)+1),
bits);
bits |= IXGBE_READ_REG(hw,
IXGBE_VLVFB(regindex*2));
}
}
if (bits)
IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
(IXGBE_VLVF_VIEN | vlan));
(IXGBE_VLVF_VIEN | vlan));
else
IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
}
out:
return IXGBE_SUCCESS;
}
@ -1221,16 +1304,75 @@ s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
**/
s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
{
int i;
u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
/*
* Before starting reinitialization process,
* FDIRCMD.CMD must be zero.
*/
for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
IXGBE_FDIRCMD_CMD_MASK))
break;
usec_delay(10);
}
if (i >= IXGBE_FDIRCMD_CMD_POLL) {
DEBUGOUT("Flow Director previous command isn't complete, "
"aborting table re-initialization. \n");
return IXGBE_ERR_FDIR_REINIT_FAILED;
}
IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
IXGBE_WRITE_FLUSH(hw);
/*
* 82599 adapters flow director init flow cannot be restarted,
* Workaround 82599 silicon errata by performing the following steps
* before re-writing the FDIRCTRL control register with the same value.
* - write 1 to bit 8 of FDIRCMD register &
* - write 0 to bit 8 of FDIRCMD register
*/
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
~IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
/*
* Clear FDIR Hash register to clear any leftover hashes
* waiting to be programmed.
*/
IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
IXGBE_WRITE_FLUSH(hw);
IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
IXGBE_WRITE_FLUSH(hw);
/* Poll init-done after we write FDIRCTRL register */
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
IXGBE_FDIRCTRL_INIT_DONE)
break;
usec_delay(10);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
DEBUGOUT("Flow Director Signature poll time exceeded!\n");
return IXGBE_ERR_FDIR_REINIT_FAILED;
}
/* Clear FDIR statistics registers (read to clear) */
IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
return IXGBE_SUCCESS;
}
#define IXGBE_FDIR_INIT_DONE_POLL 10
/**
* ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
* @hw: pointer to hardware structure
@ -1456,6 +1598,7 @@ u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
*/
union {
u64 fill[6];
u32 key[11];
u8 key_stream[44];
} tmp_key;
@ -1464,23 +1607,30 @@ u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
u8 int_key[44]; /* upper-most bit unused */
u8 hash_str[46]; /* upper-most 2 bits unused */
u16 hash_result = 0;
u16 tmp = 0;
int i, j, k, h;
memset(&tmp_key, 0, sizeof(tmp_key));
/*
* Initialize the fill member to prevent warnings
* on some compilers
*/
tmp_key.fill[0] = 0;
/* First load the temporary key stream */
for (i = 0; i < 11; i++)
tmp_key.key[i] = key;
for (i = 0; i < 6; i++) {
u64 fillkey = ((u64)key << 32) | key;
tmp_key.fill[i] = fillkey;
}
/*
* Set the interim key for the hashing. Bit 352 is unused, so we must
* shift and compensate when building the key.
*/
int_key[0] = tmp_key.key_stream[0] >> 1;
for (i = 1, j = 0; i < 44; i++) {
int_key[i] = (tmp_key.key_stream[j] & 0x1) << 7;
unsigned int this_key = tmp_key.key_stream[j] << 7;
j++;
int_key[i] |= tmp_key.key_stream[j] >> 1;
int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
}
/*
@ -1489,11 +1639,11 @@ u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
*/
hash_str[0] = (stream[40] & 0x7f) >> 1;
for (i = 1, j = 40; i < 46; i++) {
hash_str[i] = (stream[j] & 0x1) << 7;
unsigned int this_str = stream[j] << 7;
j++;
if (j > 41)
j = 0;
hash_str[i] |= stream[j] >> 1;
hash_str[i] = (u8)(this_str | (stream[j] >> 1));
}
/*
@ -1503,7 +1653,7 @@ u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
*/
for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
for (h = 0; h < 8 && k < 351; h++, k++) {
if ((int_key[j] >> h) & 0x1) {
if (int_key[j] & (1 << h)) {
/*
* Key bit is set, XOR in the current 16-bit
* string. Example of processing:
@ -1518,11 +1668,11 @@ u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
* (hash_str[i - 1] & 0xff << 1) |
* (hash_str[i] & 0x80 >> 7)
*/
tmp = ((hash_str[i] & (0xff << h)) >> h);
tmp |= ((hash_str[i - 1] & 0xff) << (8 - h));
tmp |= (hash_str[i - 2] & (0xff >> (8 - h)))
<< (16 - h);
hash_result ^= tmp;
int tmp = (hash_str[i] >> h);
tmp |= (hash_str[i - 1] << (8 - h));
tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
<< (16 - h);
hash_result ^= (u16)tmp;
}
}
}
@ -2139,6 +2289,11 @@ s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
}
IXGBE_WRITE_FLUSH(hw);
/* We need to run link autotry after the driver loads */
hw->mac.autotry_restart = TRUE;
if (ret_val == IXGBE_SUCCESS)
ret_val = ixgbe_verify_fw_version_82599(hw);
return ret_val;
}
@ -2220,6 +2375,8 @@ u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
goto out;
break;
case IXGBE_AUTOC_LMS_10G_SERIAL:
@ -2442,3 +2599,51 @@ s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
san_mac_addr_out:
return status;
}
/**
* ixgbe_verify_fw_version_82599 - verify fw version for 82599
* @hw: pointer to hardware structure
*
* Verifies that installed the firmware version is 0.6 or higher
* for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
*
* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
* if the FW version is not supported.
**/
static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM_VERSION;
u16 fw_offset, fw_ptp_cfg_offset;
u16 fw_version = 0;
/* firmware check is only necessary for SFI devices */
if (hw->phy.media_type != ixgbe_media_type_fiber) {
status = IXGBE_SUCCESS;
goto fw_version_out;
}
/* get the offset to the Firmware Module block */
hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
if ((fw_offset == 0) || (fw_offset == 0xFFFF))
goto fw_version_out;
/* get the offset to the Pass Through Patch Configuration block */
hw->eeprom.ops.read(hw, (fw_offset +
IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
&fw_ptp_cfg_offset);
if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
goto fw_version_out;
/* get the firmware version */
hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
IXGBE_FW_PATCH_VERSION_4),
&fw_version);
if (fw_version > 0x5)
status = IXGBE_SUCCESS;
fw_version_out:
return status;
}

30
sys/dev/ixgbe/ixgbe_api.c
View File

@ -103,6 +103,7 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
hw->mac.type = ixgbe_mac_82598EB;
break;
case IXGBE_DEV_ID_82599_KX4:
case IXGBE_DEV_ID_82599_XAUI_LOM:
case IXGBE_DEV_ID_82599_SFP:
case IXGBE_DEV_ID_82599_CX4:
hw->mac.type = ixgbe_mac_82599EB;
@ -935,3 +936,32 @@ s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
(hw, regval), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to acquire
*
* Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
{
return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
(hw, mask), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_release_swfw_semaphore - Release SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to release
*
* Releases the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
{
if (hw->mac.ops.release_swfw_sync)
hw->mac.ops.release_swfw_sync(hw, mask);
}

3
sys/dev/ixgbe/ixgbe_api.h
View File

@ -162,5 +162,8 @@ s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
#endif /* _IXGBE_API_H_ */

60
sys/dev/ixgbe/ixgbe_common.c
View File

@ -87,6 +87,8 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
/* LEDs */
mac->ops.led_on = &ixgbe_led_on_generic;
@ -792,13 +794,10 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM;
u32 timeout;
u32 timeout = 2000;
u32 i;
u32 swsm;
/* Set timeout value based on size of EEPROM */
timeout = hw->eeprom.word_size + 1;
/* Get SMBI software semaphore between device drivers first */
for (i = 0; i < timeout; i++) {
/*
@ -1078,6 +1077,9 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
/* Delay before attempt to obtain semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
}
/**
@ -1633,6 +1635,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
s32 ret_val = IXGBE_SUCCESS;
u32 mflcn_reg, fccfg_reg;
u32 reg;
u32 rx_pba_size;
DEBUGFUNC("ixgbe_fc_enable_generic");
@ -1699,22 +1702,41 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
/* Set up and enable Rx high/low water mark thresholds, enable XON. */
if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
if (hw->fc.send_xon) {
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
(hw->fc.low_water | IXGBE_FCRTL_XONE));
} else {
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
hw->fc.low_water);
}
reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
/* Thresholds are different for link flow control when in DCB mode */
if (reg & IXGBE_MTQC_RT_ENA) {
rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
(hw->fc.high_water | IXGBE_FCRTH_FCEN));
/* Always disable XON for LFC when in DCB mode */
reg = (rx_pba_size >> 5) & 0xFFE0;
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
reg = (rx_pba_size >> 2) & 0xFFE0;
if (hw->fc.current_mode & ixgbe_fc_tx_pause)
reg |= IXGBE_FCRTH_FCEN;
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
} else {
/* Set up and enable Rx high/low water mark thresholds,
* enable XON. */
if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
if (hw->fc.send_xon) {
IXGBE_WRITE_REG(hw,
IXGBE_FCRTL_82599(packetbuf_num),
(hw->fc.low_water |
IXGBE_FCRTL_XONE));
} else {
IXGBE_WRITE_REG(hw,
IXGBE_FCRTL_82599(packetbuf_num),
hw->fc.low_water);
}
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
(hw->fc.high_water | IXGBE_FCRTH_FCEN));
}
}
/* Configure pause time (2 TCs per register) */
reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
if ((packetbuf_num & 1) == 0)
reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
else
@ -2043,9 +2065,6 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
ixgbe_release_eeprom_semaphore(hw);
/* Delay before attempt to obtain semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
}
/**
@ -2081,6 +2100,8 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
if (!link_up) {
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
autoc_reg |= IXGBE_AUTOC_FLU;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
msec_delay(10);
@ -2104,6 +2125,7 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
autoc_reg &= ~IXGBE_AUTOC_FLU;
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);

2
sys/dev/ixgbe/ixgbe_osdep.h
View File

@ -83,6 +83,8 @@
#define true 1
#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
#define PCI_COMMAND_REGISTER PCIR_COMMAND
#define UNREFERENCED_PARAMETER(_p)
#define IXGBE_HTONL htonl

59
sys/dev/ixgbe/ixgbe_phy.c
View File

@ -444,7 +444,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
**/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
s32 status = IXGBE_NOT_IMPLEMENTED;
s32 status = IXGBE_SUCCESS;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@ -485,7 +485,6 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
status = IXGBE_SUCCESS;
break;
}
}
@ -760,9 +759,15 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
u8 comp_codes_1g = 0;
u8 comp_codes_10g = 0;
u8 oui_bytes[3] = {0, 0, 0};
u8 transmission_media = 0;
u8 cable_tech = 0;
u16 enforce_sfp = 0;
if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
status = IXGBE_ERR_SFP_NOT_PRESENT;
goto out;
}
status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
&identifier);
@ -779,13 +784,16 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
/* LAN ID is needed for sfp_type determination */
hw->mac.ops.set_lan_id(hw);
if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
hw->phy.type = ixgbe_phy_sfp_unsupported;
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
} else {
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
&comp_codes_1g);
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
&comp_codes_10g);
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
&transmission_media);
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
&cable_tech);
/* ID Module
* =========
@ -798,7 +806,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
* 6 SFP_SR/LR_CORE1 - 82599-specific
*/
if (hw->mac.type == ixgbe_mac_82598EB) {
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
hw->phy.sfp_type = ixgbe_sfp_type_sr;
@ -807,7 +815,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
else
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
} else if (hw->mac.type == ixgbe_mac_82599EB) {
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
ixgbe_sfp_type_da_cu_core0;
@ -836,6 +844,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
hw->phy.sfp_setup_needed = TRUE;
/* Determine if the SFP+ PHY is dual speed or not. */
hw->phy.multispeed_fiber = FALSE;
if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
(comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
@ -861,8 +870,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
switch (vendor_oui) {
case IXGBE_SFF_VENDOR_OUI_TYCO:
if (transmission_media &
IXGBE_SFF_TWIN_AX_CAPABLE)
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
hw->phy.type = ixgbe_phy_tw_tyco;
break;
case IXGBE_SFF_VENDOR_OUI_FTL:
@ -875,8 +883,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
hw->phy.type = ixgbe_phy_sfp_intel;
break;
default:
if (transmission_media &
IXGBE_SFF_TWIN_AX_CAPABLE)
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
hw->phy.type = ixgbe_phy_tw_unknown;
else
hw->phy.type = ixgbe_phy_sfp_unknown;
@ -884,16 +891,21 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
}
}
/* All passive DA cables are supported */
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
status = IXGBE_SUCCESS;
goto out;
}
/* 1G SFP modules are not supported */
if (comp_codes_10g == 0) {
hw->phy.type = ixgbe_phy_sfp_unsupported;
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
goto out;
}
if (hw->mac.type == ixgbe_mac_82598EB ||
(hw->phy.sfp_type != ixgbe_sfp_type_sr &&
hw->phy.sfp_type != ixgbe_sfp_type_lr &&
hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 &&
hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) {
/* Anything else 82598-based is supported */
if (hw->mac.type == ixgbe_mac_82598EB) {
status = IXGBE_SUCCESS;
goto out;
}
@ -1031,7 +1043,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
{
s32 status = IXGBE_SUCCESS;
u32 max_retry = 1;
u32 max_retry = 10;
u32 retry = 0;
u16 swfw_mask = 0;
bool nack = 1;
@ -1043,12 +1055,13 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
else
swfw_mask = IXGBE_GSSR_PHY0_SM;
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out;
}
do {
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out;
}
ixgbe_i2c_start(hw);
/* Device Address and write indication */
@ -1091,6 +1104,8 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
break;
fail:
ixgbe_release_swfw_sync(hw, swfw_mask);
msec_delay(100);
ixgbe_i2c_bus_clear(hw);
retry++;
if (retry < max_retry)

4
sys/dev/ixgbe/ixgbe_phy.h
View File

@ -46,10 +46,10 @@
#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
#define IXGBE_SFF_1GBE_COMP_CODES 0x6
#define IXGBE_SFF_10GBE_COMP_CODES 0x3
#define IXGBE_SFF_TRANSMISSION_MEDIA 0x9
#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
/* Bitmasks */
#define IXGBE_SFF_TWIN_AX_CAPABLE 0x80
#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
#define IXGBE_SFF_10GBASESR_CAPABLE 0x10

60
sys/dev/ixgbe/ixgbe_type.h
View File

@ -37,6 +37,7 @@
#include "ixgbe_osdep.h"
/* Vendor ID */
#define IXGBE_INTEL_VENDOR_ID 0x8086
@ -55,6 +56,7 @@
#define IXGBE_DEV_ID_82599_KX4 0x10F7
#define IXGBE_DEV_ID_82599_CX4 0x10F9
#define IXGBE_DEV_ID_82599_SFP 0x10FB
#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
/* General Registers */
#define IXGBE_CTRL 0x00000
@ -280,6 +282,7 @@
#define IXGBE_DTXCTL 0x07E00
#define IXGBE_DMATXCTL 0x04A80
#define IXGBE_PFDTXGSWC 0x08220
#define IXGBE_DTXMXSZRQ 0x08100
#define IXGBE_DTXTCPFLGL 0x04A88
#define IXGBE_DTXTCPFLGH 0x04A8C
@ -290,6 +293,8 @@
#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
/* Tx DCA Control register : 128 of these (0-127) */
#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
@ -711,14 +716,6 @@
#define IXGBE_PBACLR_82599 0x11068
#define IXGBE_CIAA_82599 0x11088
#define IXGBE_CIAD_82599 0x1108C
#define IXGBE_PCIE_DIAG_0_82599 0x11090
#define IXGBE_PCIE_DIAG_1_82599 0x11094
#define IXGBE_PCIE_DIAG_2_82599 0x11098
#define IXGBE_PCIE_DIAG_3_82599 0x1109C
#define IXGBE_PCIE_DIAG_4_82599 0x110A0
#define IXGBE_PCIE_DIAG_5_82599 0x110A4
#define IXGBE_PCIE_DIAG_6_82599 0x110A8
#define IXGBE_PCIE_DIAG_7_82599 0x110C0
#define IXGBE_INTRPT_CSR_82599 0x110B0
#define IXGBE_INTRPT_MASK_82599 0x110B8
#define IXGBE_CDQ_MBR_82599 0x110B4
@ -785,10 +782,20 @@
#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
#define IXGBE_PCIEECCCTL 0x1106C
#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
#define IXGBE_PCIEECCCTL0 0x11100
#define IXGBE_PCIEECCCTL1 0x11104
#define IXGBE_RXDBUECC 0x03F70
#define IXGBE_TXDBUECC 0x0CF70
#define IXGBE_RXDBUEST 0x03F74
#define IXGBE_TXDBUEST 0x0CF74
#define IXGBE_PBTXECC 0x0C300
#define IXGBE_PBRXECC 0x03300
#define IXGBE_GHECCR 0x110B0
@ -1108,6 +1115,8 @@
/* VFRE bitmask */
#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
/* RDHMPN and TDHMPN bitmasks */
#define IXGBE_RDHMPN_RDICADDR 0x007FF800
#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
@ -1351,6 +1360,7 @@
/* VLAN pool filtering masks */
#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
#define IXGBE_VLVF_ENTRIES 64
#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
@ -1363,8 +1373,10 @@
#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
/* ESDP Bit Masks */
#define IXGBE_ESDP_SDP0 0x00000001
#define IXGBE_ESDP_SDP1 0x00000002
#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
@ -1537,6 +1549,7 @@
#define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_SAN_MAC_ADDR_PTR 0x28
#define IXGBE_DEVICE_CAPS 0x2C
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
@ -1580,10 +1593,17 @@
#define IXGBE_EERD_ATTEMPTS 100000
#endif
#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
#define IXGBE_FW_PATCH_VERSION_4 0x7
/* PCI Bus Info */
#define IXGBE_PCI_LINK_STATUS 0xB2
@ -1636,6 +1656,7 @@
/* Transmit Config masks */
#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
/* Enable short packet padding to 64 bytes */
#define IXGBE_TX_PAD_ENABLE 0x00000400
#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
@ -1782,6 +1803,7 @@
#define IXGBE_PSRTYPE_UDPHDR 0x00000020
#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
#define IXGBE_PSRTYPE_L2HDR 0x00001000
/* SRRCTL bit definitions */
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
@ -1875,6 +1897,12 @@
#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
/* SR-IOV specific macros */
#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
/* Little Endian defines */
#ifndef __le16
#define __le16 u16
@ -1947,6 +1975,7 @@ enum ixgbe_fdir_pballoc_type {
#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
@ -1957,6 +1986,7 @@ enum ixgbe_fdir_pballoc_type {
#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
#define IXGBE_FDIRCMD_IPV6 0x00000080
#define IXGBE_FDIRCMD_CLEARHT 0x00000100
#define IXGBE_FDIRCMD_DROP 0x00000200
#define IXGBE_FDIRCMD_INT 0x00000400
#define IXGBE_FDIRCMD_LAST 0x00000800
@ -1964,6 +1994,8 @@ enum ixgbe_fdir_pballoc_type {
#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
#define IXGBE_FDIR_INIT_DONE_POLL 10
#define IXGBE_FDIRCMD_CMD_POLL 10
/* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc {
@ -2134,6 +2166,7 @@ typedef u32 ixgbe_physical_layer;
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
/* Software ATR hash keys */
#define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
@ -2421,6 +2454,8 @@ struct ixgbe_mac_operations {
s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
s32 (*setup_sfp)(struct ixgbe_hw *);
s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
void (*release_swfw_sync)(struct ixgbe_hw *, u16);
/* Link */
s32 (*setup_link)(struct ixgbe_hw *);
@ -2504,6 +2539,7 @@ struct ixgbe_mac_info {
bool orig_link_settings_stored;
bool autoneg;
bool autoneg_succeeded;
bool autotry_restart;
};
struct ixgbe_phy_info {
@ -2541,6 +2577,7 @@ struct ixgbe_hw {
#define ixgbe_call_func(hw, func, params, error) \
(func != NULL) ? func params : error
/* Error Codes */
#define IXGBE_SUCCESS 0
#define IXGBE_ERR_EEPROM -1
@ -2565,8 +2602,9 @@ struct ixgbe_hw {
#define IXGBE_ERR_SFP_NOT_PRESENT -20
#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
#define IXGBE_ERR_FDIR_REINIT_FAILED -23
#define IXGBE_ERR_EEPROM_VERSION -24
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#define UNREFERENCED_PARAMETER(_p)
#endif /* _IXGBE_TYPE_H_ */

2
sys/modules/ixgbe/Makefile
View File

@ -6,7 +6,7 @@ SRCS += ixgbe.c
# Shared source
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c
SRCS += ixgbe_82599.c ixgbe_82598.c
CFLAGS+= -I${.CURDIR}/../../dev/ixgbe
CFLAGS+= -I${.CURDIR}/../../dev/ixgbe -DSMP
clean:
rm -f device_if.h bus_if.h pci_if.h setdef* *_StripErr