Merge commit 241cbf201 from llvm git (by Nemanja Ivanovic):
[PowerPC] Fix crash in peephole optimization When converting reg+reg shifts to reg+imm rotates, we neglect to consider the CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a rotate with missing operands which causes a crash. Committing this fix without review since it is non-controversial that the list of mnemonics to consider should include the 64-bit aliases for the exact mnemonics. Fixes PR44183. This should fix "Assertion failed: (idx < size()), function operator[], file /usr/src/contrib/llvm/include/llvm/ADT/SmallVector.h, line 153" when building the graphics/mesa-dri port for the PowerPC64 ELFv2 ABI. Reported by: Alfredo Dal'Ava Júnior <alfredo.junior@eldorado.org.br> MFC after: 1 month X-MFC-With: r353358
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=355397
@ -3529,8 +3529,10 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
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ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
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unsigned Opc = MI.getOpcode();
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bool SpecialShift32 =
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Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
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bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLWo ||
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Opc == PPC::SRW || Opc == PPC::SRWo ||
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Opc == PPC::SLW8 || Opc == PPC::SLW8o ||
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Opc == PPC::SRW8 || Opc == PPC::SRW8o;
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bool SpecialShift64 =
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Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
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bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
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