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Restructure cache_handle_range to avoid repeated barriers. Specifically,

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restructure cache_handle_range so that all of the data cache operations are
performed before any instruction cache operations.  Then, we only need one
barrier between the data and instruction cache operations and one barrier
after the instruction cache operations.

On an Amazon EC2 a1.2xlarge instance, this simple change reduces the time
for a "make -j8 buildworld" by 9%.

Reviewed by:	andrew
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D20848
This commit is contained in:
Alan Cox 2019-07-05 20:01:06 +00:00
parent 56948d177e
commit d8d0bf06a7
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=349768
1 changed files with 12 additions and 6 deletions
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18
sys/arm64/arm64/cpufunc_asm.S
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@ -51,7 +51,7 @@ __FBSDID("$FreeBSD$");
/*
* Macro to handle the cache. This takes the start address in x0, length
* in x1. It will corrupt x0, x1, x2, and x3.
* in x1. It will corrupt x0, x1, x2, x3, and x4.
*/
.macro cache_handle_range dcop = 0, ic = 0, icop = 0
.if \ic == 0
@ -64,17 +64,23 @@ __FBSDID("$FreeBSD$");
and x2, x0, x4 /* Get the low bits of the address */
add x1, x1, x2 /* Add these to the size */
bic x0, x0, x4 /* Clear the low bit of the address */
.if \ic != 0
mov x2, x0 /* Save the address */
mov x4, x1 /* Save the size */
.endif
1:
dc \dcop, x0
dsb ish
.if \ic != 0
ic \icop, x0
dsb ish
.endif
add x0, x0, x3 /* Move to the next line */
subs x1, x1, x3 /* Reduce the size */
b.hi 1b /* Check if we are done */
dsb ish
.if \ic != 0
2:
ic \icop, x2
add x2, x2, x3 /* Move to the next line */
subs x4, x4, x3 /* Reduce the size */
b.hi 2b /* Check if we are done */
dsb ish
isb
.endif
.endm